S3C9228/P9228

8-BIT CMOS

MICROCONTROLLERS

USER'S MANUAL

Revision 1

Important Notice

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Preface

The S3C9228/P9228 Microcontrollers User's Manual is designed for application designers and programmers who are using the S3C9228/P9228 microcontrollers for application development. It is organized in two main parts:

Part I contains software-related information to familiarize you with the microcontroller's architecture, programming model, instruction set, and interrupt structure. It has six chapters:

Chapter 1, "Product Overview," is a high-level introduction to the 100% with general product descriptions, as well as detailed information about individual pin characteristics and pin circuit types.

Chapter 2, "Address Spaces," explains the 100% program and data memory, internal register file, and mapped control register, and explains how to address them. Chapter 2 also describes working register addressing, as well as system stack and user-defined stack operations.

Chapter 3, "Addressing Modes," contains detailed descriptions of the addressing modes that are supported by the CPU.

Chapter 4, "Control Registers," contains overview tables for all mapped system and peripheral control register values, as well as detailed one-page descriptions in standard format. You can use these easy-to-read, alphabetically organized, register descriptions as a quick-reference source when writing programs.

Chapter 5, "Interrupt Structure," describes the 100% interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part II.

Chapter 6, "SAM88RCRI Instruction Set," describes the features and conventions of the instruction set used for all S3C9-series microcontrollers. Several summary tables are presented for orientation and reference. Detailed descriptions of each instruction are presented in a standard format. Each instruction description includes one or more practical examples of how to use the instruction when writing an application program.

A basic familiarity with the information in Part I will help you to understand the hardware module descriptions in Part II. If you are not yet familiar with the SAM8 product family and are reading this manual for the first time, we recommend that you first read chapters 1???3 carefully. Then, briefly look over the detailed information in chapters 4, 5, and 6. Later, you can reference the information in Part I as necessary.

Part II "hardware Descriptions," has detailed information about specific hardware components of the S3C9228/P9228 microcontrollers. Also included in Part II are electrical, mechanical, OTP, and development tools data. It has 13 chapters:

Two order forms are included at the back of this manual to facilitate customer order for S3C9228/P9228 microcontrollers: the Mask ROM Order Form, and the Mask Option Selection Form. You can photocopy these forms, fill them out, and then forward them to your local Samsung Sales Representative.

Table of Contents (Continued)

Table of Contents (Continued)

List of Figures

List of Figures (Continued)

List of Figures (Continued)

List of Figures (Concluded)

List of Tables

List of Programming Tips

List of Register Descriptions

List of Instruction Descriptions

1 PRODUCT OVERVIEW

SAM88RCRI PRODUCT FAMILY

Samsung's SAM88RCRIfamily of 8-bit single-chip CMOS microcontrollers offer fast and efficient CPU, a wide range of integrated peripherals, and supports OTP device.

A dual address/data bus architecture and bit- or nibble-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time operations.

S3C9228/P9228 MICROCONTROLLER

The S3C9228 can be used for dedicated control functions in a variety of applications, and is especially designed for application with FRS or etc.

The S3C9228/P9228 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built around the powerful SAM88RCRI CPU core.

Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register space, the size of the internal register file was logically expanded. The S3C9228/P9228 has 8K-byte of program ROM, and 264-byte of RAM (including 16-byte of working register and 20-byte LCD display RAM).

Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core:

???7 configurable I/O ports including ports shared with segment/common drive outputs

???10-bit programmable pins for external interrupts

???One 8-bit basic timer for oscillation stabilization and watch-dog functions

???Two 8-bit timer/counters with selectable operating modes

???Watch timer for real time

???4 channel A/D converter

???8-bit serial I/O interface

OTP

The S3C9228 microcontroller is also available in OTP (One Time Programmable) version. S3P9228 microcontroller has an on-chip 8K-byte one-time-programmable EPROM instead of masked ROM. The S3P9228 is comparable to S3C9228, both in function and in pin configuration.

1-1

1-2

BLOCK DIAGRAM

Figure 1-1. Block Diagram

1-3

PIN ASSIGNMENTS

Figure 1-2. S3C9228 44-QFP Pin Assignments

1-4

Figure 1-3. S3C9228 42-SDIP Pin Assignments

1-5

PIN DESCRIPTIONS

Table 1-1. Pin Descriptions

NOTE: Parentheses indicate pin number for 42-SDIP-600 package.

1-6

S3C9228/P9228PRODUCT OVERVIEW

Table 1-1. Pin Descriptions (Continued)

NOTE: Parentheses indicate pin number for 42-SDIP-600 package.

1-7

PIN CIRCUIT DIAGRAMS

VDD

Pull-Up

Resistor

RESET Noise Filter

Figure 1-4. Pin Circuit Type B

VDD

Data

Output

Output

Disable

VSS

Figure 1-5. Pin Circuit Type C

1-8

External

Interrupt

Input

Figure 1-7. Pin Circuit Type E-4

Figure 1-8. Pin Circuit Type F-16A

1-9

VLC1

VLC2

VLC3

Output

Disable

VLC4

VLC5

VSS

Figure 1-9. Pin Circuit Type H-23

1-10

1-11

1-12

2 ADDRESS SPACES

OVERVIEW

The S3C9228/P9228 microcontroller has three kinds of address space:

???Program memory (ROM)

???Internal register file

???LCD display register file

A 16-bit address bus supports program memory operations. Special instructions and related internal logic determine when the 16-bit bus carries addresses for program memory. A separate 8-bit register bus carries addresses and data between the CPU and the internal register file.

The S3C9228 has 8K bytes of mask-programmable program memory on-chip. The S3C9228/P9228 microcontroller has 244 bytes general-purpose registers in its internal register file and the 20 bytes for LCD display memory is implemented in the internal register file too. Fifty-six bytes in the register file are mapped for system and peripheral control functions.

2-1

PROGRAM MEMORY (ROM)

Program memory (ROM) stores program code or table data. The S3C9228 has 8K bytes of mask-programable program memory. The program memory address range is therefore 0H-1FFFH. The first 2 bytes of the ROM (0000H???0001H) are an interrupt vector address. The program reset address in the ROM is 0100H.

8K bytes Internal Program Memory Area

Figure 2-1. S3C9228/P9228 Program Memory Address Space

2-2

REGISTER ARCHITECTURE

The upper 72 bytes of the S3C9228/P9228's internal register file are addressed as working registers, system control registers and peripheral control registers. The lower 184 bytes of internal register file (00H???B7H) is called the general purpose register space.

For many SAM88RCRI microcontrollers, the addressable area of the internal register file is further expanded by the additional of one or more register pages at general purpose register space (00H???BFH). This register file expansion is implemented by page 1 in the S3C9228/P9228. The page 1 (20 ?? 8 bits) is for LCD display register and can be used as general-purpose registers.

Figure 2-2. Internal Register File Organization

2-3

COMMON WORKING REGISTER AREA (C0H???CFH)

The SAM88RCRI register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time.

This16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file. Typically, these working registers serve as temporary buffers for data operations between different pages.

The Register (R) addressing mode can be used to access this area

Registers are addressed either as a single 8-bit register or as a paired 16-bit register. In 16-bit register pairs, the address of the first 8-bit register is always an even number and the address of the next register is an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register.

Figure 2-3. 16-Bit Register Pairs

+ PROGRAMMING TIP ??? Addressing the Common Working Register Area

As the following examples show, you should access working registers in the common area, locations C0H???CFH, using working register addressing mode only.

2-4

SYSTEM STACK

S3C9-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system stack operations. The S3C9228/P9228 architecture supports stack operations in the internal register file.

STACK OPERATIONS

Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their original locations. The stack address is always decremented before a push operation and incremented after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-4.

Figure 2-4. Stack Operations

STACK POINTER (SP)

Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset, the SP value is undetermined.

Because only internal memory space is implemented in the S3C9228/P9228, the SP must be initialized to an 8- bit value in the range 00H???B7H.

NOTE

In case a Stack Pointer is initialized to 00H, it is decreased to FFH when stack operation starts. This means that a Stack Pointer access invalid stack area.

2-5

+PROGRAMMING TIP ??? Standard Stack Operations Using PUSH and POP

The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions:

2-6

3 ADDRESSING MODES

OVERVIEW

Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in SAM88RCRI instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory.

The SAM88RCRI instruction set supports six explicit addressing modes. Not all of these addressing modes are available for each instruction. The addressing modes and their symbols are as follows:

???Register (R)

???Indirect Register (IR)

???Indexed (X)

???Direct Address (DA)

???Relative Address (RA)

???Immediate (IM)

3-1

REGISTER ADDRESSING MODE (R)

In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register addressing differs from Register addressing because it uses a 16-byte working register space in the register file and a 4-bit register within that space (see Figure 3-2).

Figure 3-1. Register Addressing

Figure 3-2. Working Register Addressing

3-2

INDIRECT REGISTER ADDRESSING MODE (IR)

In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).

You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly address another memory location.

Figure 3-3. Indirect Register Addressing to Register File

3-3

INDIRECT REGISTER ADDRESSING MODE (Continued)

Register File

Figure 3-4. Indirect Register Addressing to Program Memory

3-4

INDIRECT REGISTER ADDRESSING MODE (Continued)

Figure 3-5. Indirect Working Register Addressing to Register File

3-5

INDIRECT REGISTER ADDRESSING MODE (Concluded)

Register File

CFH

Figure 3-6. Indirect Working Register Addressing to Program or Data Memory

3-6

INDEXED ADDRESSING MODE (X)

Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory.

In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range of ???128 to +127. This applies to external memory accesses only (see Figure 3-8).

For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address (see Figure 3-9).

The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction (LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory, external program memory, and for external data memory, when implemented.

Register File

Figure 3-7. Indexed Addressing to Register File

3-7

INDEXED ADDRESSING MODE (Continued)

Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset

3-8

INDEXED ADDRESSING MODE (Concluded)

Figure 3-9. Indexed Addressing to Program or Data Memory with Long Offset

3-9

DIRECT ADDRESS MODE (DA)

In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.

The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory (LDC) or to external data memory (LDE), if implemented.

Figure 3-10. Direct Addressing for Load Instructions

3-10

DIRECT ADDRESS MODE (Continued)

Figure 3-11. Direct Addressing for Call and Jump Instructions

3-11

RELATIVE ADDRESS MODE (RA)

In Relative Address (RA) mode, a two's-complement signed displacement between ??? 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction.

The instructions that support RA addressing is JR.

Program Memory

Next OPCODE

Program Memory

Address Used

Figure 3-12. Relative Addressing

IMMEDIATE MODE (IM)

In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. Immediate addressing mode is useful for loading constant values into registers.

Program Memory

OPERAND

OPCODE

(The Operand value is in the instruction)

Sample Instruction:

LD R0,#0AAH

Figure 3-13. Immediate Addressing

3-12

4 CONTROL REGISTERS

OVERVIEW

In this section, detailed descriptions of the S3C9228/P9228 control registers are presented in an easy-to-read format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use them as a quick-reference source when writing application programs.

System and peripheral registers are summarized in Table 4-1. Figure 4-1 illustrates the important features of the standard register description format.

Control register descriptions are arranged in alphabetical order according to register mnemonic. More information about control registers is presented in the context of the various peripheral hardware descriptions in Part II of this manual.

4-1

CONTROL REGISTERSS3C9228/P9228

Table 4-1. System and Peripheral Control Registers (Page 0)

4-2

S3C9228/P9228CONTROL REGISTERS

Table 4-1. System and Peripheral Control Registers (Page 0)

4-3

Bit number(s) that is/are appended to the register name for bit addressing

0Operation dose not generate a carry or borrow condition

1Operation generates carry-out or borrow into high-order bit7

0Operation result is a non-zero value

1Operation result is zero

0 Operation generates positive number (MSB = "0")

1 Operation generates negative number (MSB = "1")

Figure 4-1. Register Description Format

4-4

S3C9228/P9228CONTROL REGISTERS

0Disable operation

1Start operation (automatically disable operation after conversion complete)

4-5

CONTROL REGISTERSS3C9228/P9228

0No effect

1Clear clock frequency dividers

NOTES

1.When "1" is written to BTCON.1, the basic timer counter value is cleared to "00H". Immediately following the write operation, the BTCON.1 value is automatically cleared to "0".

2.When "1" is written to BTCON.0, the corresponding frequency divider is cleared to "00H". Immediately following the write operation, the BTCON.0 value is automatically cleared to "0".

4-6

S3C9228/P9228CONTROL REGISTERS

0Enable IRQ for main or sub oscillator wake-up in power down mode

1Disable IRQ for main or sub oscillator wake-up in power down mode

0 Always logic zero

4-7

CONTROL REGISTERSS3C9228/P9228

0Operation result is a non-zero value

1Operation result is zero

0Operation generates a positive number (MSB = "0")

1Operation generates a negative number (MSB = "1")

4-8

S3C9228/P9228CONTROL REGISTERS

0No interrupt pending (when read), clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), Clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), Clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), Clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), Clear pending bit (when write)

1Interrupt is pending (when read)

NOTE: Refer to Page 5-6 to clear any pending bits.

4-9

CONTROL REGISTERSS3C9228/P9228

INTPND2 ??? Interrupt Pending Register 2D7H

0No interrupt pending (when read), clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), Clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), Clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), Clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), Clear pending bit (when write)

1Interrupt is pending (when read)

NOTE: Refer to Page 5-6 to clear any pending bits.

4-10

S3C9228/P9228CONTROL REGISTERS

0Normal COMs signal output

1COM pins are at high impedance

0Normal I/O

1High impedance input

0Display off (cut off the LCD voltage dividing resistors)

1Normal display on

4-11

CONTROL REGISTERSS3C9228/P9228

0SEG port

1Normal I/O port

0SEG port

1Normal I/O port

0SEG port

1Normal I/O port

0SEG port

1Normal I/O port

NOTE: SEG16-SEG19 are shared with COM4-COM7.

4-12

S3C9228/P9228CONTROL REGISTERS

0Main oscillator RUN

1Main oscillator STOP

0Sub oscillator RUN

1Sub oscillator STOP

4-13

CONTROL REGISTERSS3C9228/P9228

4-14

S3C9228/P9228CONTROL REGISTERS

0Disable interrupt

1Enable interrupt

0Disable interrupt

1Enable interrupt

0Disable interrupt

1Enable interrupt

0Disable interrupt

1Enable interrupt

4-15

CONTROL REGISTERSS3C9228/P9228

0Disable pull-up resistor

1Enable pull-up resistor

0Disable pull-up resistor

1Enable pull-up resistor

0Disable pull-up resistor

1Enable pull-up resistor

0Disable pull-up resistor

1Enable pull-up resistor

4-16

S3C9228/P9228CONTROL REGISTERS

0Falling edge interrupt

1Rising edge interrupt

0Falling edge interrupt

1Rising edge interrupt

0Falling edge interrupt

1Rising edge interrupt

0Falling edge interrupt

1Rising edge interrupt

4-17

CONTROL REGISTERSS3C9228/P9228

4-18

S3C9228/P9228CONTROL REGISTERS

0Disable interrupt

1Enable interrupt

0Disable interrupt

1Enable interrupt

0Disable interrupt

1Enable interrupt

0Disable interrupt

1Enable interrupt

4-19

CONTROL REGISTERSS3C9228/P9228

0Disable pull-up resistor

1Enable pull-up resistor

0Disable pull-up resistor

1Enable pull-up resistor

0Disable pull-up resistor

1Enable pull-up resistor

0Disable pull-up resistor

1Enable pull-up resistor

4-20

S3C9228/P9228CONTROL REGISTERS

0Falling edge interrupt

1Rising edge interrupt

0Falling edge interrupt

1Rising edge interrupt

0Falling edge interrupt

1Rising edge interrupt

0Falling edge interrupt

1Rising edge interrupt

4-21

CONTROL REGISTERSS3C9228/P9228

4-22

S3C9228/P9228CONTROL REGISTERS

0Disable pull-up resistor

1Enable pull-up resistor

0Disable pull-up resistor

1Enable pull-up resistor

0Disable pull-up resistor

1Enable pull-up resistor

0Disable pull-up resistor

1Enable pull-up resistor

4-23

CONTROL REGISTERSS3C9228/P9228

4-24

S3C9228/P9228CONTROL REGISTERS

0Disable interrupt

1Enable interrupt

0Disable interrupt

1Enable interrupt

4-25

CONTROL REGISTERSS3C9228/P9228

0Disable pull-up resistor

1Enable pull-up resistor

0Disable pull-up resistor

1Enable pull-up resistor

4-26

S3C9228/P9228CONTROL REGISTERS

0Falling edge interrupt

1Rising edge interrupt

0Falling edge interrupt

1Rising edge interrupt

4-27

CONTROL REGISTERSS3C9228/P9228

4-28

S3C9228/P9228CONTROL REGISTERS

4-29

CONTROL REGISTERSS3C9228/P9228

4-30

S3C9228/P9228CONTROL REGISTERS

4-31

CONTROL REGISTERSS3C9228/P9228

4-32

S3C9228/P9228CONTROL REGISTERS

0Internal clock (P.S clock)

1External clock (SCK)

0MSB-first mode

1LSB-first mode

0Receive-only mode

1Transmit/receive mode

0Tx at falling edges, Rx at rising edges

1Tx at rising edges, Rx at falling edges

0No action

1Clear 3-bit counter and start shifting

0Disable shifter and clock counter

1Enable shifter and clock counter

0Disable SIO interrupt

1Enable SIO interrupt

4-33

CONTROL REGISTERSS3C9228/P9228

NOTE: Before executing the STOP instruction, the STPCON register must be set to "10100101B". Otherwise the STOP instruction will not execute.

4-34

S3C9228/P9228CONTROL REGISTERS

SYM ??? System Mode RegisterDFH

4-35

CONTROL REGISTERSS3C9228/P9228

0Two 8-bit timers mode (Timer A/B)

1One 16-bit timer mode (Timer 1)

0No effect

1Clear the timer 1/A counter (when write)

0Disable counting operation

1Enable counting operation

0Disable interrupt

1Enable interrupt

4-36

S3C9228/P9228CONTROL REGISTERS

4-37

CONTROL REGISTERSS3C9228/P9228

0Select main clock divided by 27 (fx/128)

1Select sub clock (fxt)

0Disable watch timer interrupt

1Enable watch timer interrupt

4-38

5 INTERRUPT STRUCTURE

OVERVIEW

The SAM88RCRI interrupt structure has two basic components: a vector, and sources. The number of interrupt sources can be serviced through a interrupt vector which is assigned in ROM address 0000H???0001H.

1.The SAM88RCRI interrupt has only one vector address (0000H-0001H).

2.The number of Sn value is expandable.

Figure 5-1. S3C9-Series Interrupt Type

INTERRUPT PROCESSING CONTROL POINTS

Interrupt processing can be controlled in two ways: globally, or by specific interrupt level and source. The system- level control points in the interrupt structure are therefore:

???Global interrupt enable and disable (by EI and DI instructions)

???Interrupt source enable and disable settings in the corresponding peripheral control register(s)

ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, DI)

The system mode register, SYM (DFH), is used to enable and disable interrupt processing.

SYM.3 is the enable and disable bit for global interrupt processing, which you can set by modifying SYM.3. An Enable Interrupt (EI) instruction must be included in the initialization routine that follows a reset operation in order to enable interrupt processing. Although you can manipulate SYM.3 directly to enable and disable interrupts during normal operation, we recommend that you use the EI and DI instructions for this purpose.

5-1

INTERRUPT PENDING FUNCTION TYPES

When the interrupt service routine has executed, the application program's service routine must clear the appropriate pending bit before the return from interrupt subroutine (IRET) occurs.

INTERRUPT PRIORITY

Because there is not a interrupt priority register in SAM87RCRI, the order of service is determined by a sequence of source which is executed in interrupt service routine.

Figure 5-2. Interrupt Function Diagram

5-2

INTERRUPT SOURCE SERVICE SEQUENCE

The interrupt request polling and servicing sequence is as follows:

1.A source generates an interrupt request by setting the interrupt request pending bit to "1".

2.The CPU generates an interrupt acknowledge signal.

3.The service routine starts and the source's pending flag is cleared to "0" by software.

4.Interrupt priority must be determined by software polling method.

INTERRUPT SERVICE ROUTINES

Before an interrupt request can be serviced, the following conditions must be met:

???Interrupt processing must be enabled (EI, SYM.3 = "1")

???Interrupt must be enabled at the interrupt's source (peripheral control register)

If all of the above conditions are met, the interrupt request is acknowledged at the end of the instruction cycle. The CPU then initiates an interrupt machine cycle that completes the following processing sequence:

1.Reset (clear to "0") the global interrupt enable bit in the SYM register (DI, SYM.3 = "0") to disable all subsequent interrupts.

2.Save the program counter and status flags to stack.

3.Branch to the interrupt vector to fetch the service routine's address.

4.Pass control to the interrupt service routine.

When the interrupt service routine is completed, an Interrupt Return instruction (IRET) occurs. The IRET restores the PC and status flags and sets SYM.3 to "1"(EI), allowing the CPU to process the next interrupt request.

GENERATING INTERRUPT VECTOR ADDRESSES

The interrupt vector area in the ROM contains the address of the interrupt service routine. Vectored interrupt processing follows this sequence:

1.Push the program counter's low-byte value to tacks.

2.Push the program counter's high-byte value to stack.

3.Push the FLAGS register values to stack.

4.Fetch the service routine's high-byte address from the vector address 0000H.

5.Fetch the service routine's low-byte address from the vector address 0001H.

6.Branch to the service routine specified by the 16-bit vector address.

5-3

S3C9228/P9228 INTERRUPT STRUCTURE

The S3C9228/P9228 microcontroller has fourteen peripheral interrupt sources:

???Timer 1/A interrupt

???Timer B interrupt

???SIO interrupt

???Watch Timer interrupt

???Four external interrupts for port 0

???Four external interrupts for port 1

???Two external interrupts for port 3

5-4

Figure 5-3. S3C9228/P9228 Interrupt Structure

5-5

INTERRUPT STRUCTURES3C9228/P9228

Programming Tip ??? How to clear an interrupt pending bit

As the following examples are shown, a load instruction should be used to clear an interrupt pending bit.

Examples:

5-6

6 SAM88RCRI INSTRUCTION SET

OVERVIEW

The SAM88RCRI instruction set is designed to support the large register file. It includes a full complement of 8- bit arithmetic and logic operations. There are 41 instructions. No special I/O instructions are necessary because I/O control and data registers are mapped directly into the register file. Flexible instructions for bit addressing, rotate, and shift operations complete the powerful data manipulation capabilities of the SAM88RCRI instruction set.

REGISTER ADDRESSING

To access an individual register, an 8-bit address in the range 0-255 or the 4-bit address of a working register is specified. Paired registers can be used to construct 16-bit program memory or data memory addresses. For detailed information about register addressing, please refer to Section 2, "Address Spaces".

ADDRESSING MODES

There are six addressing modes: Register (R), Indirect Register (IR), Indexed (X), Direct (DA), Relative (RA), and Immediate (IM). For detailed descriptions of these addressing modes, please refer to Section 3, "Addressing Modes".

6-1

SAM88RI INSTRUCTION SETS3C9228/P9228

6-2

S3C9228/P9228SAM88RCRI INSTRUCTION SET

Table 6-1. Instruction Group Summary (Continued)

6-3

FLAGS REGISTER (FLAGS)

The FLAGS register contains eight bits that describe the current status of CPU operations. Four of these bits, FLAGS.4 ??? FLAGS.7, can be tested and used with conditional jump instructions;

FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags, such as, Load instruction. Logical and Arithmetic instructions such as, AND, OR, XOR, ADD, and SUB can affect the Flags register. For example, the AND instruction updates the Zero, Sign and Overflow flags based on the outcome of the AND instruction. If the AND instruction uses the Flags register as the destination, then simultaneously, two write will occur to the Flags register producing an unpredictable result.

System Flags Register (FLAGS)

D5H, R/W

Carry flag (C)

Not mapped

Zero flag (Z)

Sign flag (S)

Overflow flag (V)

Figure 6-1. System Flags Register (FLAGS)

FLAG DESCRIPTIONS

Overflow Flag (FLAGS.4, V)

The V flag is set to "1" when the result of a two's-complement operation is greater than + 127 or less than ??? 128. It is also cleared to "0" following logic operations.

Sign Flag (FLAGS.5, S)

Following arithmetic, logic, rotate, or shift operations, the sign bit identifies the state of the MSB of the result. A logic zero indicates a positive number and a logic one indicates a negative number.

Zero Flag (FLAGS.6, Z)

For arithmetic and logic operations, the Z flag is set to "1" if the result of the operation is zero. For operations that test register bits, and for shift and rotate operations, the Z flag is set to "1" if the result is logic zero.

Carry Flag (FLAGS.7, C)

The C flag is set to "1" if the result from an arithmetic operation generates a carry-out from or a borrow to the bit 7 position (MSB). After rotate and shift operations, it contains the last value shifted out of the specified register. Program instructions can set, clear, or complement the carry flag.

6-4

S3C9228/P9228SAM88RCRI INSTRUCTION SET

INSTRUCTION SET NOTATION

6-5

SAM88RI INSTRUCTION SETS3C9228/P9228

Table 6-4. Instruction Notation Conventions

6-6

S3C9228/P9228SAM88RCRI INSTRUCTION SET

Table 6-5. Opcode Quick Reference

OPCODE MAP

LOWER NIBBLE (HEX)

6-7

SAM88RI INSTRUCTION SETS3C9228/P9228

Table 6-5. Opcode Quick Reference (Continued)

OPCODE MAP

LOWER NIBBLE (HEX)

6-8

CONDITION CODES

The opcode of a conditional jump always contains a 4-bit field called the condition code (cc). This specifies under which conditions it is to execute the jump. For example, a conditional jump with the condition code for "equal" after a compare operation only jumps if the two operands are equal. Condition codes are listed in Table 6-6.

The carry (C), zero (Z), sign (S), and overflow (V) flags are used to control the operation of conditional jump instructions.

Table 6-6. Condition Codes

NOTES:

1.Indicate condition codes that are related to two different mnemonics but which test the same flag.

For example, Z and EQ are both true if the zero flag (Z) is set, but after an ADD instruction, Z would probably be used; after a CP instruction, however, EQ would probably be used.

2.For operations involving unsigned numbers, the special condition codes UGE, ULT, UGT, and ULE must be used.

6-9

INSTRUCTION DESCRIPTIONS

This section contains detailed information and programming examples for each instruction in the SAM88RCRI instruction set. Information is arranged in a consistent format for improved readability and for fast referencing. The following information is included in each instruction description:

???Instruction name (mnemonic)

???Full instruction name

???Source/destination format of the instruction operand

???Shorthand notation of the instruction's operation

???Textual description of the instruction's effect

???Specific flag settings affected by the instruction

???Detailed description of the instruction's format, execution time, and addressing mode(s)

???Programming example(s) explaining how to use the instruction

6-10

ADC ??? Add With Carry

ADCdst,src

Operation: dst ?? dst + src + c

The source operand, along with the setting of the carry flag, is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's- complement addition is performed. In multiple precision arithmetic, this instruction permits the carry from the addition of low-order operands to be carried into the addition of high-order operands.

cleared otherwise.

Examples: Given: R1 = 10H, R2 = 03H, C flag = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH:

In the first example, destination register R1 contains the value 10H, the carry flag is set to "1", and the source working register R2 contains the value 03H. The statement "ADC R1,R2" adds 03H and the carry flag value ("1") to the destination value 10H, leaving 14H in register R1.

6-11

SAM88RI INSTRUCTION SETS3C9228/P9228

ADD ??? Add

ADDdst,src

Operation: dst ?? dst + src

The source operand is added to the destination operand and the sum is stored in the destination. The contents of the source are unaffected. Two's-complement addition is performed.

Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

In the first example, destination working register R1 contains 12H and the source working register R2 contains 03H. The statement "ADD R1,R2" adds 03H to 12H, leaving the value 15H in register R1.

6-12

AND ??? Logical AND

ANDdst,src

Operation: dst ?? dst AND src

The source operand is logically ANDed with the destination operand. The result is stored in the destination. The AND operation results in a "1" bit being stored whenever the corresponding bits in the two operands are both logic ones; otherwise a "0" bit value is stored. The contents of the source are unaffected.

Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

In the first example, destination working register R1 contains the value 12H and the source working register R2 contains 03H. The statement "AND R1,R2" logically ANDs the source operand 03H with the destination operand value 12H, leaving the value 02H in register R1.

6-13

CALL ??? Call Procedure

The current contents of the program counter are pushed onto the top of the stack. The program counter value used is the address of the first instruction following the CALL instruction. The specified destination address is then loaded into the program counter and points to the first instruction of a procedure. At the end of the procedure the return instruction (RET) can be used to return to the original program flow. RET pops the top of the stack back into the program counter.

Flags: No flags are affected.

Format:

Examples: Given: R0 = 15H, R1 = 21H, PC = 1A47H, and SP = 0B2H:

In the first example, if the program counter value is 1A47H and the stack pointer contains the value 0B2H, the statement "CALL 1521H" pushes the current PC value onto the top of the stack. The stack pointer now points to memory location 00H. The PC is then loaded with the value 1521H, the address of the first instruction in the program sequence to be executed.

If the contents of the program counter and stack pointer are the same as in the first example, the statement "CALL @RR0" produces the same result except that the 49H is stored in stack location 01H (because the two-byte instruction format was used). The PC is then loaded with the value 1521H, the address of the first instruction in the program sequence to be executed.

6-14

CCF ??? Complement Carry Flag

CCF

Operation: C ?? NOT C

The carry flag (C) is complemented. If C = "1", the value of the carry flag is changed to logic zero; if C = "0", the value of the carry flag is changed to logic one.

If the carry flag = "0", the CCF instruction complements it in the FLAGS register (0D5H), changing its value from logic zero to logic one.

6-15

CLR ??? Clear

CLRdst

Operation: dst ?? "0"

The destination location is cleared to "0".

Flags: No flags are affected.

Format:

Examples: Given: Register 00H = 4FH, register 01H = 02H, and register 02H = 5EH:

In Register (R) addressing mode, the statement "CLR 00H" clears the destination register 00H value to 00H. In the second example, the statement "CLR @01H" uses Indirect Register (IR) addressing mode to clear the 02H register value to 00H.

6-16

S3C9228/P9228SAM88RCRI INSTRUCTION SET

COM ??? Complement

In the first example, destination working register R1 contains the value 07H (00000111B). The statement "COM R1" complements all the bits in R1: all logic ones are changed to logic zeros, and vice-versa, leaving the value 0F8H (11111000B).

In the second example, Indirect Register (IR) addressing mode is used to complement the value of destination register 07H (11110001B), leaving the new value 0EH (00001110B).

6-17

CP ??? Compare

Destination working register R1 contains the value 02H and source register R2 contains the value 03H. The statement "CP R1,R2" subtracts the R2 value (source/subtrahend) from the R1 value (destination/minuend). Because a "borrow" occurs and the difference is negative, C and S are "1".

2. Given: R1 = 05H and R2 = 0AH:

In this example, destination working register R1 contains the value 05H which is less than the contents of the source working register R2 (0AH). The statement "CP R1,R2" generates C = "1" and the JP instruction does not jump to the SKIP location. After the statement "LD R3,R1" executes, the value 06H remains in working register R3.

6-18

S3C9228/P9228SAM88RCRI INSTRUCTION SET

DEC ??? Decrement

In the first example, if working register R1 contains the value 03H, the statement "DEC R1" decrements the hexadecimal value by one, leaving the value 02H. In the second example, the statement "DEC @R1" decrements the value 10H contained in the destination register 03H by one, leaving the value 0FH.

6-19

DI ??? Disable Interrupts

DI

Operation: SYM (2) ?? 0

Bit zero of the system mode register, SYM.2, is cleared to "0", globally disabling all interrupt processing. Interrupt requests will continue to set their respective interrupt pending bits, but the CPU will not service them while interrupt processing is disabled.

If the value of the SYM register is 04H, the statement "DI" leaves the new value 00H in the register and clears SYM.2 to "0", disabling interrupt processing.

6-20

EI ??? Enable Interrupts

EI

Operation: SYM (2) ?? 1

An EI instruction sets bit 2 of the system mode register, SYM.2 to "1". This allows interrupts to be serviced as they occur. If an interrupt's pending bit was set while interrupt processing was disabled (by executing a DI instruction), it will be serviced when you execute the EI instruction.

If the SYM register contains the value 00H, that is, if interrupts are currently disabled, the statement "EI" sets the SYM register to 04H, enabling all interrupts (SYM.2 is the enable bit for global interrupt processing).

6-21

SAM88RI INSTRUCTION SETS3C9228/P9228

IDLE ??? Idle Operation

6-22

INC ??? Increment

INCdst

Operation: dst ?? dst + 1

The contents of the destination operand are incremented by one.

Examples: Given: R0 = 1BH, register 00H = 0CH, and register 1BH = 0FH:

In the first example, if destination working register R0 contains the value 1BH, the statement "INC R0" leaves the value 1CH in that same register.

The next example shows the effect an INC instruction has on register 00H, assuming that it contains the value 0CH.

In the third example, INC is used in Indirect Register (IR) addressing mode to increment the value of register 1BH from 0FH to 10H.

6-23

IRET ??? Interrupt Return

IRETIRET

Operation: FLAGS ?? @SP

SP ?? SP + 1

PC ?? @SP

SP ?? SP + 2

SYM(2) ?? 1

This instruction is used at the end of an interrupt service routine. It restores the flag register and the program counter. It also re-enables global interrupts.

Flags: All flags are restored to their original settings (that is, the settings before the interrupt occurred).

Format:

6-24

JP ??? Jump

NOTES:

1.The 3-byte format is used for a conditional jump and the 2-byte format for an unconditional jump.

2.In the first byte of the three-byte instruction format (conditional jump), the condition code and the opcode are both four bits.

Examples: Given: The carry flag (C) = "1", register 00 = 01H, and register 01 = 20H:

The first example shows a conditional JP. Assuming that the carry flag is set to "1", the statement "JP C,LABEL_W" replaces the contents of the PC with the value 1000H and transfers control to that location. Had the carry flag not been set, control would then have passed to the statement immediately following the JP instruction.

The second example shows an unconditional JP. The statement "JP @00" replaces the contents of the PC with the contents of the register pair 00H and 01H, leaving the value 0120H.

6-25

SAM88RI INSTRUCTION SETS3C9228/P9228

JR ??? Jump Relative

NOTE: In the first byte of the two-byte instruction format, the condition code and the opcode are each four bits.

Example: Given: The carry flag = "1" and LABEL_X = 1FF7H:

If the carry flag is set (that is, if the condition code is true), the statement "JR C,LABEL_X" will pass control to the statement whose address is now in the PC. Otherwise, the program instruction following the JR would be executed.

6-26

LD ??? Load

6-27

LD ??? Load

LD(Continued)

Examples: Given: R0 = 01H, R1 = 0AH, register 00H = 01H, register 01H = 20H, register 02H = 02H, LOOP = 30H, and register 3AH = 0FFH:

6-28

LDC/LDE ??? Load Memory

LDC/LDE dst,src

Operation: dst ?? src

This instruction loads a byte from program or data memory into a working register or vice-versa. The source values are unaffected. LDC refers to program memory and LDE to data memory. The assembler makes Irr' orrr' values an even number for program memory and an odd number for data memory.

1.The source (src) or working register pair [rr] for formats 5 and 6 cannot use register pair 0???1.

2.For formats 3 and 4, the destination address 'XSrr]'[ and the source address 'XSrr]'[ are each one byte.

3.For formats 5 and 6, the destination address 'XLrr][ and the source address 'XLrr]'[ are each two bytes.

4.The DA and r source values for formats 7 and 8 are used to address program memory; the second set of values, used in formats 9 and 10, are used to address data memory.

6-29

LDC/LDE ??? Load Memory

LDC/LDE (Continued)

Examples: Given: R0 = 11H, R1 = 34H, R2 = 01H, R3 = 04H, R4 = 00H, R5 = 60H; Program memory locations 0061 = AAH, 0103H = 4FH, 0104H = 1A, 0105H = 6DH, and 1104H = 88H. External data memory locations 0061H = BBH, 0103H = 5FH, 0104H = 2AH, 0105H = 7DH, and 1104H = 98H:

NOTE: These instructions are not supported by masked ROM type devices.

6-30

LDCD/LDED ??? Load Memory and Decrement

LDCD/LDED dst,src

Operation: dst ?? src

rr ?? rr ??? 1

These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then decremented. The contents of the source are unaffected.

LDCD references program memory and LDED references external data memory. The assembler makes ???Irr??? an even number for program memory and an odd number for data memory.

Flags: No flags are affected.

Format:

Examples: Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory location 1033H = 0CDH, and external data memory location 1033H = 0DDH:

6-31

LDCI/LDEI ??? Load Memory and Increment

LDCI/LDEI dst,src

Operation: dst ?? src

rr ?? rr + 1

These instructions are used for user stacks or block transfers of data from program or data memory to the register file. The address of the memory location is specified by a working register pair. The contents of the source location are loaded into the destination location. The memory address is then incremented automatically. The contents of the source are unaffected.

LDCI refers to program memory and LDEI refers to external data memory. The assembler makes Irr' even for program memory and odd for data memory.

Flags: No flags are affected.

Format:

Examples: Given: R6 = 10H, R7 = 33H, R8 = 12H, program memory locations 1033H = 0CDH and 1034H = 0C5H; external data memory locations 1033H = 0DDH and 1034H = 0D5H:

6-32

NOP ??? No Operation

NOP

Operation: No action is performed when the CPU executes this instruction. Typically, one or more NOPs are executed in sequence in order to effect a timing delay of variable duration.

is encountered in a program, no operation occurs. Instead, there is a delay in instruction execution time.

6-33

OR ??? Logical OR

Examples: Given: R0 = 15H, R1 = 2AH, R2 = 01H, register 00H = 08H, register 01H = 37H, and register 08H = 8AH:

In the first example, if working register R0 contains the value 15H and register R1 the value 2AH, the statement "OR R0,R1" logical-ORs the R0 and R1 register contents and stores the result (3FH) in destination register R0.

The other examples show the use of the logical OR instruction with the various addressing modes and formats.

6-34

POP ??? Pop From Stack

POPdst

Operation: dst ?? @SP

SP ?? SP + 1

The contents of the location addressed by the stack pointer are loaded into the destination. The stack pointer is then incremented by one.

Examples: Given: Register 00H = 01H, register 01H = 1BH, SP (0D9H) = 0BBH, and stack register 0BBH = 55H:

In the first example, general register 00H contains the value 01H. The statement "POP 00H" loads the contents of location 0BBH (55H) into destination register 00H and then increments the stack pointer by one. Register 00H then contains the value 55H and the SP points to location 0BCH.

6-35

PUSH ??? Push To Stack

PUSHsrc

Operation: SP ?? SP ??? 1

@SP ?? src

A PUSH instruction decrements the stack pointer value and loads the contents of the source (src) into the location addressed by the decremented stack pointer. The operation then adds the new value to the top of the stack.

Flags: No flags are affected.

Format:

Examples: Given: Register 40H = 4FH, register 4FH = 0AAH, SP = 0C0H:

In the first example, if the stack pointer contains the value 0C0H, and general register 40H the value 4FH, the statement "PUSH 40H" decrements the stack pointer from 0C0 to 0BFH. It then loads the contents of register 40H into location 0BFH. Register 0BFH then contains the value 4FH and SP points to location 0BFH.

6-36

S3C9228/P9228SAM88RCRI INSTRUCTION SET

RCF ??? Reset Carry Flag

6-37

RET ??? Return

RET

Operation: PC ?? @SP

SP ?? SP + 2

The RET instruction is normally used to return to the previously executing procedure at the end of a procedure entered by a CALL instruction. The contents of the location addressed by the stack pointer are popped into the program counter. The next statement that is executed is the one that is addressed by the new program counter value.

Example: Given: SP = 0BCH, (SP) = 101AH, and PC = 1234:

The statement "RET" pops the contents of stack pointer location 0BCH (10H) into the high byte of the program counter. The stack pointer then pops the value in location 0BDH (1AH) into the PC's low byte and the instruction at location 101AH is executed. The stack pointer now points to memory location 0BEH.

6-38

RL ??? Rotate Left

dst (0) ?? dst (7)

dst (n + 1) ?? dst (n), n = 0???6

The contents of the destination operand are rotated left one bit position. The initial value of bit 7 is moved to the bit zero (LSB) position and also replaces the carry flag.

Examples: Given: Register 00H = 0AAH, register 01H = 02H and register 02H = 17H:

In the first example, if general register 00H contains the value 0AAH (10101010B), the statement "RL 00H" rotates the 0AAH value left one bit position, leaving the new value 55H (01010101B) and setting the carry and overflow flags.

6-39

RLC ??? Rotate Left Through Carry

RLCdst

Operation: dst (0) ?? C

C ?? dst (7)

dst (n + 1) ?? dst (n), n = 0???6

The contents of the destination operand with the carry flag are rotated left one bit position. The initial value of bit 7 replaces the carry flag (C); the initial value of the carry flag replaces bit zero.

Examples: Given: Register 00H = 0AAH, register 01H = 02H, and register 02H = 17H, C = "0":

In the first example, if general register 00H has the value 0AAH (10101010B), the statement "RLC 00H" rotates 0AAH one bit position to the left. The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register 00H, leaving the value 55H (01010101B). The MSB of register 00H resets the carry flag to "1" and sets the overflow flag.

6-40

RR ??? Rotate Right

dst (7) ?? dst (0)

dst (n) ?? dst (n + 1), n = 0???6

The contents of the destination operand are rotated right one bit position. The initial value of bit zero (LSB) is moved to bit 7 (MSB) and also replaces the carry flag (C).

In the first example, if general register 00H contains the value 31H (00110001B), the statement "RR 00H" rotates this value one bit position to the right. The initial value of bit zero is moved to bit 7, leaving the new value 98H (10011000B) in the destination register. The initial bit zero also resets the C flag to "1" and the sign flag and overflow flag are also set to "1".

6-41

RRC ??? Rotate Right Through Carry

RRCdst

Operation: dst (7) ?? C

C ?? dst (0)

dst (n) ?? dst (n + 1), n = 0???6

The contents of the destination operand and the carry flag are rotated right one bit position. The initial value of bit zero (LSB) replaces the carry flag; the initial value of the carry flag replaces bit 7 (MSB).

Examples: Given: Register 00H = 55H, register 01H = 02H, register 02H = 17H, and C = "0":

In the first example, if general register 00H contains the value 55H (01010101B), the statement "RRC 00H" rotates this value one bit position to the right. The initial value of bit zero ("1") replaces the carry flag and the initial value of the C flag ("1") replaces bit 7. This leaves the new value 2AH (00101010B) in destination register 00H. The sign flag and overflow flag are both cleared to "0".

6-42

SBC ??? Subtract With Carry

f the result is the same as the sign of the source; cleared otherwise. D: Always set to "1".

H:Cleared if there is a carry from the most significant bit of the low-order four bits of the result; set otherwise, indicating a "borrow".

Format:

Examples: Given: R1 = 10H, R2 = 03H, C = "1", register 01H = 20H, register 02H = 03H, and register 03H = 0AH:

In the first example, if working register R1 contains the value 10H and register R2 the value 03H, the statement "SBC R1,R2" subtracts the source value (03H) and the C flag value ("1") from the destination (10H) and then stores the result (0CH) in register R1.

6-43

SAM88RI INSTRUCTION SETS3C9228/P9228

SCF ??? Set Carry Flag

6-44

SRA ??? Shift Right Arithmetic

C ?? dst (0)

dst (n) ?? dst (n + 1), n = 0???6

An arithmetic shift-right of one bit position is performed on the destination operand. Bit zero (the LSB) replaces the carry flag. The value of bit 7 (the sign bit) is unchanged and is shifted into bit position 6.

Examples: Given: Register 00H = 9AH, register 02H = 03H, register 03H = 0BCH, and C = "1":

In the first example, if general register 00H contains the value 9AH (10011010B), the statement "SRA 00H" shifts the bit values in register 00H right one bit position. Bit zero ("0") clears the C flag and bit 7 ("1") is then shifted into the bit 6 position (bit 7 remains unchanged). This leaves the value 0CDH (11001101B) in destination register 00H.

6-45

STOP ??? Stop Operation

6-46

SUB ??? Subtract

Examples: Given: R1 = 12H, R2 = 03H, register 01H = 21H, register 02H = 03H, register 03H = 0AH:

In the first example, if working register R1 contains the value 12H and if register R2 contains the value 03H, the statement "SUB R1,R2" subtracts the source value (03H) from the destination value (12H) and stores the result (0FH) in destination register R1.

6-47

TCM ??? Test Complement Under Mask

TCMdst,src

Operation: (NOT dst) AND src

This instruction tests selected bits in the destination operand for a logic one value. The bits to be tested are specified by setting a "1" bit in the corresponding position of the source operand (mask). The TCM statement complements the destination operand, which is then ANDed with the source mask. The zero (Z) flag can then be checked to determine the result. The destination and source operands are unaffected.

Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 12H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H:

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TCM R0,R1" tests bit one in the destination register for a "1" value. Because the mask value corresponds to the test bit, the Z flag is set to logic one and can be tested to determine the result of the TCM operation.

6-48

TM ??? Test Under Mask

Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H:

In the first example, if working register R0 contains the value 0C7H (11000111B) and register R1 the value 02H (00000010B), the statement "TM R0,R1" tests bit one in the destination register for a "0" value. Because the mask value does not match the test bit, the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation.

6-49

XOR ??? Logical Exclusive OR

XORdst,src

Operation: dst ?? dst XOR src

The source operand is logically exclusive-ORed with the destination operand and the result is stored in the destination. The exclusive-OR operation results in a "1" bit being stored whenever the corresponding bits in the operands are different; otherwise, a "0" bit is stored.

Examples: Given: R0 = 0C7H, R1 = 02H, R2 = 18H, register 00H = 2BH, register 01H = 02H, and register 02H = 23H:

In the first example, if working register R0 contains the value 0C7H and if register R1 contains the value 02H, the statement "XOR R0,R1" logically exclusive-ORs the R1 value with the R0 value and stores the result (0C5H) in the destination register R0.

6-50

7 CLOCK CIRCUITS

OVERVIEW

The S3C9228 microcontroller has two oscillator circuits: a main clock, and a sub clock circuit. The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits. The maximum CPU clock frequency, is determined by CLKCON register settings.

SYSTEM CLOCK CIRCUIT

The system clock circuit has the following components:

???Crystal, ceramic resonator, RC oscillation source (main clock only), or an external clock

???Oscillator stop and wake-up functions

???Programmable frequency divider for the CPU clock (fxx divided by 1, 2, 8, or 16)

???Clock circuit control register, CLKCON

???Oscillator control register, OSCCON

CPU CLOCK NOTATION

In this document, the following notation is used for descriptions of the CPU clock:

fx main clock fxt sub clock

fxx selected system clock

7-1

XIN

R

XOUT

Figure 7-3. RC Oscillator

7-2

CLOCK STATUS DURING POWER-DOWN MODES

The two power-down modes, Stop mode and Idle mode, affect the system clock as follows:

???In Stop mode, the main oscillator is halted. Stop mode is released, and the oscillator started, by a reset operation, by an external interrupt, or by an internal interrupt if sub clock is selected as the clock source (When the fx is selected as system clock).

???In Idle mode, the internal clock signal is gated away from the CPU, but continues to be supplied to the interrupt structure, timer A/B, and watch timer. Idle mode is released by a reset or by an external or internal interrupts.

Figure 7-6. System Clock Circuit Diagram

7-3

SYSTEM CLOCK CONTROL REGISTER (CLKCON)

The system clock control register, CLKCON, is located in address D4H. It is read/write addressable and has the following functions:

???Oscillator IRQ wake-up function enable/disable

???Oscillator frequency divide-by value

CLKCON register settings control whether or not an external interrupt can be used to trigger a Stop mode release (This is called the ???IRQ wake-up??? function). The IRQ ???wake-up??? enable bit is CLKCON.7.

After a reset, the external interrupt oscillator wake-up function is enabled, the main oscillator is activated, and the fx/16 (the slowest clock speed) is selected as the CPU clock. If necessary, you can then increase the CPU clock speed to fx, fx/2, or fx/8 by setting the CLKCON, and you can change system clock from main clock to sub clock by setting the OSCCON.

System Clock Control Register (CLKCON)

D4H, R/W

Not used for S3C9228 (must keep always "0")

Figure 7-7. System Clock Control Register (CLKCON)

7-4

OSCILLATOR CONTROL REGISTER (OSCCON)

The oscillator control register, OSCCON, is located in address D3H. It is read/write addressable and has the following functions:

???System clock selection

???Main oscillator control

???Sub oscillator control

OSCCON.0 register settings select Main clock or Sub clock as system clock.

After a reset, Main clock is selected for system clock because the reset value of OSCCON.0 is "0".

The main oscillator can be stopped or run by setting OSCCON.3.

The sub oscillator can be stopped or run by setting OSCCON.2.

Oscillator Control Register (OSCCON)

D3H, R/W

System clock selection bit: 0 = Main oscillator select 1 = Sub oscillator select

Sub oscillator control bit: 0 = Sub oscillator RUN 1 = Sub oscillator STOP

Main oscillator control bit: 0 = Main oscillator RUN 1 = Main oscillator STOP

Figure 7-8. Oscillator Control Register (OSCCON)

7-5

SWITCHING THE CPU CLOCK

Data loadings in the oscillator control register, OSCCON, determine whether a main or a sub clock is selected as the CPU clock, and also how this frequency is to be divided by setting CLKCON. This makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies.

OSCCON.0 select the main clock (fx) or the sub clock (fxt) for the system clock. OSCCON .3 start or stop main clock oscillation, and OSCCON.2 start or stop sub clock oscillation. CLKCON.4???.3 control the frequency divider circuit, and divide the selected fxx clock by 1, 2, 8, or 16.

For example, you are using the default system clock (normal operating mode and a main clock of fx/16) and you want to switch from the fx clock to a sub clock and to stop the main clock. To do this, you need to set OSCCON.0 to "1", take a delay, and OSCCON.3 to "1" sequently. This switches the clock from fx to fxt and stops main clock oscillation.

The following steps must be taken to switch from a sub clock to the main clock: first, set OSCCON.3 to "0" to enable main system clock oscillation. Then, after a certain number of machine cycles has elapsed, select the main clock by setting OSCCON.0 to "0".

+PROGRAMMING TIP ??? Switching the CPU clock

1. This example shows how to change from the main clock to the sub clock:

7-6

STOP CONTROL REGISTER (STPCON)

The STOP control register, STPCON, is located in address E0H. It is read/write addressable and has the following functions:

???Enable/Disable STOP instruction

After a reset, the STOP instruction is disabled, because the value of STPCON is "other values". If necessary, you can use the STOP instruction by setting the value of STPCON to "10100101B".

Stop Control Register (STPCON)

E0H, R/W

STOP control bits:

10100101 = Enable STOP instruction Other values = Disable STOP instruction

Figure 7-9. STOP Control Register (STPCON)

+PROGRAMMING TIP ??? How to Use Stop Instruction

This example shows how to go STOP mode when a main clock is selected as the system clock.

7-7

NOTES

7-8

8 RESET and POWER-DOWN

SYSTEM RESET

OVERVIEW

During a power-on reset, the voltage at VDD goes to High level and the RESET pin is forced to Low level. The

RESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock. This procedure brings S3C9228/P9228 into a known operating status.

To allow time for internal CPU clock oscillation to stabilize, the RESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance. The minimum required oscillation stabilization time for a reset operation is 1 millisecond.

Whenever a reset occurs during normal operation (that is, when both VDD and RESET are High level), the

RESET pin is forced Low and the reset operation starts. All system and peripheral control registers are then reset to their default hardware values (see Table 8-1).

In summary, the following sequence of events occurs during a reset operation:

???All interrupts are disabled.

???The watchdog function (basic timer) is enabled.

???The P0.0???P0.3, P1, and P2.2???P2.3 are set to schmitt trigger input mode and all pull-up resistors are disabled for the I/O port pin circuits.

???Peripheral control and data registers are disabled and reset to their default hardware values.

???The program counter (PC) is loaded with the program reset address in the ROM, 0100H.

???When the programmed oscillation stabilization time interval has elapsed, the instruction stored in ROM location 0100H (and 0101H) is fetched and executed.

NOTE

To program the duration of the oscillation stabilization interval, you make the appropriate settings to the basic timer control register, BTCON, before entering Stop mode. Also, if you do not want to use the basic timer watchdog function (which causes a system reset if a basic timer counter overflow occurs), you can disable it by writing '1010B' to the upper nibble of BTCON.

8-1

POWER-DOWN MODES

STOP MODE

Stop mode is invoked by the instruction STOP. In Stop mode, the operation of the CPU and main oscillator is halted. All peripherals which the main oscillator is selected as a clock source stop also because main oscillator stops. But the watch timer and LCD controller will not halted in stop mode if the sub clock is selected as watch timer clock source. The data stored in the internal register file are retained in stop mode. Stop mode can be released in one of three ways: by a system reset, by an internal watch timer interrupt (when sub clock is selected as clock source of watch timer), or by an external interrupt.

NOTES

1.Do not use stop mode if you are using an external clock source because XIN input must be restricted internally to VSS to reduce current leakage.

2.In application programs, a STOP instruction must be immediately followed by at least three NOP instructions. This ensures an adequate time interval for the clock to stabilize before the next instruction is executed. If three or more NOP instructions are not used after STOP instruction, leakage current could be flown because of the floating state in the internal bus.

3.To enable/disable STOP instruction, the STOPCON register should be written with 10100101B/other values before/after stop instruction.

Using RESET to Release Stop Mode

Stop mode is released when the RESET signal goes active (Low level): all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained. When the programmed oscillation stabilization interval has elapsed, the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H.

Using an External Interrupt to Release Stop Mode

External interrupts can be used to release stop mode. For the S3C9228 microcontroller, we recommend using the INT interrupt, P0, P1, and P3.

8-2

Using an Internal Interrupt to Release Stop Mode

An internal interrupt, watch timer, can be used to release stop mode because the watch timer operates in stop mode if the clock source of watch timer is sub clock. If system clock is sub clock, you can't use any interrupts to release stop mode. That is, you had better use the idle instruction instead of stop one when sub clock is selected as the system clock.

Please note the following conditions for Stop mode release:

???If you release stop mode using an internal or external interrupt, the current values in system and peripheral control registers are unchanged.

???If you use an internal or external interrupt for stop mode release, you can also program the duration of the oscillation stabilization interval. To do this, you must make the appropriate control and clock settings before entering stop mode.

???If you use an interrupt to release stop mode, the bit-pair setting for CLKCON.4/CLKCON.3 remains unchanged and the currently selected clock value is used.

???The internal or external interrupt is serviced when the stop mode release occurs. Following the IRET from the service routine, the instruction immediately following the one that initiated stop mode is executed.

IDLE MODE

Idle mode is invoked by the instruction IDLE (opcode 6FH). In Idle mode, CPU operations are halted while some peripherals remain active. During Idle mode, the internal clock signal is gated away from the CPU and from all but the following peripherals, which remain active:

???Interrupt logic

???Basic timer

???Timer 1 (Timer A and B)

???Watch timer

???LCD controller

I/O port pins retain the mode (input or output) they had at the time Idle mode was entered.

Idle Mode Release

You can release Idle mode in one of two ways:

1.Execute a reset. All system and peripheral control registers are reset to their default values and the contents of all data registers are retained. The reset automatically selects the slowest clock (1/16) because of the hardware reset value for the CLKCON register. If all external interrupts are masked in the IMR register, a reset is the only way you can release Idle mode.

2.Activate any enabled interrupt ??? internal or external. When you use an interrupt to release Idle mode, the 2-bit CLKCON.4/CLKCON.3 value remains unchanged, and the currently selected clock value is used. The interrupt is then serviced. When the return-from-interrupt condition (IRET) occurs, the instruction immediately following the one which initiated Idle mode is executed.

8-3

HARDWARE RESET VALUES

Table 8-1 list the values for CPU and system registers, peripheral control registers, and peripheral data registers following a RESET operation in normal operating mode. The following notation is used in these table to represent specific RESET values:

???A "1" or a "0" shows the RESET bit value as logic one or logic zero, respectively.

???An 'x' means that the bit value is undefined followingRESET.

???A dash ('???') means that the bit is either not used or not mapped.

Table 8-1. Register Values after RESET

8-4

S3C9228/P9228RESET and POWER-DOWN

Table 8-1. Register Values after RESET (Continued)

Location FFH is not mapped.

8-5

NOTES

8-6

9 I/O PORTS

OVERVIEW

The S3C9228/P9228 microcontroller has seven bit-programmable I/O ports, P0-P6. Port 0 is 6-bit port, port 1, port 2, and port 6 are 4-bit ports, port 3 is 2-bit port, and port 4 and port 5 are 8-bit ports. This gives a total of 36 I/O pins. Each port can be flexibly configured to meet application design requirements.

The CPU accesses ports by directly writing or reading port registers. No special I/O instructions are required. All ports of the S3C9228/P9228 except P0.4 and P0.5 can be configured to input or output mode. All LCD signal pins are shared with normal I/O ports.

Table 9-1 gives you a general overview of S3C9228 I/O port functions.

9-1

PORT DATA REGISTERS

Table 9-2 gives you an overview of the register locations of all seven S3C9228 I/O port data registers. Data registers for ports 1, 2, 3, 4, 5, and 6 have the general format shown in Figure 9-1.

Table 9-2. Port Data Register Summary

S3C9228 I/O Port Data Register Format (n = 0-6)

Pn.7 Pn.6 Pn.5 Pn.4 Pn.3 Pn.2 Pn.1 Pn.0

Figure 9-1. S3C9228 I/O Port Data Register Format

9-2

PORT 0

Port 0 is an 6-bit I/O port with individually configurable pins. Port 0 pins are accessed directly by writing or reading the port 0 data register, P0 at location E4H in page 0. P0.0-P0.3 can serve as inputs (with or without pull- up), as outputs (push-pull or open-drain) or you can be configured the following functions.

???Low-nibble pins (P0.0-P0.3): TAOUT,T1CLK, BUZ, INT

???High-nibble pins (P0.4-P0.5): push-pull output ports (only 44-QFP package)

Port 0 Control register (P0CON)

Port 0 has a 8-bit control register: P0CON for P0.0-P0.3. A reset clears the P0CON register to ???00H???, configuring pins to input mode. You use control register setting to select input or output mode (push-pull or open-drain) and enable the alternative functions.

When programming this port, please remember that any alternative peripheral I/O function you configure using the port 0 control register must also be enabled in the associated peripheral module.

Port 0 Pull-up Resistor Control Register (P0PUR)

Using the port 0 pull-up resistor control register, P0PUR (ECH, page 0), you can configure pull-up resistors to individual port 0 pins.

Port 0 Interrupt Enable, Pending, and Edge Selection Registers (P0INT, INTPND1.3-.0, P0EDGE)

To process external interrupts at the port 0 pins, three additional control registers are provided: the port 0 interrupt enable register P0INT (EDH, page 0), the port 0 interrupt pending bits INTPND1.3-.0 (D6H, page 0), and the port 0 interrupt edge selection register P0EDGE (EEH, page 0).

The port 0 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the INTPND1.3-.0 register at regular intervals.

When the interrupt enable bit of any port 0 pin is "1", a rising or falling edge at that pin will generate an interrupt request. The corresponding INTPND1 bit is then automatically set to "1" and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding INTPND1 bit.

9-3

Port 0 Control Register (P0CON)

EBH, Page 0, R/W

P0CON bit-pair pin configuration settings:

00 Schmitt trigger input mode (T1CLK)

01 Push-pull output mode

10N-channel open-drain output mode

11Alternative function (TAOUT, BUZ)

Figure 9-2. Port 0 Control Register (P0CON)

Port 0 Interrupt Control Register (P0INT)

EDH, Page 0, R/W

P0INT bit configuration settings:

0Disable interrupt

1Enable interrupt

Figure 9-3. Port 0 Interrupt Control Register (P0INT)

9-4

Port 0 Interrupt Pending Bits (INTPND1.3-.0)

D6H, Page 0, R/W

INTPND1 bit configuration settings:

0No interrupt pending (when read), clear pending bit (when write)

1Interrupt is pending (when read)

Figure 9-4. Port 0 Interrupt Pending Bits (INTPND1.3-.0)

Port 0 Interrupt Edge Selection Register (P0EDGE)

EEH, Page 0, R/W

P0EDGE bit configuration settings:

0Falling edge detection

1Rising edge detection

Figure 9-5. Port 0 Interrupt Edge Selection Register (P0EDGE)

Port 0 Pull-up Control Register (P0PUR)

ECH, Page 0, R/W

P0PUR bit configuration settings:

0Disable pull-up resistor

1Enable pull-up resistor

Figure 9-6. Port 0 Pull-up Control Register (P0PUR)

9-5

PORT 1

Port 1 is an 4-bit I/O port with individually configurable pins. Port 1 pins are accessed directly by writing or reading the port 1 data register, P1 at location E5H in page 0. P1.0-P1.3 can serve as inputs (with or without pull- up), as outputs (push-pull or open-drain) or you can be configured the following functions.

???Low-nibble pins (P1.0-P1.3): AD0-AD3, INT

Port 1 Control Register (P1CON)

Port 1 has a 8-bit control register: P1CON for P1.0-P1.3. A reset clears the P1CON register to "00H", configuring pins to input mode. You use control register setting to select input or output mode (push-pull or open-drain) and enable the alternative functions.

When programming this port, please remember that any alternative peripheral I/O function you configure using the port 1 control register must also be enabled in the associated peripheral module.

Port 1 Pull-up Resistor Control Register (P1PUR)

Using the port 1 pull-up resistor control register, P1PUR (F0H, page 0), you can configure pull-up resistors to individual port 1 pins.

Port 1 Interrupt Enable, Pending, and Edge Selection Registers (P1INT, INTPND1.7-.4, P1EDGE)

To process external interrupts at the port 1 pins, three additional control registers are provided: the port 1 interrupt enable register P1INT (F1H, page 0), the port 1 interrupt pending bits INTPND1.7-.4 (D6H, page 0), and the port 1 interrupt edge selection register P1EDGE (F2H, page 0).

The port 1 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the INTPND1.7-.4 register at regular intervals.

When the interrupt enable bit of any port 1 pin is "1", a rising or falling edge at that pin will generate an interrupt request. The corresponding INTPND1 bit is then automatically set to "1" and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding INTPND1 bit.

Port 1 Control Register (P1CON)

EFH, Page 0, R/W

P1CON bit-pair pin configuration settings:

00 Schmitt trigger input mode

01 Push-pull output mode

10N-channel open-drain output mode

11Alternative function (AD0,AD1, AD2, AD3)

Figure 9-7. Port 1 Control Register (P1CON)

9-6

Port 1 Interrupt Control Register (P1INT)

F1H, Page 0, R/W

P1INT bit configuration settings:

0Disable interrupt

1Enable interrupt

Figure 9-8. Port 1 Interrupt Control Register (P1INT)

Port 1 Interrupt Pending Bits (INTPND1.7-.4)

D6H, Page 0, R/W

INTPND1 bit configuration settings:

0No interrupt pending (when read), clear pending bit (when write)

1Interrupt is pending (when read)

Figure 9-9. Port 1 Interrupt Pending Bits (INTPND1.7-.4)

9-7

Port 1 Interrupt Edge Selection Register (P1EDGE)

F2H, Page 0, R/W

P1EDGE bit configuration settings:

0Falling edge detection

1Rising edge detection

Figure 9-10. Port 1 Interrupt Edge Selection Register (P1EDGE)

Port 1 Pull-up Control Register (P1PUR)

F0H, Page 0, R/W

P1PUR bit configuration settings:

0Disable pull-up resistor

1Enable pull-up resistor

Figure 9-11. Port 1 Pull-up Control Register (P1PUR)

9-8

PORT 2

Port 2 is an 4-bit I/O port with individually configurable pins. Port 2 pins are accessed directly by writing or reading the port 2 data register, P2 at location E6H in page 0. P2.0-P2.3 can serve as inputs (with or without pull- up), as outputs (push-pull or open-drain) or you can be configured the following functions.

???Low-nibble pins (P2.0-P2.3): SCK, SO, SI, SEG0-SEG1

Port 2 Control Register (P2CON)

Port 2 has a 8-bit control register: P2CON for P2.0-P2.3. A reset clears the P2CON register to "00H", configuring pins to input mode. You use control register setting to select input or output mode (push-pull or open-drain) and enable the alternative functions.

When programming this port, please remember that any alternative peripheral I/O function you configure using the port 2 control register must also be enabled in the associated peripheral module.

Port 2 Pull-up Resistor Control Register (P2PUR)

Using the port 2 pull-up resistor control register, P2PUR (F4H, page 0), you can configure pull-up resistors to individual port 2 pins.

Port 2 Control Register (P2CON)

F3H, Page 0, R/W

P2.3 P2.2/SI P2.1/SO/SEG0 P2.0/SCK/SEG1

P2CON bit-pair pin configuration settings:

00 Schmitt trigger input mode (SI,SCK)

01 Push-pull output mode

10N-channel open-drain output mode

11Alternative function (SCK, SO)

Figure 9-12. Port 2 Control Register (P2CON)

9-9

Port 2 Pull-up Control Register (P2PUR)

F4H, Page 0, R/W

P2PUR bit configuration settings:

0Disable pull-up resistor

1Enable pull-up resistor

Figure 9-13. Port 2 Pull-up Control Register (P2PUR)

9-10

PORT 3

Port 3 is an 2-bit I/O port with individually configurable pins. Port 3 pins are accessed directly by writing or reading the port 3 data register, P3 at location E7H in page 0. P3.0-P3.1 can serve as inputs (with or without pull- up, and high impedance input), as outputs (push-pull or open-drain) or you can be configured the following functions.

???Low-nibble pins (P3.0-P3.1): SEG2-SEG3, INTP

Port 3 Control Register (P3CON)

Port 3 has a 8-bit control register: P3CON for P3.0-P3.1. A reset clears the P3CON register to "00H", configuring pins to input mode. You use control register setting to select input or output mode (push-pull or open-drain).

Port 3 Pull-up Resistor Control Register (P3PUR)

Using the port 3 pull-up resistor control register, P3PUR (F6H, page 0), you can configure pull-up resistors to individually port 3 pins.

Port 3 Interrupt Enable, Pending, and Edge Selection Registers(P3INT, INTPND2.5-.4, P3EDGE)

To process external interrupts at the port 3 pins, three additional control registers are provided: the port 3 interrupt enable register P3INT (F7H, page 0), the port 3 interrupt pending bits INTPND2.5-.4 (D7H, page 0), and the port 3 interrupt edge selection register P3EDGE (F8H, page 0).

The port 3 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated. The application program detects interrupt requests by polling the INTPND2.5-.4 register at regular intervals.

When the interrupt enable bit of any port 3 pin is "1", a rising or falling edge at that pin will generate an interrupt request. The corresponding INTPND2 bit is then automatically set to "1" and the IRQ level goes low to signal the CPU that an interrupt request is waiting. When the CPU acknowledges the interrupt request, application software must the clear the pending condition by writing a "0" to the corresponding INTPND2 bit.

Port 3 Control Register (P3CON)

F5H, Page 0, R/W

P3CON bit-pair pin configuration settings:

00 Schmitt trigger input mode

01 Push-pull output mode

10N-channel open-drain output mode

11Not available

Figure 9-14. Port 3 Control Register (P3CON)

9-11

Port 3 Interrupt Control Register (P3INT)

F7H, Page 0, R/W

(INTP) (INTP)

P3INT bit configuration settings:

0Disable interrupt

1Enable interrupt

Figure 9-15. Port 3 Interrupt Control Register (P3INT)

Port 3 Interrupt Pending Bits (INTPND2.5-.4)

D7H, Page 0, R/W

INTPND2 bit configuration settings:

0No interrupt pending (when read), clear pending bit (when write)

1Interrupt is pending (when read)

Figure 9-16. Port 3 Interrupt Pending Bits (INTPND2.5-.4)

9-12

Port 3 Interrupt Edge Selection Register (P3EDGE)

F8H, Page 0, R/W

P3EDGE bit configuration settings:

0Falling edge detection

1Rising edge detection

Figure 9-17. Port 3 Interrupt Edge Selection Register (P3EDGE)

Port 3 Pull-up Control Register (P3PUR)

F6H, Page 0, R/W

P3PUR bit configuration settings:

0Disable pull-up resistor

1Enable pull-up resistor

Figure 9-18. Port 3 Pull-up Control Register (P3PUR)

9-13

PORT 4

Port 4 is an 8-bit I/O port with individually configurable pins. Port 4 pins are accessed directly by writing or reading the port 4 data register, P4 at location E8H in page 0. P4.0-P4.7 can serve as inputs or as push-pull, open-drain outputs. You can configure the following alternative functions with LCD port control register, LPOT:

???Low-nibble pins (P4.0-P4.3): SEG4-SEG7

???High-nibble pins (P4.4-P4.7): SEG8-SEG11

Port 4 Control Registers (P4CONH, P4CONL)

Port 4 has two 8-bit control registers: P4CONH for P4.4-P4.7 and P4CONL for P4.0-P4.3. A reset clears the P4CONH and P4CONL registers to "00H", configuring all pins to input mode. You use control registers setting to select input or output mode.

Port 4 Control Register, High Byte (P4CONH)

F9H, Page 0, R/W

P4.7/SEG11 P4.6/SEG10 P4.5/SEG9 P4.4/SEG8

P4CONH bit-pair pin configuration settings:

00 Input mode

01 Push-pull output mode

10N-channel open-drain output mode

11Input mode with pull-up

Figure 9-19. Port 4 High-Byte Control Register (P4CONH)

Port 4 Control Register, Low Byte (P4CONL)

FAH, Page 0, R/W

P4.3/SEG7 P4.2/SEG6 P4.1/SEG5 P4.0/SEG4

P4CONL bit-pair pin configuration settings:

00 Input mode

01 Push-pull output mode

10N-channel open-drain output mode

11Input mode with pull-up

Figure 9-20. Port 4 Low-Byte Control Register (P4CONL)

9-14

PORT 5

Port 5 is an 8-bit I/O port with individually configurable pins. Port 5 pins are accessed directly by writing or reading the port 5 data register, P5 at location E9H in page 0. P5.0-P5.7 can serve as inputs or as push-pull, open-drain outputs. You can configure the following alternative functions with LCD port control register, LPOT:

???Low-nibble pins (P5.0-P5.3): SEG12-SEG15

???High-nibble pins (P5.4-P5.7): SEG16-SEG19, COM4-COM7

Port 5 Control Registers (P5CONH, P5CONL)

Port 5 has two 8-bit control registers: P5CONH for P5.4-P5.7 and P4CONL for P5.0-P5.3. A reset clears the P5CONH and P5CONL registers to "00H", configuring all pins to input mode. You use control registers setting to select input or output mode.

Port 5 Control Register, High Byte (P5CONH)

FBH, Page 0, R/W

P5.6/SEG18/COM5 P5.4/SEG16/COM7

P5.7/SEG19/COM4 P5.5/SEG17/COM6

P5CONH bit-pair pin configuration settings:

00 Input mode

01 Push-pull output mode

10N-channel open-drain output mode

11Input mode with pull-up

Figure 9-21. Port 5 High-Byte Control Register (P5CONH)

Port 5 Control Register, Low Byte (P5CONL)

FCH, Page 0, R/W

P5.3/SEG15 P5.2/SEG14 P5.1/SEG13 P5.0/SEG12

P5CONL bit-pair pin configuration settings:

00 Input mode

01 Push-pull output mode

10N-channel open-drain output mode

11Input mode with pull-up

Figure 9-22. Port 5 Low-Byte Control Register (P5CONL)

9-15

PORT 6

Port 6 is an 4-bit I/O port with individually configurable pins. Port 6 pins are accessed directly by writing or reading the port 6 data register, P6 at location EAH in page 0. P6.0-P6.3 can serve as inputs or as push-pull, open-drain outputs. You can configure the following alternative functions with LCD port control register, LPOT:

???Low-nibble pins (P6.0-P6.3): COM0-COM3

Port 6 Control Register (P6CON)

Port 6 has a 8-bit control register: P6CONH for P6.0-P6.3. A reset clears the P6CON registers to "00H", configuring all pins to input mode. You use control registers setting to select input or output mode.

Port 6 Control Register, Low Byte (P6CON)

FDH, Page 0, R/W

P6.3/COM0 P6.2/COM1 P6.1/COM2 P6.0/COM3

P6CON bit-pair pin configuration settings:

00 Input mode

01 Push-pull output mode

10N-channel open-drain output mode

11Input mode with pull-up

Figure 9-23. Port 6 Control Register (P6CON)

9-16

10 BASIC TIMER

OVERVIEW

Basic timer (BT) can be used in two different ways:

???As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction.

???To signal the end of the required oscillation stabilization interval after a reset or a stop mode release.

The functional components of the basic timer block are:

???Clock frequency divider (fxx divided by 4096, 1024, 128, or 16) with multiplexer

???8-bit basic timer counter, BTCNT (DDH, read-only)

???Basic timer control register, BTCON (DCH, read/write)

10-1

BASIC TIMER CONTROL REGISTER (BTCON)

The basic timer control register, BTCON, is used to select the input clock frequency, to clear the basic timer counter and frequency dividers, and to enable or disable the watchdog timer function. It is located in page 0, address DCH, and is read/write addressable using Register addressing mode.

A reset clears BTCON to "00H". This enables the watchdog function and selects a basic timer clock frequency of fxx/4096. To disable the watchdog function, you must write the signature code ???1010B??? to the basic timer register control bits BTCON.7???BTCON.4.

The 8-bit basic timer counter, BTCNT (page 0, DDH), can be cleared at any time during normal operation by writing a "1" to BTCON.1. To clear the frequency dividers for the basic timer input clock and timer counters, you write a "1" to BTCON.0.

Basic TImer Control Register (BTCON)

DCH, R/W

Basic timer input clock selection bits: 00 = fXX/4096

01 = fXX/1024

10 = fXX/128

11 = fXX/16

Figure 10-1. Basic Timer Control Register (BTCON)

10-2

BASIC TIMER FUNCTION DESCRIPTION

Watchdog Timer Function

You can program the basic timer overflow signal (BTOVF) to generate a reset by setting BTCON.7???BTCON.4 to any value other than ???1010B???. (The ???1010B??? value disables the watchdog function.) A reset clears BTCON to ???00H???, automatically enabling the watchdog timer function. A reset also selects the CPU clock (as determined by the current CLKCON register setting), divided by 4096, as the BT clock.

A reset whenever a basic timer counter overflow occurs. During normal operation, the application program must prevent the overflow, and the accompanying reset operation, from occurring. To do this, the BTCNT value must be cleared (by writing a "1" to BTCON.1) at regular intervals.

If a system malfunction occurs due to circuit noise or some other error condition, the BT counter clear operation will not be executed and a basic timer overflow will occur, initiating a reset. In other words, during normal operation, the basic timer overflow loop (a bit 7 overflow of the 8-bit basic timer counter, BTCNT) is always broken by a BTCNT clear instruction. If a malfunction does occur, a reset is triggered automatically.

Oscillation Stabilization Interval Timer Function

You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt.

In stop mode, whenever a reset or an internal and an external interrupt occurs, the oscillator starts. The BTCNT value then starts increasing at the rate of fxx/4096 (for reset), or at the rate of the preset clock source (for an internal and an external interrupt). When BTCNT.3 overflows, a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation.

In summary, the following events occur when stop mode is released:

1.During stop mode, a power-on reset or an internal and an external interrupt occurs to trigger the stop mode release and oscillation starts.

2.If a power-on reset occurred, the basic timer counter will increase at the rate of fxx/4096. If an internal and an external interrupt is used to release stop mode, the BTCNT value increases at the rate of the preset clock source.

3.Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows.

4.When a BTCNT.3 overflow occurs, normal CPU operation resumes.

10-3

NOTE: During a power-on reset operation, the CPU is idle during the required oscillation stabilization interval (until bit 4 of the basic timer counter overflows).

Figure 10-2. Basic Timer Block Diagram

10-4

11 TIMER 1

ONE 16-BIT TIMER MODE (TIMER 1)

The 16-bit timer 1 is used in one 16-bit timer or two 8-bit timers mode. If TACON.7 is set to "1", timer 1 is used as a 16-bit timer. If TACON.7 is set to "0", timer 1 is used as two 8-bit timers.

???One 16-bit timer mode (Timer 1)

???Two 8-bit timers mode (Timer A and B)

OVERVIEW

The 16-bit timer 1 is an 16-bit general-purpose timer. Timer 1 has the interval timer mode by using the appropriate TACON setting.

Timer 1 has the following functional components:

???Clock frequency divider (fxx divided by 512, 256, 64, 8, or 1, fxt, and T1CLK: External clock) with multiplexer

???16-bit counter (TACNT, TBCNT), 16-bit comparator, and 16-bit reference data register (TADATA, TBDATA)

???Timer 1 match interrupt generation

???Timer 1 control register, TACON (page 0, BBH, read/write)

FUNCTION DESCRIPTION

Interval Timer Function

The timer 1 module can generate an interrupt: the timer 1 match interrupt (T1INT).

The T1INT pending condition should be cleared by software when it has been serviced. Even though T1INT is disabled, the application's service routine can detect a pending condition of T1INT by the software and execute it's sub-routine. When this case is used, the T1INT pending bit must be cleared by the application sub-routine by writing a "0" to the INTPND2.0 pending bit.

In interval timer mode, a match signal is generated when the counter value is identical to the values written to the timer 1 reference data registers, TADATA and TBDATA. The match signal generates a timer 1 match interrupt and clears the counter.

If, for example, you write the value 32H and 10H to TADATA and TBDATA, respectively, and 8EH to TACON, the counter will increment until it reaches 3210H. At this point, the timer 1 interrupt request is generated, the counter value is reset, and counting resumes.

11-1

Timer 1 Control Register (TACON)

You use the timer 1 control register, TACON, to

???Enable the timer 1 operating (interval timer)

???Select the timer 1 input clock frequency

???Clear the timer 1 counter, TACNT and TBCNT

???Enable the timer 1 interrupt

TACON is located in page 0, at address BBH, and is read/write addressable using register addressing mode.

A reset clears TACON to "00H". This sets timer 1 to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer 1 interrupt. You can clear the timer 1 counter at any time during normal operation by writing a "1" to TACON.3.

To enable the timer 1 interrupt, you must write TACON.7, TACON.2, and TACON.1 to "1".

To generate the exact time interval, you should write TACON.3 and INTPND2.0, which cleared counter and interrupt pending bit. To detect an interrupt pending condition when T1INT is disabled, the application program polls pending bit, INTPND.2.0. When a "1" is detected, a timer 1 interrupt is pending. When the T1INT sub- routine has been serviced, the pending condition must be cleared by software by writing a "0" to the timer 1 interrupt pending bit, INTPND2.0.

Timer A Control Register (TACON)

BBH, R/W

Figure 11-1. Timer 1 Control Register (TACON)

11-2

Figure 11-2. Timer 1 Block Diagram (One 16-bit Mode)

11-3

TWO 8-BIT TIMERS MODE (TIMER A and B)

OVERVIEW

The 8-bit timer A and B are the 8-bit general-purpose timers. Timer A and B have the interval timer mode by using the appropriate TACON and TBCON setting, respectively.

Timer A and B have the following functional components:

???Clock frequency divider with multiplexer

???fxx divided by 512, 256, 64, 8 or 1, fxt, and T1CLK (External clock) for timer A

???fxx divided by 512, 256, 64, 8 or 1, and fxt for timer B

???8-bit counter (TACNT, TBCNT), 8-bit comparator, and 8-bit reference data register (TADATA, TBDATA)

???Timer A have I/O pin for match output (TAOUT)

???Timer A match interrupt generation

???Timer A control register, TACON (page 0, BBH, read/write)

???Timer B match interrupt generation

???Timer B control register, TBCON (page 0, BAH, read/write)

Timer A and B Control Register (TACON, TBCON)

You use the timer A and B control register, TACON and TBCON, to

???Enable the timer A (interval timer mode) and B operating (interval timer mode)

???Select the timer A and B input clock frequency

???Clear the timer A and B counter, TACNT and TBCNT

???Enable the timer A and B interrupt

11-4

TACON and TBCON are located in page 0, at address BBH and BAH, and is read/write addressable using register addressing mode.

A reset clears TACON to "00H". This sets timer A to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer A interrupt. You can clear the timer A counter at any time during normal operation by writing a "1" to TACON.3.

A reset clears TBCON to "00H". This sets timer B to disable interval timer mode, selects an input clock frequency of fxx/512, and disables timer A interrupt. You can clear the timer B counter at any time during normal operation by writing a "1" to TBCON.3.

To enable the timer A interrupt (TAINT) and timer B interrupt (TBINT), you must write TACON.7 to "0", TACON.2 (TBCON.2) and TACON.1 (TBCON.1) to "1". To generate the exact time interval, you should write TACON.3 (TBCON.3) and INTPND2.0 (INTPND2.1), which cleared counter and interrupt pending bit. To detect an interrupt pending condition when TAINT and TBINT is disabled, the application program polls pending bit, INTPND2.0 and INTPND2.1. When a "1" is detected, a timer A interrupt (TAINT) and timer B interrupt (TBINT) is pending. When the TAINT and TBINT sub-routine has been serviced, the pending condition must be cleared by software by writing a "0" to the timer A and B interrupt pending bit, INTPND2.0 and INTPND2.1.

Timer A Control Register (TACON)

E4H, R/W

Figure 11-3. Timer A Control Register (TACON)

11-5

Figure 11-4. Timer B Control Register (TBCON)

11-6

FUNCTION DESCRIPTION

Interval Timer Function (Timer A and Timer B)

The timer A and B module can generate an interrupt: the timer A match interrupt (TAINT) and the timer B match interrupt (TBINT).

The timer A match interrupt pending condition (INTPND2.0) and the timer B match interrupt pending condition (INTPND2.1) must be cleared by software in the application's interrupt service by means of writing a "0" to the INTPND2.0 and INTPND2.1 interrupt pending bit.

Even though TAINT and TBINT are disabled, the application's service routine can detect a pending condition of TAINT and TBINT by the software and execute it's sub-routine. When this case is used, the TAINT and TBINT pending bit must be cleared by the application sub-routine by writing a "0" to the corresponding pending bit INTPND2.0 and INTPND2.1.

In interval timer mode, a match signal is generated when the counter value is identical to the values written to the timer A or timer B reference data registers, TADATA or TBDATA. The match signal generates corresponding match interrupt and clears the counter.

If, for example, you write the value 20H to TADATA and 0EH to TACON, the counter will increment until it reaches 20H. At this point, the timer A interrupt request is generated, the counter value is cleared, and counting resumes and you write the value 10H to TBDATA, "0" to TACON.7, and 0EH to TBCON, the counter will increment until it reaches 10H. At this point, TB interrupt request is generated, the counter value is cleared and counting resumes.

11-7

TADATA Register

Data Bus

NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer A)

Figure 11-5. Timer A Block Diagram(Two 8-bit Timers Mode)

11-8

NOTE: When two 8-bit timers mode (TACON.7 <- "0": Timer B)

Figure 11-6. Timer B Block Diagram (Two 8-bit Timers Mode)

11-9

NOTES

11-10

12 WATCH TIMER

OVERVIEW

Watch timer functions include real-time and watch-time measurement and interval timing for the system clock. To start watch timer operation, set bit 1 of the watch timer control register, WTCON.1 to "1".

And if you want to service watch timer overflow interrupt, then set the WTCON.6 to ???1???.

The watch timer overflow interrupt pending condition (INTPND2.3) must be cleared by software in the application's interrupt service routine by means of writing a "0" to the INTPND2.3 interrupt pending bit. After the watch timer starts and elapses a time, the watch timer interrupt pending bit (INTPND2.3) is

automatically set to "1", and interrupt requests commence in 3.91ms, 0.25, 0.5 and 1-second intervals by setting Watch timer speed selection bits (WTCON.3 ??? .2).

The watch timer can generate a steady 0.5 kHz, 1 kHz, 2 kHz, or 4 kHz signal to BUZ output pin for Buzzer. By setting WTCON.3 and WTCON.2 to "11b", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. High-speed mode is useful for timing events for program debugging sequences.

Also, you can select watch timer clock source by setting the WTCON.7 appropriately value.

The watch timer supplies the clock frequency for the LCD controller (fLCD ). Therefore, if the watch timer is disabled, the LCD controller does not operate.

Watch timer has the following functional components:

???Real Time and Watch-Time Measurement

???Using a Main or Sub Clock Source (Main clock divided by 27(fx/128) or Sub clock(fxt))

???Clock Source Generation for LCD Controller (fLCD )

???I/O pin for Buzzer Output Frequency Generator (P0.3, BUZ)

???Timing Tests in High-Speed Mode

???Watch timer overflow interrupt generation

???Watch timer control register, WTCON (page 0, DAH, read/write)

12-1

WATCH TIMER CONTROL REGISTER (WTCON)

The watch timer control register, WTCON is used to select the input clock source, the watch timer interrupt time and Buzzer signal, to enable or disable the watch timer function. It is located in page 0 at address DAH, and is read/write addressable using register addressing mode.

A reset clears WTCON to "00H". This disable the watch timer and select fx/128 as the watch timer clock. So, if you want to use the watch timer, you must write appropriate value to WTCON.

Watch Timer Control Register (WTCON)

DAH, R/W

Figure 12-1. Watch Timer Control Register (WTCON)

12-2

WATCH TIMER CIRCUIT DIAGRAM

Figure 12-2. Watch Timer Circuit Diagram

12-3

NOTES

12-4

13 LCD CONTROLLER/DRIVER

OVERVIEW

The S3C9228/P9228 microcontroller can directly drive an up-to-128-dot (16segments x 8 commons) LCD panel. Its LCD block has the following components:

???LCD controller/driver

???Display RAM for storing display data

???16 segment output pins (SEG0???SEG15)

???8 common output pins (COM0???COM7)

???Internal resistor circuit for LCD bias

To use the LCD controller, bit 2 in the watch mode register WMOD must be set to 1 because LCDCK is supplied by the watch timer.

The LCD mode control register, LMOD, is used to turn the LCD display on or off, to select LCD clock frequency, to turn the COM signal output on or off, to select bias and duty, and to switch the port 3 high impedance or normal I/O port. Data written to the LCD display RAM can be transferred to the segment signal pins automatically without program control.

The LCD port control register, LPOT, is used to determine the LCD signal pins used for display output.

When a sub clock is selected as the LCD clock source, the LCD display is enabled even during main clock stop and idle modes.

Figure 13-1. LCD Function Diagram

13-1

LCD CIRCUIT DIAGRAM

Figure 13-2. LCD Circuit Diagram

13-2

LCD RAM ADDRESS AREA

RAM addresses of page 1 are used as LCD data memory. When the bit value of a display segment is "1", the LCD display is turned on; when the bit value is "0", the display is turned off.

Display RAM data are sent out through segment pins SEG0???SEG19 using a direct memory access (DMA) method that is synchronized with the fLCD signal. RAM addresses in this location that are not used for LCD

display can be allocated to general-purpose use.

Figure 13-3. LCD Display Data RAM Organization

Table 13-1. Common and Segment Pins per Duty Cycle

13-3

LCD MODE CONTROL REGISTER (LMOD)

A LMOD is located in page 0, at address FEH, and is read/write addressable using register addressing mode. It has the following control functions.

???LCD duty and bias selection

???LCD clock selection

???LCD display control

???COMs signal output control

???P3 high impedance control

The LMOD register is used to turn the LCD display on/off, to select duty and bias, to select LCD clock, to control port 3 high impedance/normal I/O port, and to turn the COM signal output on/off. Following a RESET, all LMOD values are cleared to "0". This turns off the LCD display, select 1/3 duty and 1/3 bias, and select 256Hz for LCD clock.

The LCD clock signal determines the frequency of COM signal scanning of each segment output. This is also referred as the LCD frame frequency. Since the LCD clock is generated by watch timer clock (fw). The watch timer should be enabled when the LCD display is turned on.

LCD Mode Control Register (LMOD)

FEH, R/W

LCD display control bit 0 = Display off

1 = Normal display on

Figure 13-4. LCD Mode Control Register (LMOD)

13-4

LCD PORT CONTROL REGISTER

The LCD port control register LPOT is used to control LCD signal pins or normal I/O pins. Following a RESET, a LPOT values are cleared to "0".

LCD Port Control Register

D8H, R/W

SEG3/P3.0 selection bit: 0 = SEG port

1 = Normal I/O port

Figure 13-5. LCD Port Control Register

13-5

LCD VOLTAGE DIVIDING RESISTORS

Figure 13-6. Internal Voltage Dividing Resistor Connection

COMMON (COM) SIGNALS

The common signal output pin selection (COM pin selection) varies according to the selected duty cycle.

???In 1/3 duty mode, COM0-COM2 pins are selected

???In 1/4 duty mode, COM0-COM3 pins are selected

???In 1/8 duty mode, COM0-COM7 pins are selected

SEGMENT (SEG) SIGNALS

The 19 LCD segment signal pins are connected to corresponding display RAM locations at page 1. Bits of the display RAM are synchronized with the common signal output pins.

When the bit value of a display RAM location is "1", a select signal is sent to the corresponding segment pin. When the display bit is "0", a 'no-select' signal to the corresponding segment pin.

13-6

-VLCD

Figure 13-7. LCD Signal Waveforms (1/8 Duty, 1/4 Bias)

13-7

SEG0

Figure 13-8. LCD Signal Waveforms (1/4 Duty, 1/3 Bias)

13-8

VDD

VLC1(VLC2)

COM1

VLC3(VLC4)

VSS

VDD

VLC1(VLC2)

COM2

VLC3(VLC4)

VSS

VDD

VLC1(VLC2)

SEG0

VLC3(VLC4)

VSS

VDD

VLC1(VLC2)

SEG1

VLC3(VLC4)

VSS

+ VLCD

+ 1/3 VLCD

COM0-SEG00V

- 1/3 VLCD

- VLCD

Figure 13-9. LCD Signal Waveforms (1/3 Duty, 1/3 Bias)

13-9

NOTES

13-10

14 10-BIT ANALOG-TO-DIGITAL CONVERTER

OVERVIEW

The 10-bit A/D converter (ADC) module uses successive approximation logic to convert analog levels entering at one of the four input channels to equivalent 10-bit digital values. The analog input level must lie between the AVREF and AVSS values. The A/D converter has the following components:

???Analog comparator with successive approximation logic

???D/A converter logic (resistor string type)

???ADC control register (ADCON)

???Four multiplexed analog data input pins (AD0???AD3)

???10-bit A/D conversion data output register (ADDATAH/ADDATAL)

???4-bit digital input port (Alternately, I/O port)

FUNCTION DESCRIPTION

To initiate an analog-to-digital conversion procedure, at first you must set with alternative function for ADC input enable at port 1, the pin set with alternative function can be used for ADC analog input. And you write the channel selection data in the A/D converter control register ADCON.4???.5 to select one of the four analog input pins (AD0???3) and set the conversion start or enable bit, ADCON.0. The read-write ADCON register is located in page 0, at address D0H. The pins which are not used for ADC can be used for normal I/O.

During a normal conversion, ADC logic initially sets the successive approximation register to 800H (the approximate half-way point of an 10-bit register). This register is then updated automatically during each conversion step. The successive approximation block performs 10-bit conversions for one input channel at a time. You can dynamically select different channels by manipulating the channel selection bit value (ADCON.5??? 4) in the ADCON register. To start the A/D conversion, you should set the enable bit, ADCON.0. When a conversion is completed, ADCON.3, the end-of-conversion(EOC) bit is automatically set to 1 and the result is dumped into the ADDATAH/ADDATAL register where it can be read. The A/D converter then enters an idle state. Remember to read the contents of ADDATAH/ADDATAL before another conversion starts. Otherwise, the previous result will be overwritten by the next conversion result.

NOTE

Because the A/D converter has no sample-and-hold circuitry, it is very important that fluctuation in the analog level at the AD0???AD3 input pins during a conversion procedure be kept to an absolute minimum. Any change in the input level, perhaps due to noise, will invalidate the result. If the chip enters to STOP or IDLE mode in conversion process, there will be a leakage current path in A/D block. You must use STOP or IDLE mode after ADC operation is finished.

14-1

CONVERSION TIMING

The A/D conversion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set-up A/D conversion. Therefore, total of 50 clocks are required to complete an 10-bit conversion: When fxx/8 is selected for conversion clock with an 4.5 MHz fxx clock frequency, one clock cycle is 1.78 us. Each bit conversion requires 4 clocks, the conversion rate is calculated as follows:

4 clocks/bit ?? 10-bit + set-up time = 50 clocks, 50 clock ?? 1.78 us = 89 us at 0.56 MHz (4.5 MHz/8)

Note that A/D converter needs at least 25??s for conversion time.

A/D CONVERTER CONTROL REGISTER (ADCON)

The A/D converter control register, ADCON, is located at address D0H in page 0. It has three functions:

???Analog input pin selection (bits 4 and 5)

???End-of-conversion status detection (bit 3)

???ADC clock selection (bits 2 and 1)

???A/D operation start or enable (bit 0 )

After a reset, the start bit is turned off. You can select only one analog input channel at a time. Other analog input pins (AD0???AD3) can be selected dynamically by manipulating the ADCON.4???5 bits. And the pins not used for analog input can be used for normal I/O function.

A/D Converter Control Register (ADCON)

D0H, Page0, R/W (EOC bit is read-only)

Figure 14-1. A/D Converter Control Register (ADCON)

14-2

Conversion Data Register ADDATAH/ADDATAL

D1H/D2H, Page 0, Read Only

Figure 14-2. A/D Converter Data Register (ADDATAH/ADDATAL)

INTERNAL REFERENCE VOLTAGE LEVELS

In the ADC function block, the analog input voltage level is compared to the reference voltage. The analog input level must remain within the range VSS to VDD.

Different reference voltage levels are generated internally along the resistor tree during the analog conversion process for each conversion step. The reference voltage level for the first conversion bit is always 1/2 VDD.

BLOCK DIAGRAM

Figure 14-3. A/D Converter Functional Block Diagram

14-3

VDD

Analog AD0-AD3

Input Pin

Figure 14-4. Recommended A/D Converter Circuit for Highest Absolute Accuracy

14-4

15 SERIAL I/O INTERFACE

OVERVIEW

Serial I/O modules, SIO can interface with various types of external device that require serial data transfer. The components of SIO function block are:

???8-bit control register (SIOCON)

???Clock selector logic

???8-bit data buffer (SIODATA)

???8-bit prescaler (SIOPS)

???3-bit serial clock counter

???Serial data I/O pins (SI, SO)

???Serial clock input/output pin (SCK)

The SIO module can transmit or receive 8-bit serial data at a frequency determined by its corresponding control register settings. To ensure flexible data transmission rates, you can select an internal or external clock source.

PROGRAMMING PROCEDURE

To program the SIO module, follow these basic steps:

1.Configure the I/O pins at port (SCK/SI/SO) by loading the appropriate value to the P2CON register if necessary.

2.Load an 8-bit value to the SIOCON control register to properly configure the serial I/O module. In this operation, SIOCON.2 must be set to "1" to enable the data shifter.

3.For interrupt generation, set the serial I/O interrupt enable bit (SIOCON) to "1".

4.When you transmit data to the serial buffer, write data to SIODATA and set SIOCON.3 to 1, the shift operation starts.

5.When the shift operation (transmit/receive) is completed, the SIO pending bit (INTPND2.2) are set to "1" and SIO interrupt request is generated.

15-1

SIO CONTROL REGISTERS (SIOCON)

The control register for serial I/O interface module, SIOCON, is located at E1H in page 0. It has the control setting for SIO module.

???Clock source selection (internal or external) for shift clock

???Interrupt enable

???Edge selection for shift operation

???Clear 3-bit counter and start shift operation

???Shift operation (transmit) enable

???Mode selection (transmit/receive or receive-only)

???Data direction selection (MSB first or LSB first)

A reset clears the SIOCON value to "00H". This configures the corresponding module with an internal clock source at the SCK, selects receive-only operating mode, and clears the 3-bit counter. The data shift operation and the interrupt are disabled. The selected data direction is MSB-first.

Serial I/O Module Control Register (SIOCON)

E1H, Page 0, R/W

Data direction control bit:

0 = MSB-first mode

1 = LSB-first modeSIO shift operation enable bit:

0 = Disable shifter and clock counter

1 = Enable shifter and clock counter

SIO mode selection bit:

0 = Receive only mode

1 = Transmit/receive mode SIO counter clear and shift start bit: 0 = No action

1 = Clear 3-bit counter and start shifting

Shift clock edge selection bit:

0 = tX at falling edeges, rx at rising edges. 1 = tX at rising edeges, rx at falling edges.

Figure 15-1. Serial I/O Module Control Register (SIOCON)

15-2

SIO PRE-SCALER REGISTER (SIOPS)

The prescaler register for serial I/O interface module, SIOPS, are located at E3H in page 0.

The value stored in the SIO pre-scale register, SIOPS, lets you determine the SIO clock rate (baud rate) as follows:

Baud rate = Input clock (fxx/4)/(Prescaler value + 1), or SCK input clock.

SIO Pre-scaler Register (SIOPS)

E3H, Page 0, R/W

Baud rate = (fXX/4)/(SIOPS + 1)

Figure 15-2. SIO Prescaler Register (SIOPS)

SIO BLOCK DIAGRAM

Figure 15-3. SIO Functional Block Diagram

15-3

SERIAL I/O TIMING DIAGRAM (SIO)

Set SIOCON.3

Figure 15-4. Serial I/O Timing in Transmit/Receive Mode (Tx at falling, SIOCON.4 = 0)

Set SIOCON.3

Figure 15-5. Serial I/O Timing in Transmit/Receive Mode (Tx at rising, SIOCON.4 = 1)

15-4

16 ELECTRICAL DATA

OVERVIEW

In this chapter, S3C9228/P9228 electrical characteristics are presented in tables and graphs. The information is arranged in the following order:

???Absolute maximum ratings

???D.C. electrical characteristics

???Data retention supply voltage in Stop mode

???Stop mode release timing when initiated by an external interrupt

???Stop mode release timing when initiated by a Reset

???I/O capacitance

???A.C. electrical characteristics

???A/D converter electrical characteristics

???Input timing for external interrupt

???Input timing for RESET

???Serial data transfer timing

???Oscillation characteristics

???Oscillation stabilization time

???Operating voltage range

16-1

Table 16-1. Absolute Maximum Ratings

(TA = 25??C)

Table 16-2. D.C. Electrical Characteristics

(TA = ??? 25??C to + 85??C, VDD = 2.0 V to 5.5 V)

16-2

S3C9228/P9228ELECTRICAL DATA

Table 16-2. D.C. Electrical Characteristics (Continued)

(TA = ??? 25??C to + 85??C, VDD = 2.0 V to 5.5 V)

16-3

Table 16-2. D.C. Electrical Characteristics (Concluded)

(TA = ??? 25??C to + 85??C, VDD = 2.0 V to 5.5 V)

NOTES:

1.Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, and ADC.

2.IDD1 and IDD2 include power consumption for subsystem clock oscillation.

3.IDD3 and IDD4 are current when main system clock oscillation stops and the subsystem clock is used.

4.IDD5 is current when main system clock and subsystem clock oscillation stops.

16-4

Table 16-3. Data Retention Supply Voltage in Stop Mode

(TA = ??? 25 ??C to + 85 ??C)

NOTE: tWAIT is the same as 16 x 1/BT clock.

Figure 16-1. Stop Mode Release Timing When Initiated by an External Interrupt

16-5

Figure 16-2. Stop Mode Release Timing When Initiated by a RESET

Table 16-4. Input/Output Capacitance

(TA = 25 ??C, VDD = 0 V)

16-6

S3C9228/P9228ELECTRICAL DATA

Table 16-5. A.C. Electrical Characteristics

(TA = ??? 25??C to + 85??C, VDD = 2.0 V to 5.5 V)

16-7

NOTES:

1.'Conversion time' is the time required from the moment a conversion operation starts until it ends.

2.IADC is an operating current during A/D conversion.

Figure 16-3. Input Timing for External Interrupts

16-8

tRSL

RESET

0.2 VDD

Figure 16-4. Input Timing for RESET

Figure 16-5. Serial Data Transfer Timing

16-9

Table 16-7. Main Oscillation Characteristics

Table 16-8. Sub Oscillation Characteristics

(TA = ??? 25??C to + 85??C)

16-10

Table 16-9. Main Oscillation Stabilization Time

(TA = ??? 25 ??C to + 85 ??C, VDD = 2.0 V to 5.5 V)

Figure 16-6. Clock Timing Measurement at XIN

16-11

Table 16-10. Sub Oscillation Stabilization Time

(TA = ??? 25 ??C to + 85 ??C, VDD = 2.0 V to 5.5 V)

Figure 16-7. Clock Timing Measurement at XTIN

16-12

Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16)

Figure 16-8. Operating Voltage Range

16-13

NOTES

16-14

17 MECHANICAL DATA

OVERVIEW

The S3C9228/P9228 microcontroller is currently available in a 42-pin SDIP and 44-pin QFP package.

17-1

Figure 17-2. 44-QFP-1010B Package Dimensions

17-2

18 S3P9228 OTP

OVERVIEW

The S3P9228 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the S3C9228 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed by serial data format.

The S3P9228 is fully compatible with the S3C9228, both in function and in pin configuration. Because of its simple programming requirements, the S3P9228 is ideal for use as an evaluation chip for the S3C9228.

Figure 18-1. S3P9228 44-QFP Pin Assignments

18-1

Figure 18-2. S3P9228 42-SDIP Pin Assignments

18-2

Table 18-1. Descriptions of Pins Used to Read/Write the EPROM

NOTE: Parentheses indicate pin number for 42-SDIP package.

Table 18-2. Comparison of S3P9228 and S3C9228 Features

OPERATING MODE CHARACTERISTICS

When 12.5 V is supplied to the VPP(TEST) pin of the S3P72C8, the EPROM programming mode is entered.

The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 17-3 below.

Table 18-3. Operating Mode Selection Criteria

NOTE: "0" means Low level; "1" means High level.

18-3

Table 18-4. D.C. Electrical Characteristics

(TA = ??? 25??C to + 85??C, VDD = 2.0 V to 5.5 V)

NOTES:

1.Supply current does not include current drawn through internal pull-up resistors, LCD voltage dividing resistors, and ADC.

2.IDD1 and IDD2 include power consumption for subsystem clock oscillation.

3.IDD3 and IDD4 are current when main system clock oscillation stops and the subsystem clock is used.

4.IDD5 is current when main system clock and subsystem clock oscillation stops.

18-4

Instruction Clock = 1/4n x oscillator frequency (n = 1, 2, 8, 16)

Figure 18-3. Standard Operating Voltage Range

18-5

NOTES

18-6

19 DEVELOPMENT TOOLS

OVERVIEW

Samsung provides a powerful and easy-to-use development support system in turn key form. The development support system is configured with a host system, debugging tools, and support software. For the host system, any standard computer that operates with MS-DOS as its operating system can be used. One type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, SMDS2+, for S3C7, S3C8, S3C9 families of microcontrollers. The SMDS2+ is a new and improved version of SMDS2. Samsung also offers support software that includes debugger, assembler, and a program for setting options.

SHINE

Samsung Host Interface for In-Circuit Emulator, SHINE, is a multi-window based debugger for SMDS2+. SHINE provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. It has an advanced, multiple-windowed user interface that emphasizes ease of use. Each window can be sized, moved, scrolled, highlighted, added, or removed completely.

SAMA ASSEMBLER

The Samsung Arrangeable Microcontroller (SAM) Assembler, SAMA, is a universal assembler, and generates object code in standard hexadecimal format. Assembled program code includes the object code that is used for ROM data and required SMDS program control data. To assemble programs, SAMA requires a source file and an auxiliary definition (DEF) file with device specific information.

SASM86

The SASM86 is an relocatable assembler for Samsung's S3C9-seriesmicrocontrollers. The SASM86 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. The SASM86 supports macros and conditional assembly. It runs on the MS-DOS operating system. It produces the relocatable object code only, so the user should link object file. Object files can be linked with other object files and loaded into memory.

HEX2ROM

HEX2ROM file generates ROM code from HEX file which has been produced by assembler. ROM code must be needed to fabricate a microcontroller which has a mask ROM. When generating the ROM code (.OBJ file) by HEX2ROM, the value ???FF??? is filled into the unused ROM area up to the maximum ROM size of the target device automatically.

TARGET BOARDS

Target boards are available for all S3C9-series microcontrollers. All required target system cables and adapters are included with the device-specific target board.

19-1

Figure 19-1. SMDS Product Configuration (SMDS2+)

19-2

TB9228 TARGET BOARD

The TB9228 target board is used for the S3C9228 microcontroller. It is supported by the SMDS2+ development system.

Figure 19-2. TB9228 Target Board Configuration

19-3

NOTE: The following symbol in the "To User_VCC" Setting column indicates the electrical short (off) configuration:

19-4

SMDS2+ Selection (SAM8)

In order to write data into program memory that is available in SMDS2+, the target board should be selected to be for SMDS2+ through a switch as follows. Otherwise, the program memory writing function is not available.

Table 19-2. The SMDS2+ Tool Selection Setting

Table 19-3. Using Single Header Pins as the Input Path for External Trigger Sources

You can connect an external trigger source to one of the two external trigger channels (CH1 or CH2) for the SMDS2+ breakpoint and trace functions.

IDLE LED

The Green LED is ON when the evaluation chip (S3E9220) is in idle mode.

STOP LED

The Red LED is ON when the evaluation chip (S3E9220) is in stop mode.

19-5

Figure 19-3. Connectors (J101, J102) for TB9228

19-6

Figure 19-4. S3C9228 Probe Adapter for 42-SDIP Package

Figure 19-5. S3C9228 Probe Adapter for 44-QFP Package

19-7

NOTES

19-8

1 PRODUCT OVERVIEW

SAM88RCRI PRODUCT FAMILY

Samsung's SAM88RCRIfamily of 8-bit single-chip CMOS microcontrollers offer fast and efficient CPU, a wide range of integrated peripherals, and supports OTP device.

A dual address/data bus architecture and bit- or nibble-configurable I/O ports provide a flexible programming environment for applications with varied memory and I/O requirements. Timer/counters with selectable operating modes are included to support real-time operations.

S3C9228/P9228 MICROCONTROLLER

The S3C9228 can be used for dedicated control functions in a variety of applications, and is especially designed for application with FRS or etc.

The S3C9228/P9228 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is built around the powerful SAM88RCRI CPU core.

Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register space, the size of the internal register file was logically expanded. The S3C9228/P9228 has 8K-byte of program ROM, and 264-byte of RAM (including 16-byte of working register and 20-byte LCD display RAM).

Using the SAM88RCRI design approach, the following peripherals were integrated with the SAM88RCRI core:

???7 configurable I/O ports including ports shared with segment/common drive outputs

???10-bit programmable pins for external interrupts

???One 8-bit basic timer for oscillation stabilization and watch-dog functions

???Two 8-bit timer/counters with selectable operating modes

???Watch timer for real time

???4 channel A/D converter

???8-bit serial I/O interface

OTP

The S3C9228 microcontroller is also available in OTP (One Time Programmable) version. S3P9228 microcontroller has an on-chip 8K-byte one-time-programmable EPROM instead of masked ROM. The S3P9228 is comparable to S3C9228, both in function and in pin configuration.

1-1

1-2

BLOCK DIAGRAM

Figure 1-1. Block Diagram

1-3

PIN ASSIGNMENTS

Figure 1-2. S3C9228 44-QFP Pin Assignments

1-4

Figure 1-3. S3C9228 42-SDIP Pin Assignments

1-5

PIN DESCRIPTIONS

Table 1-1. Pin Descriptions

NOTE: Parentheses indicate pin number for 42-SDIP-600 package.

1-6

S3C9228/P9228PRODUCT OVERVIEW

Table 1-1. Pin Descriptions (Continued)

NOTE: Parentheses indicate pin number for 42-SDIP-600 package.

1-7

PIN CIRCUIT DIAGRAMS

VDD

Pull-Up

Resistor

RESET Noise Filter

Figure 1-4. Pin Circuit Type B

VDD

Data

Output

Output

Disable

VSS

Figure 1-5. Pin Circuit Type C

1-8

External

Interrupt

Input

Figure 1-7. Pin Circuit Type E-4

Figure 1-8. Pin Circuit Type F-16A

1-9

VLC1

VLC2

VLC3

Output

Disable

VLC4

VLC5

VSS

Figure 1-9. Pin Circuit Type H-23

1-10

1-11

1-12

2 ADDRESS SPACES

OVERVIEW

The S3C9228/P9228 microcontroller has three kinds of address space:

???Program memory (ROM)

???Internal register file

???LCD display register file

A 16-bit address bus supports program memory operations. Special instructions and related internal logic determine when the 16-bit bus carries addresses for program memory. A separate 8-bit register bus carries addresses and data between the CPU and the internal register file.

The S3C9228 has 8K bytes of mask-programmable program memory on-chip. The S3C9228/P9228 microcontroller has 244 bytes general-purpose registers in its internal register file and the 20 bytes for LCD display memory is implemented in the internal register file too. Fifty-six bytes in the register file are mapped for system and peripheral control functions.

2-1

PROGRAM MEMORY (ROM)

Program memory (ROM) stores program code or table data. The S3C9228 has 8K bytes of mask-programable program memory. The program memory address range is therefore 0H-1FFFH. The first 2 bytes of the ROM (0000H???0001H) are an interrupt vector address. The program reset address in the ROM is 0100H.

8K bytes Internal Program Memory Area

Figure 2-1. S3C9228/P9228 Program Memory Address Space

2-2

REGISTER ARCHITECTURE

The upper 72 bytes of the S3C9228/P9228's internal register file are addressed as working registers, system control registers and peripheral control registers. The lower 184 bytes of internal register file (00H???B7H) is called the general purpose register space.

For many SAM88RCRI microcontrollers, the addressable area of the internal register file is further expanded by the additional of one or more register pages at general purpose register space (00H???BFH). This register file expansion is implemented by page 1 in the S3C9228/P9228. The page 1 (20 ?? 8 bits) is for LCD display register and can be used as general-purpose registers.

Figure 2-2. Internal Register File Organization

2-3

COMMON WORKING REGISTER AREA (C0H???CFH)

The SAM88RCRI register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time.

This16-byte address range is called common area. That is, locations in this area can be used as working registers by operations that address any location on any page in the register file. Typically, these working registers serve as temporary buffers for data operations between different pages.

The Register (R) addressing mode can be used to access this area

Registers are addressed either as a single 8-bit register or as a paired 16-bit register. In 16-bit register pairs, the address of the first 8-bit register is always an even number and the address of the next register is an odd number. The most significant byte of the 16-bit data is always stored in the even-numbered register; the least significant byte is always stored in the next (+ 1) odd-numbered register.

Figure 2-3. 16-Bit Register Pairs

+ PROGRAMMING TIP ??? Addressing the Common Working Register Area

As the following examples show, you should access working registers in the common area, locations C0H???CFH, using working register addressing mode only.

2-4

SYSTEM STACK

S3C9-series microcontrollers use the system stack for subroutine calls and returns and to store data. The PUSH and POP instructions are used to control system stack operations. The S3C9228/P9228 architecture supports stack operations in the internal register file.

STACK OPERATIONS

Return addresses for procedure calls and interrupts and data are stored on the stack. The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction. When an interrupt occurs, the contents of the PC and the FLAGS register are pushed to the stack. The IRET instruction then pops these values back to their original locations. The stack address is always decremented before a push operation and incremented after a pop operation. The stack pointer (SP) always points to the stack frame stored on the top of the stack, as shown in Figure 2-4.

Figure 2-4. Stack Operations

STACK POINTER (SP)

Register location D9H contains the 8-bit stack pointer (SP) that is used for system stack operations. After a reset, the SP value is undetermined.

Because only internal memory space is implemented in the S3C9228/P9228, the SP must be initialized to an 8- bit value in the range 00H???B7H.

NOTE

In case a Stack Pointer is initialized to 00H, it is decreased to FFH when stack operation starts. This means that a Stack Pointer access invalid stack area.

2-5

+PROGRAMMING TIP ??? Standard Stack Operations Using PUSH and POP

The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions:

2-6

3 ADDRESSING MODES

OVERVIEW

Instructions that are stored in program memory are fetched for execution using the program counter. Instructions indicate the operation to be performed and the data to be operated on. Addressing mode is the method used to determine the location of the data operand. The operands specified in SAM88RCRI instructions may be condition codes, immediate data, or a location in the register file, program memory, or data memory.

The SAM88RCRI instruction set supports six explicit addressing modes. Not all of these addressing modes are available for each instruction. The addressing modes and their symbols are as follows:

???Register (R)

???Indirect Register (IR)

???Indexed (X)

???Direct Address (DA)

???Relative Address (RA)

???Immediate (IM)

3-1

REGISTER ADDRESSING MODE (R)

In Register addressing mode, the operand is the content of a specified register (see Figure 3-1). Working register addressing differs from Register addressing because it uses a 16-byte working register space in the register file and a 4-bit register within that space (see Figure 3-2).

Figure 3-1. Register Addressing

Figure 3-2. Working Register Addressing

3-2

INDIRECT REGISTER ADDRESSING MODE (IR)

In Indirect Register (IR) addressing mode, the content of the specified register or register pair is the address of the operand. Depending on the instruction used, the actual address may point to a register in the register file, to program memory (ROM), or to an external memory space (see Figures 3-3 through 3-6).

You can use any 8-bit register to indirectly address another register. Any 16-bit register pair can be used to indirectly address another memory location.

Figure 3-3. Indirect Register Addressing to Register File

3-3

INDIRECT REGISTER ADDRESSING MODE (Continued)

Register File

Figure 3-4. Indirect Register Addressing to Program Memory

3-4

INDIRECT REGISTER ADDRESSING MODE (Continued)

Figure 3-5. Indirect Working Register Addressing to Register File

3-5

INDIRECT REGISTER ADDRESSING MODE (Concluded)

Register File

CFH

Figure 3-6. Indirect Working Register Addressing to Program or Data Memory

3-6

INDEXED ADDRESSING MODE (X)

Indexed (X) addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address (see Figure 3-7). You can use Indexed addressing mode to access locations in the internal register file or in external memory.

In short offset Indexed addressing mode, the 8-bit displacement is treated as a signed integer in the range of ???128 to +127. This applies to external memory accesses only (see Figure 3-8).

For register file addressing, an 8-bit base address provided by the instruction is added to an 8-bit offset contained in a working register. For external memory accesses, the base address is stored in the working register pair designated in the instruction. The 8-bit or 16-bit offset given in the instruction is then added to the base address (see Figure 3-9).

The only instruction that supports Indexed addressing mode for the internal register file is the Load instruction (LD). The LDC and LDE instructions support Indexed addressing mode for internal program memory, external program memory, and for external data memory, when implemented.

Register File

Figure 3-7. Indexed Addressing to Register File

3-7

INDEXED ADDRESSING MODE (Continued)

Figure 3-8. Indexed Addressing to Program or Data Memory with Short Offset

3-8

INDEXED ADDRESSING MODE (Concluded)

Figure 3-9. Indexed Addressing to Program or Data Memory with Long Offset

3-9

DIRECT ADDRESS MODE (DA)

In Direct Address (DA) mode, the instruction provides the operand's 16-bit memory address. Jump (JP) and Call (CALL) instructions use this addressing mode to specify the 16-bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed.

The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory (LDC) or to external data memory (LDE), if implemented.

Figure 3-10. Direct Addressing for Load Instructions

3-10

DIRECT ADDRESS MODE (Continued)

Figure 3-11. Direct Addressing for Call and Jump Instructions

3-11

RELATIVE ADDRESS MODE (RA)

In Relative Address (RA) mode, a two's-complement signed displacement between ??? 128 and + 127 is specified in the instruction. The displacement value is then added to the current PC value. The result is the address of the next instruction to be executed. Before this addition occurs, the PC contains the address of the instruction immediately following the current instruction.

The instructions that support RA addressing is JR.

Program Memory

Next OPCODE

Program Memory

Address Used

Figure 3-12. Relative Addressing

IMMEDIATE MODE (IM)

In Immediate (IM) addressing mode, the operand value used in the instruction is the value supplied in the operand field itself. Immediate addressing mode is useful for loading constant values into registers.

Program Memory

OPERAND

OPCODE

(The Operand value is in the instruction)

Sample Instruction:

LD R0,#0AAH

Figure 3-13. Immediate Addressing

3-12

4 CONTROL REGISTERS

OVERVIEW

In this section, detailed descriptions of the S3C9228/P9228 control registers are presented in an easy-to-read format. These descriptions will help familiarize you with the mapped locations in the register file. You can also use them as a quick-reference source when writing application programs.

System and peripheral registers are summarized in Table 4-1. Figure 4-1 illustrates the important features of the standard register description format.

Control register descriptions are arranged in alphabetical order according to register mnemonic. More information about control registers is presented in the context of the various peripheral hardware descriptions in Part II of this manual.

4-1

CONTROL REGISTERSS3C9228/P9228

Table 4-1. System and Peripheral Control Registers (Page 0)

4-2

S3C9228/P9228CONTROL REGISTERS

Table 4-1. System and Peripheral Control Registers (Page 0)

4-3

Bit number(s) that is/are appended to the register name for bit addressing

0Operation dose not generate a carry or borrow condition

1Operation generates carry-out or borrow into high-order bit7

0Operation result is a non-zero value

1Operation result is zero

0 Operation generates positive number (MSB = "0")

1 Operation generates negative number (MSB = "1")

Figure 4-1. Register Description Format

4-4

S3C9228/P9228CONTROL REGISTERS

0Disable operation

1Start operation (automatically disable operation after conversion complete)

4-5

CONTROL REGISTERSS3C9228/P9228

0No effect

1Clear clock frequency dividers

NOTES

1.When "1" is written to BTCON.1, the basic timer counter value is cleared to "00H". Immediately following the write operation, the BTCON.1 value is automatically cleared to "0".

2.When "1" is written to BTCON.0, the corresponding frequency divider is cleared to "00H". Immediately following the write operation, the BTCON.0 value is automatically cleared to "0".

4-6

S3C9228/P9228CONTROL REGISTERS

0Enable IRQ for main or sub oscillator wake-up in power down mode

1Disable IRQ for main or sub oscillator wake-up in power down mode

0 Always logic zero

4-7

CONTROL REGISTERSS3C9228/P9228

0Operation result is a non-zero value

1Operation result is zero

0Operation generates a positive number (MSB = "0")

1Operation generates a negative number (MSB = "1")

4-8

S3C9228/P9228CONTROL REGISTERS

0No interrupt pending (when read), clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), Clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), Clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), Clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), Clear pending bit (when write)

1Interrupt is pending (when read)

NOTE: Refer to Page 5-6 to clear any pending bits.

4-9

CONTROL REGISTERSS3C9228/P9228

INTPND2 ??? Interrupt Pending Register 2D7H

0No interrupt pending (when read), clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), Clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), Clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), Clear pending bit (when write)

1Interrupt is pending (when read)

0No interrupt pending (when read), Clear pending bit (when write)

1Interrupt is pending (when read)

NOTE: Refer to Page 5-6 to clear any pending bits.

4-10

S3C9228/P9228CONTROL REGISTERS

0Normal COMs signal output

1COM pins are at high impedance

0Normal I/O

1High impedance input

0Display off (cut off the LCD voltage dividing resistors)

1Normal display on

4-11

CONTROL REGISTERSS3C9228/P9228

0SEG port

1Normal I/O port

0SEG port

1Normal I/O port

0SEG port

1Normal I/O port

0SEG port

1Normal I/O port

NOTE: SEG16-SEG19 are shared with COM4-COM7.

4-12

S3C9228/P9228CONTROL REGISTERS

0Main oscillator RUN

1Main oscillator STOP

0Sub oscillator RUN

1Sub oscillator STOP

4-13

CONTROL REGISTERSS3C9228/P9228

4-14

S3C9228/P9228CONTROL REGISTERS

0Disable interrupt

1Enable interrupt

0Disable interrupt

1Enable interrupt

0Disable interrupt

1Enable interrupt

0Disable interrupt

1Enable interrupt

4-15

CONTROL REGISTERSS3C9228/P9228

0Disable pull-up resistor

1Enable pull-up resistor

0Disable pull-up resistor

1Enable pull-up resistor

0Disable pull-up resistor

1Enable pull-up resistor

0Disable pull-up resistor

1Enable pull-up resistor

4-16

S3C9228/P9228CONTROL REGISTERS

0Falling edge interrupt

1Rising edge interrupt

0Falling edge interrupt

1Rising edge interrupt

0Falling edge interrupt

1Rising edge interrupt

0Falling edge interrupt

1Rising edge interrupt

4-17

CONTROL REGISTERSS3C9228/P9228

4-18

S3C9228/P9228CONTROL REGISTERS

0Disable interrupt

1Enable interrupt

0Disable interrupt

1Enable interrupt

0Disable interrupt

1Enable interrupt

0Disable interrupt

1Enable interrupt

4-19

CONTROL REGISTERSS3C9228/P9228

0Disable pull-up resistor

1Enable pull-up resistor

0Disable pull-up resistor

1Enable pull-up resistor

0Disable pull-up resistor

1Enable pull-up resistor

0Disable pull-up resistor

1Enable pull-up resistor

4-20

S3C9228/P9228CONTROL REGISTERS

0Falling edge interrupt

1Rising edge interrupt

0Falling edge interrupt

1Rising edge interrupt

0Falling edge interrupt

1Rising edge interrupt

0Falling edge interrupt

1Rising edge interrupt

4-21

CONTROL REGISTERSS3C9228/P9228

4-22

S3C9228/P9228CONTROL REGISTERS

0Disable pull-up resistor

1Enable pull-up resistor

0Disable pull-up resistor

1Enable pull-up resistor

0Disable pull-up resistor

1Enable pull-up resistor

0Disable pull-up resistor

1Enable pull-up resistor

4-23

CONTROL REGISTERSS3C9228/P9228

4-24

S3C9228/P9228CONTROL REGISTERS

0Disable interrupt

1Enable interrupt

0Disable interrupt

1Enable interrupt

4-25

CONTROL REGISTERSS3C9228/P9228

0Disable pull-up resistor

1Enable pull-up resistor

0Disable pull-up resistor

1Enable pull-up resistor

4-26

S3C9228/P9228CONTROL REGISTERS

0Falling edge interrupt

1Rising edge interrupt

0Falling edge interrupt

1Rising edge interrupt

4-27

CONTROL REGISTERSS3C9228/P9228

4-28

S3C9228/P9228CONTROL REGISTERS

4-29

CONTROL REGISTERSS3C9228/P9228

4-30

S3C9228/P9228CONTROL REGISTERS

4-31

CONTROL REGISTERSS3C9228/P9228

4-32

S3C9228/P9228CONTROL REGISTERS

0Internal clock (P.S clock)

1External clock (SCK)

0MSB-first mode

1LSB-first mode

0Receive-only mode

1Transmit/receive mode

0Tx at falling edges, Rx at rising edges

1Tx at rising edges, Rx at falling edges

0No action

1Clear 3-bit counter and start shifting

0Disable shifter and clock counter

1Enable shifter and clock counter

0Disable SIO interrupt

1Enable SIO interrupt

4-33

CONTROL REGISTERSS3C9228/P9228

NOTE: Before executing the STOP instruction, the STPCON register must be set to "10100101B". Otherwise the STOP instruction will not execute.

4-34