IBM_Switch_CMX58886CX

CMX58886CX cpuModules??? User???s Manual

RTD Document Number: BDM-610000050 Revision A

Trademarks

Advanced Digital I/O, aDIO, a2DIO, Autonomous SmartCal, cpuModule, dspFramework, dspModule, IDAN, HiDAN, HiDANplus, ???MIL Value for COTS prices???, multiPort, and PC/104EZ are trademarks, and ???Accessing the Analog World???, dataModule, RTD, and the RTD logo are registered trademarks of RTD Embedded Technologies, Inc. PS/2, PC/XT, PC/AT, and IBM are trademarks of International Business Machines Inc. MS-DOS, Windows, Windows 95, Windows 98, and Windows NT are trademarks of Microsoft Corporation. Linux is a registered trademark of Linus Torvalds. ROM-DOS is a trademark of Datalight, Inc. Intel is a registered trademark of Intel Corporation. M-Systems and DiskOnChip are trademarks or registered trademarks of M-Systems Flash Disk Pioneers, Ltd. PC/104 is a registered trademark of PC/104 Consortium. All other trademarks appearing in this document are the property of their respective owners.

Contents and specifications within this manual are subject to change without notice.

Revision History

CMX58886CX cpuModules

RTD's CMX58886CX cpuModule represents the latest in high-performance embedded computing solutions. It includes 400 MHz source-synchronous Front Side Bus (FSB), on-die 512kB L2 cache, and data pre-fetch logic. It uses a 333MHz DDR-SDRAM controller that can support up to 2.7 G-Bytes per second of memory bandwidth. All memory chips are soldered directly onto the board.

The video interface is provided by an Analog SVGA output and an LVDS flat panel output. The two outputs are independent, and can display separate images and display timings. Maximum resolution is 2048 x 1536.

High-speed peripheral connections include USB 2.0, with up to 480 Mb/sec data throughput. An ATA-100/66/33 IDE controller provides a fast connection to the hard drive. Network connectivity is provided by an integrated 10/100 Mbps Ethernet controller. Other features include two RS-232/422/485 COM ports, Parallel Port, and AC97 audio.

RTD has gone the extra mile to include additional advanced features for maximum flexibility. These include an ATA/IDE Disk Chip socket that allows a true IDE drive to be attached to the board, either socketed or soldered. A MultiPort can be configured as a standard EPP/ECP parallel port, a floppy drive port, or an Advanced Digital I/O (aDIO) port. An Advanced Watchdog Timer is provided that can generate and interrupt or reset when the timer expires. The DDR-SDRAM controller uses Error-Correcting-Codes (ECC) to correct single bit memory errors, and detect two-bit memory errors, providing for a more robust memory system. SDRAM is soldered directly to the board for high vibration resistance. The CMX58886CX is also available in a rugged, fanless IDAN enclosure.

LVDS Flat

Panel

(CN19) COM1 (CN7)

multiPort COM2 (CN6) (CN8)

Figure 1 CMX58886CX cpuModule (top view)

Thermal Monitor and Thermal Throttling

The Intel ?? Thermal Monitor is a feature on the CMX58886CX that automatically throttles the CPU when the CPU exceeds its thermal limit. The maximum temperature of the processor is defined as the temperature that the Thermal Monitor is activated. The thermal limit and duty cycle of the Thermal Monitor cannot be modified. The Thermal Monitor can be disabled by the BIOS for applications where deteministic speed is more important than device failure due to thermal runaway. In addition to the Thermal Monitor, conventional Thermal Throttling is also provided. This forces the CPU to skip clock cycles when it exceeds a thermal limit. The thermal limit and duty cycle of thermal throttling can be modified in the BIOS.

Error-Correction Codes

The Graphics and Memory Controller Hub (GMCH) may be configured in the BIOS setup to operate in an Error-Correction-Code (ECC) data integrity mode. ECC mode allows multiple bit error detection and single bit error correction. The GMCH generate an 8-bit code word for each 64-bit Qword of memory, and performs a full Qword write at a time so that an 8-bit code is sent with each write. Since the code word covers a full Qword, writes of less than a Qword require a read-merge-write operation. Consider a Dword write to memory. In this case, when in ECC mode, GMCH will read the Qword where the addressed Dword will be written, merge in the new Dword, generate a code covering the new Qword and finally write the entire Qword and code back to memory. Any correctable (single-bit) errors detected during the initial Qword read are corrected before merging the new Dword.

Memory with ECC enabled requires additional system memory resources. This will cause the integrated graphics engine to have less memory bandwidth for access to the graphics frame buffer. Because of this, the display may flicker at high resolutions when the graphics processor is fully utilized and ECC is enabled. ECC memory is supported with internal graphics only.

aDIO with Wake-on-aDIO

RTD???s exclusive multiPort??? allows the parallel port to be configured as an Advanced Digital I/O (aDIO???), ECP/ EPP parallel port, or a floppy drive. aDIO??? is 16 digital bits configured as 8 bit-direction programmable and 8-bit port-direction programmable I/O giving you any combination of inputs and outputs. Match, event, and strobe interrupt modes mean no more wasting valuable processor time polling digital inputs. Interrupts are generated when the 8 bit-direction programmable digital inputs match a pattern or on any value change event. Bit masking allows selecting any subgroup of eight bits. The strobe input latches data into the bit-programmable port and generates an interrupt. Any of the interrupt modes can be used to generate a wake event from any standby/powerdown mode.

Ordering Information

The CMX58886CX cpuModule is available with a 1.0 GHz processor and 256 or 512 MB of DDR SDRAM. The cpuModule can also be purchased as part of an Intelligent Data Acquisition Node (IDAN???) building block, which consists of the cpuModule and a milled aluminum IDAN frame. The IDAN building block can be used in just about any combination with other IDAN building blocks to create a simple but rugged PC/104 stack. Refer to Appendix C, IDAN??? Dimensions and Pinout, for more information. The CMX58886CX cpuModule can also be purchased as part of a custom-built RTD HiDAN??? or HiDANplus High Reliability Intelligent Data Acquisition Node. Contact RTD for more information on its high reliability PC/PCI-104 systems.

CMX58886CX Model Options

The basic cpuModule model options are shown below. Refer to the RTD website (www.rtd.com) for more detailed ordering information.

Table 1 CMX58886CX cpuModule Model Options

Cable Kits and Accessories

For maximum flexibility, RTD does not provide cables with the cpuModule. You may wish to purchase the CMX58886CX cpuModule cable kit (P/N XK-CM65), which contains:

???Multi-function utility harness (keyboard socket, battery, reset, speaker)

???Two serial port cables (DIL-10 to DSUB-9)

???Parallel port cable (DIL-26 to DSUB-25)

???Two IDE cables

???VGA monitor cable (DIL-10 to high density 15-pin DSUB)

???Power cable (DIL-12 to wire leads)

???Two USB cables (5-pin SIL to USB A)

???Audio Cable (DIL-10 to three Mini-Jacks)

???One Ethernet cable (DIL-10 to RJ-45)

A floppy drive cable kit (P/N XK-CM49) is also available for connecting to to the multiPort. This cable kit comes with:

???3.5??? HDD Floppy Drive with a multiPort interface board

???Two floppy cables

For additional accessories, refer to the RTD website.

Board Features

???1.0 GHz Intel Celeron M with thermal throttling

???400 MHz, source-synchronous Front Side Bus

???Math coprocessor

???Supports MMX and SSE2 instructions

???Internal Cache

???L1 - 32KB of instruction and 32KB data; L2 - 512kB

???256 or 512 Mbytes BGA DDR SDRAM

???Up to 333 MHz Data Rate

???ECC corrects single-bit memory errors and detects 2-bit errors

???Stackable 120-pin PCI bus

???4 Bus master add-on cards capable

???3.3V or 5V PCI bus signaling

???Advanced Thermal Management

???Thermal Throttling reduces clock speed to prevent thermal runaway

???Auto Fan Control only runs fan when needed

???SMBus Temperature Monitor for CPU and board temperature

???Mini Fan Heatsink with Auto Fan control

???Passive Structural Heatsink & Heatpipes in IDAN and HiDAN System Configurations

???Advanced Programmable Interrupt Controller (APIC)

???High resolution 100 MHz APIC timer

???24 interrupt channels with APIC enabled (15 in legacy PIC mode)

???Advanced Configuration and Power Interface (ACPI)

???ACPI 1.0 Compliant

???Supported power down modes: S1 (Power On Suspend), S3 (Suspend to RAM), S4 (Hibernate), and S5 (Soft-Off)

???CPU Clock Throttling and Clock Stop for C0 to C3 Support

???Wake events include:

???aDIO Interrupt

???Wake-on-LAN

???Real Time Clock

???COM port Ring

???Power Switch

???etc.

???Three (3) counter/timers (Intel 8254 compatible)

???Seven (7) DMA channels (Intel 8237 compatible)

???Y2K compliant Real-Time Clock (external battery required)

???Nonvolatile storage of CMOS settings without battery

???Watchdog timer

???Complete PC-compatible Single Board Computer

I/O

???AC97 Audio Support

???Selectable Headphone or Line level output

???Line level input

???Microphone input

???Fast Ethernet

???Ethernet Controller

???Intel 82562 Fast Ethernet PCI Controller

???Integrated 3KByte Transmit and 3Kbyte Receive FIFOs

???Physical Layer

???100Base-Tx and 10Base-T

???Full Duplex support

???Easy to Use

???Low Power Features

???LED Status

???Software configuration

???855GME SVGA controller Onboard with 3D Acceleration

???DirectX & OpenGL 3D Accelerator

???Analog SVGA Output

???LVDS Flat Panel output

???Resolution up to 2048 x 1536 pixels with 32K colors

???VGA, SVGA, XGA, SXGA, UXGA

???Up to 16 million colors

???64-bit AGP Hardware graphics-accelerator

???1MB to 64MB of shared DDR high-performance memory

???Software-configurable RS-232/422/485 serial ports

???16550 compatible UARTs for high-speed

???Termination resistors for RS-422/485

???multiPort function connector

???Parallel port

???SPP, PS/2 bi-directional, EPP & ECP

???Advanced Digital I/O (aDIO)

???One 8-bit port programmable as input or output

???Eight bit-programmable I/O with Advanced Digital Interrupt Modes

???Event Mode Interrupt generates an interrupt when any input bit changes

???Match Mode Interrupt generates an interrupt when input bits match a preset value

???External Strobe Mode latches 8 data inputs and generates and interrupt

???Two Strobes can be configured as readable inputs

???Floppy controller interface

???Interfaces with RTD's multiPort Floppy Drive and Cable Kit

???ESD protection

???Two USB 2.0 (Universal Serial Bus) Ports

???Supports 480 Mb/s (high-speed), 12Mb/s (full-speed), and 1.5Mbs (low speed) peripherals

???500 mA @ 5 Vdc provided per port

???USB Boot capability

???UltraDMA-100 / 66 / 33 Master Mode PCI EIDE Controller

???Transfer rate up to 100MB/sec using UltraDMA

???Increased reliability using UltraDMA-66 transfer protocols

???Support ATAPI compliant devices including DVD drives

???48-bit LBA support for hard drives larger than 137GB

???32 pin ATA/IDE Disk Chip Socket

???Miniature ATA/IDE Flash Disk Chip

???Capacities up to 4GB

???Natively supported by all major operating systems

???Utility port

???PC/AT compatible keyboard port

???PS/2 Mouse Port

???Speaker port (0.1W output)

???Hardware Reset input

???Battery input for Real Time Clock

???Soft Power Button input

???Power I/O

???Access to PCI-104 Bus pins

???Power ground, ??12, 5 & 3.3 VDC

BIOS

???RTD Enhanced AMI BIOS

???User-configurable using built-in Setup program

???Nonvolatile storage of CMOS settings without battery

???Boot Devices

???Standard Devices (floppy disk, hard disk, etc.)

???ATA/IDE Disk Chip

???USB Device

???Network

???Fail Safe Boot ROM

???Surface-mount Flash chip that holds ROM-DOS???

???Quick Boot mode

Block Diagram

The next figure shows a simplified block diagram of the CMX58886CX cpuModule.

SVGA/

LVDS Flat Panel

Figure 2 CMX58886CX cpuModule Simplified Block Diagram

You can easily customize the cpuModule by stacking PCI-104 modules such as video controllers, modems, LAN controllers, or analog and digital data acquisition modules. Stacking PCI-104 modules onto the cpuModule avoids expensive installations of backplanes and card cages, and preserves the module's compactness.

The cpuModule uses the RTD Enhanced AMI BIOS. Drivers in the BIOS allow booting from floppy disk, hard disk, ATA/IDE Disk Chip, or boot block flash, thus enabling the system to be used with traditional disk drives or nonmechanical drives. Boot from USB devices and network are also supported.

The cpuModule and BIOS are also compatible with most real-time operating systems for PC compatible computers, although these may require creation of custom drivers to use the aDIO and watchdog timer.

Specifications

Physical Characteristics

???Dimensions: 117mm L x 97mm W x 15mm H (4.6"L x 3.8"W x 0.6"H)

???Weight: Approximately 0.19 Kg (0.40 lbs.)

???PCB: 14-layer, mixed surface-mount and thru-hole

Power Consumption

Exact power consumption depends on the actual application. Table 2 lists power consumption for typical configurations and clock speeds.

Table 2 cpuModule Power Consumption

Operating Conditions

1.Because the cpuModule has an onboard +3.3V supply, an external +3.3V supply is not required. However, if a +3.3 V supply is installed in the system to power PC/104-Plus or PCI-104 expansion boards, it will be monitored by the CPU at power up.

2.The 12V and -12V rails are not used by the cpuModule. They are only connected between the bus connector and the power connector. Any requirements on these signals are driven by other components in the system.

3.5V Standby is used to power the board when the main supply is turned off (power down modes S3-S5). It is not required for board operation.

4.With proper cooling (See Thermal Management on page 65)

Chapter 2 Getting Started

For many users, the factory configuration of the CMX58886CX cpuModule can be used to get a PC/104 system operational. You can get your system up and running quickly by following the simple steps described in this chapter, which are:

1.Connect power.

2.Connect the utility harness.

3.Connect a keyboard.

4.Default BIOS configuration.

5.Fail Safe Boot ROM.

6.Connect a VGA monitor to the SVGA connector.

Refer to the remainder of this chapter for details on each of these steps.

Table 5 CMX58886CX Basic Connectors

WARNING If you connect power incorrectly, the module will almost certainly be damaged or destroyed. Such damage is not covered by the RTD warranty! Please verify connections to the module before applying power.

Power is normally supplied to the cpuModule through the PCI bus connectors (CN16). If you are placing the cpuModule onto a PC/104-Plus or PCI-104 stack that has a power supply, you do not need to make additional connections to supply power.

If you are using the cpuModule without a PCI-104 or PC/104-Plus stack or with a stack that does not include a power supply, refer to Auxiliary Power (CN3) on page 24 for more details.

Some PCI-104 and PC/104-Plus expansion cards may require +3.3V supplied on the PC/104-Plus (PCI) connector (CN16). To learn how to supply this voltage, refer to Auxiliary Power (CN3) on page 24 and Jumper Settings and Locations on page 80.

Connecting the Utility Cable

The multi-function connector (CN5) implements the following interfaces:

???PC/AT compatible keyboard

???PS/2 mouse port

???Speaker port (0.1W output)

???Hardware Reset input

???Battery input for Real Time Clock

???Soft Power Button input

To use these interfaces, you must connect to the utility port connector (CN5). The utility harness from the RTD cable kit provides a small speaker, two connectors for the keyboard and mouse, a push-button for resetting the PC/104-Plus or PCI-104 system, and a lithium battery to provide backup power for the real time clock.

Refer to Utility Port Connector (CN5) on page 26 to connect devices to the utility port connector .

Connecting a Keyboard

You may plug a PC/AT compatible keyboard directly into the circular DIN connector of the utility harness in the cable kit.

Note Many keyboards are switchable between PC/XT and AT operating modes, with the mode usually selected by a switch on the back or bottom of the keyboard. For correct operation with this cpuModule, you must select AT mode.

Connecting to the PC/104-Plus (PCI) Bus

Other PC/104-Plus or PCI-104 expansion boards may be connected to the cpuModule???s PC/104-Plus (PCI) bus connector. To connect expansion modules to the PC/104-Plus bus, follow the procedure below to ensure that stacking of the modules does not damage connectors or electronics.

WARNING Do not force the module onto the stack! Wiggling the module or applying too much pressure may damage it. If the module does not readily press into place, remove it, check for bent pins or out-of-place keying pins, and try again.

1.Turn off power to the PC/104-Plus or PCI-104 system or stack.

2.Select and install stand-offs to properly position the cpuModule on the stack.

3.Touch a grounded metal part of the rack to discharge any buildup of static electricity.

4.Remove the cpuModule from its anti-static bag.

5.Check that keying pins in the bus connector are properly positioned.

6.Check the stacking order; if a PCI to ISA bridge card is used to connect any PC/104 modules, make sure an XT bus card will not be placed between two AT bus cards or it will interrupt the AT bus signals.

7.Hold the cpuModule by its edges and orient it so the bus connector pins line up with the matching connector on the stack.

8.Gently and evenly press the cpuModule onto the PC/104-Plus or PCI-104 stack.

There are three additional considerations to make when using the PCI bus:

???Slot selection switches on add-in boards

???PCI bus expansion card power

???PCI bus signaling levels

Slot Selection Switches

Unlike PC/104 cards, PC/104-Plus and PCI-104 expansion cards have a "slot" selection switch or jumpers. In total, there are 4 PCI cards that can be stacked onto the cpuModule with switch positions 0 through 3. The distance from the CPU determines these switch settings. The card closest to the CPU is said to be in slot 0, the next closest slot 1 and so on to the final card as slot 3.

Note This requirement means that all PC/104-Plus and PCI-104 cards must be stacked either on the top or the bottom of the CPU, not on both sides.

The "slot" setting method may vary from manufacturer to manufacturer, but the concept is the same. The CPU is designed to provide the correct delay to the clock signals to compensate for the bus length. The correct switch setting ensures the proper clock delay setting, interrupt assignment, and bus grant/request channel assignment. Refer to the expansion board???s manual for the proper settings. Each expansion card must be in a different slot.

PCI Bus Expansion Card Power

+5 Volt DC

The +5 V power pins on the PC/104-Plus (PCI) bus are connected directly to the +5 V pins on the auxiliary power connector, CN3 (pins 2 and 8).

+3.3 Volt DC

The factory default configuration is to connect the +3.3 V pins on the PCI bus to the auxiliary power connector (CN3) by soldering pins 1???2 on solder blob, B3 (see Table 58 on page 82 for solder blob settings). This is to ensure that the cpuModule???s onboard +3.3V supply will not supply power to the PC/104-Plus connector while a PC/104-Plus or PCI-104 power supply is already powering the +3.3V pins.

To supply +3.3V to PC/104-Plus or PCI-104 expansion boards with the onboard +3.3 V power supply, change B3 from pins 1???2 to pins 2???3. In this configuration, the current limit of the +3.3V connection to the PCI +3.3V via B3 should not be exceeded (see Table 58 on page 82 for current limitation).

PCI Bus Signaling Levels

The PCI bus can operate at +3.3 V or +5 V signaling levels. The signaling levels for the I/O pins on a PCI bus card are determined by solder blob B1. The default is +3.3 V. Refer to Table 58 on page 82 for solder blob settings.

WARNING You will have to ensure that all your expansion cards can operate together at a single signaling level.

Booting the CMX58886CX cpuModule for the First Time

You can now apply power to the cpuModule. You will see:

???A greeting message from the VGA BIOS (if the VGA BIOS has a sign-on message)

???The cpuModule BIOS version information

???A message requesting you press Delete to enter the Setup program

If you don???t press Delete, the cpuModule will try to boot from the current settings. If you press Delete, the cpuModule will enter Setup. Once you have configured the cpuModule using Setup, save your changes and reboot.

Note You may miss the initial sign-on messages if your monitor takes a while to power on.

Note By default, cpuModules are shipped with Fail Safe Boot ROM enabled. When Fail Safe Boot ROM is enabled, the system will boot to it exclusively.

Auxiliary Power (CN3)

WARNING If you connect power incorrectly, the module will almost certainly be destroyed. Please verify power connections to the module before applying power.

Power can be conveyed to the module either through the PCI-104-Plus bus (CN16) or through the Auxiliary Power connector (CN3). The cpuModule only requires +5 VDC and ground for operation; however, other modules in the system may require +12 VDC, ???12 VDC, and ???5 VDC. In these instances, the corresponding inputs on the Auxiliary Power Connector (CN3) may be used to supply these voltages.

Insufficient current supply will prevent your cpuModule from booting. The gauge and length of the wire used for connecting power to the cpuModule must be taken into consideration. Some power connectors have clip leads on them and may have significant resistance. Make sure that the input voltage does not drop below +4.8 V at the +5 V power pins. (Refer to Table 2 on page 10 for the cpuModule???s power requirements). A good rule of thumb is to use wire that can supply twice the power required by the system.

Note Connect two separate wires to the +5V pins (2 and 8) on the power connector to ensure a good power supply connection. We recommend that no less than 18 gauge wire be used and the length of this wire should not exceed 3 ft. Always measure the voltage drop from your power supply to the power pins on the cpuModule. The voltage at pins (2 and 8) should be +5V.

Table 7 Auxiliary Power Connector (CN3)1

1.For more information on the ATX style signals, +5V Standby and PSON#, refer to the Power Management section in Chapter 4, Using the cpuModule.

Note The +3.3 V pins (10 and 12) on the auxiliary power connector (CN3) are connected to the +3.3 V pins on the PC-104-Plus bus by default. These pins be configured to supply power to PC/104-Plus or PCI-104 expansion. If +3.3 V is supplied to the PC/104-Plus connector from the onboard power supply, the +3.3V pins (10 and 12) are not connected. Refer to the B3 description in Table 58 on page 82 for more information.

Utility Port Connector (CN5)

The utility port connector implements the following functions:

???PC/AT compatible keyboard port

???PS/2 mouse port

???Speaker port (0.1W output)

???Hardware Reset input

???Battery input for Real Time Clock

???Soft Power Button input

Table 8 provides the pinout of the multi-function connector.

Table 8 Utility Port Connector (CN5)

Facing the connector pins, the pinout is:

Speaker

A speaker output is available on pins 1 and 2 of the multi-function connector. These outputs are controlled by a transistor to supply 0.1 W of power to an external speaker. The external speaker should have 8 ?? impedance and be connected between pins 1 and 2.

Keyboard

A PS/2 compatible keyboard can be connected to the multi-function connector. Usually PC keyboards come with a cable ending with a 5-pin male PS/2 connector. Table 9 lists the relationship between the multi-function connector pins and a standard PS/2 keyboard connector.

Table 9 Keyboard Connector Pins (CN5)

To ensure correct operation, check that the keyboard is either an AT compatible keyboard or a switchable XT/AT keyboard set to AT mode. Switchable keyboards are usually set by a switch on the back or bottom of the keyboard.

Mouse

A PS/2 compatible mouse can be connected to the multi-function connector. Table 10 lists the relationship between the multi-function connector pins and a standard PS/2 mouse connector.

Table 10 Mouse Connector Pins (CN5)

System Reset

Pin 3 of the multi-function connector allows connection of an external push-button to manually reset the system. The push-button should be normally open, and connect to ground when pushed.

Soft Power Button

Pin 4 of the multi-function connector allows connection of an external push-button to send a soft power signal to the system. The push-button should be normally open, and connect to ground when pushed. For more information on the modes of the Soft Power Button, refer to the Power Management section in Chapter 4, Using the cpuModule.

LVDS Flat Panel Video Connector (CN19)

Table 13 provides the pinout of the Flat Panel Video connector (CN19). FP_VCC can be either +5 V or +3.3 V, and is selected with jumper JP8. FP_VBKLT can be either +5 V or +12 V, and can be selected with JP9. See Jumper Settings and Locations on page 80 for more details.

Table 13 Flat Panel Video Connector (CN19)

Table 14 lists several LVDS panels that were tested with this cpuModule. When evaluating a panel to be used with this cpuModule, review the specifications of the tested panels to assure compatability.

Table 14 Tested LVDS Panels

ATA/IDE Disk Chip Socket (U16)

The ATA/IDE Disk Chip socket is a 32-pin socket that supports +3.3V or +5V miniature ATA/IDE flash disk chips. The socket allows a true IDE device to be attached to the board with either a socketed or soldered connection. Such true IDE devices are supported by all major operating systems, and do not require special drivers. The socket supports ATA/IDE flash disk chips with capacites up to 4GB..

WARNING Before installing a device in the ATA/IDE Disk Chip socket, the system must be configured in the correct mode. For details on configuring the socket, refer to Chapter 4, Using the cpuModule.

WARNING The ATA/IDE Disk Chip socket does not support conventional SSD memory devices or devices that install as a BIOS extension (such as the M-Systems DiskOnChip??). If such a device is installed, the cpuModule and device will almost certainly be destroyed.

Table 16 ATA/IDE Disk Chip Socket (U16)1

1.Signals marked with (#) are active low.

2.VDD may be set to +3.3 V or +5 V with jumper JP4

Serial Port 1 (CN7) and Serial Port 2 (CN8)

Serial Port 1 (COM1) is implemented on connector CN7, and Serial Port 2 is implemented on connector CN8. The serial ports are normally configured as PC compatible full-duplex RS-232 ports, but you may use the Setup program to reconfigure these ports as half-duplex RS-422 or full-duplex RS-422 or RS-485. If you reconfigure the ports, you must also select the I/O address and corresponding interrupt using Setup. Table 17 provides the available I/O addresses and corresponding interrupts.

Table 17 Serial Port Settings

Serial Port UART

The serial ports are implemented with a 16550-compatible UART (Universal Asynchronous Receiver/Transmitter). This UART is capable of baud rates up to 115.2 kbaud in 16450 and 16550A compatible mode, and includes a 16-byte FIFO. Refer to any standard PC-AT hardware reference for the register map of the UART. For more information about programming UARTs, refer to the Appendix.

RS-232 Serial Port (Default)

The default serial port mode is full-duplex RS-232. With this mode enabled, the serial port connectors must be connected to RS-232 compatible devices. Table 18 provides the serial port connector pinout and shows how to connect to an external DB-25 or DB-9 compatible serial connector.

Table 18 Serial Port in RS-232 Mode

Facing the serial port???s connector pins, the pinout is:

RS-422 or RS-485 Serial Port

You may use Setup to configure the serial ports as RS-422 or RS-485. In this case, you must connect the serial port to an RS-422 or RS-485 compatible device.

When using RS-422 or RS-485 mode, you can use the serial ports in either half-duplex (two-wire) or full-duplex (four-wire) configurations. For half-duplex (2-wire) operation, you must connect RXD+ to TXD+, and connect RXD??? to TXD???.

Note The cpuModule has a 120 ?? termination resistor. Termination is usually necessary on all RS-422 receivers and at the ends of the RS-485 bus.

Note If required, the termination resistor can be enabled by closing jumper JP1 for Serial Port 1 (COM1) or JP2 for Serial Port 2 (COM2).

When using full-duplex (typically in RS-422 mode), connect the ports as shown in Table 19.

Table 19 Full-Duplex Connections

When using half-duplex in RS-485 mode, connect the ports as shown in Table 20.

Table 20 Half-Duplex RS-485 Mode

RS-422 and RS-485 Mode Pinout

Table 21 provides the serial port connector pinout when RS-422 or RS-485 modes are enabled.

Table 21 Serial Port in RS-422/485 Mode

Facing the serial port connector, the pinout is:

Note When using the serial port in RS-485 mode, the serial transmitters are enabled and disabled under software control. The transmitters are enabled by manipulating the Request To Send (RTS*) signal of the serial port controller. This signal is controlled by writing bit 1 of the Modem Control Register (MCR) as follows:

???If MCR bit 1 = 1, then RTS* = 0, and serial transmitters are disabled

???If MCR bit 1 = 0, then RTS* = 1, and serial transmitters are enabled

Note For more information on the serial port registers, including the MCR, refer to the Serial Port Programming reference on page 99.

multiPort??? (CN6)

RTD???s exclusive multiPort can be configured as an Advanced Digital I/O (aDIO???), a parallel port, or a floppy drive. Refer to Chapter 4, Using the cpuModule, to configure the multiPort.

multiPort Configured as an Advanced Digital I/O (aDIO???) Port

The mulitPort connector (CN6) can be configured as an aDIO port. aDIO is 16 digital bits configured as 8-bit programmable and 8-bit port programmable I/O, providing any combination of inputs and outputs. Match, event, and strobe interrupt modes mean no more wasting valuable processor time polling digital inputs.

Interrupts are generated when the 8-bit programmable digital inputs match a pattern, or on any value change event. Bit masking allows selecting any subgroup of 8 bits. The strobe input latches data into the bit programmable port and generates an interrupt. Refer to multiPort: Advanced Digital I/O Ports (aDIO???) on page 56 for information on programming the multiPort.

Table 22 multiPort aDIO Pinout

multiPort Configured as a Parallel Port

The parallel port is available on connector CN6. Make sure the multiPort in the BIOS Setup is configured to parallel port. You can use the BIOS Setup to select the parallel port???s address and associated interrupt, and choose between its operational modes (SPP, ECP, EPP 1.7, and EPP 1.9).

The pinout of the connector enables a ribbon cable to be connected directly to a DB-25 connector, thus providing a standard PC compatible port.

Note For correct operation, keep the length of the cable connecting the cpuModule and parallel device less than 3 meters (10 feet).

Table 23 lists the parallel port signals and explains how to connect it to a DB-25 connector to obtain a PC compatible port.

Table 23 multiPort Connector (CN6) as a Parallel Port

PC/104-Plus PCI Bus Signals

The following are brief descriptions of the PC/104-Plus PCI bus signals.

Address and Data

AD[31:00] ??? Address and Data are multiplexed. A bus transaction consists of an address cycle followed by one or more data cycles.

C/BE[3:0]# ??? Bus Command/Byte Enables are multiplexed. During the address cycle, the command is defined. During the Data cycle, they define the byte enables.

PAR ??? Parity is even on AD[31:00] and C/BE[3:0]# and is required.

Interface Control Pins

FRAME# ??? Frame is driven by the current master to indicate the start of a transaction and will remain active until the final data cycle.

TRDY# ??? Target Ready indicates the selected devices ability to complete the current data cycle of the transaction. Both IRDY# and TRDY# must be asserted to terminate a data cycle.

IRDY# ??? Initiator Ready indicates the master's ability to complete the current data cycle of the transaction.

STOP# ??? Stop indicates the current selected device is requesting the master to stop the current transaction.

DEVSEL# ??? Device Select is driven by the target device when its address is decoded.

IDSEL[3:0] ??? Initialization Device Select is used as a chip-select during configuration.

LOCK# ??? Lock indicates an operation that may require multiple transactions to complete.

Error Reporting

PERR# ??? Parity Error is for reporting data parity errors.

SERR# ??? System Error is for reporting address parity errors.

Arbitration (Bus Masters Only)

REQ[3:0]# ??? Request indicates to the arbitrator that this device desires use of the bus.

GNT[3:0]# ??? Grant indicates to the requesting device that access has been granted.

System

CLK ??? Clock provides timing for all transactions on the PCI bus.

RST# ??? Reset is used to bring PCI-specific registers to a known state.

Interrupts

INTA# ??? Interrupt A is used to request Interrupts.

INTB# ??? Interrupt B is used to request Interrupts only for multi-function devices.

INTC# ??? Interrupt C is used to request Interrupts only for multi-function devices.

INTD# ??? Interrupt D is used to request Interrupts only for multi-function devices.

Power Supplies and VIO

+5 V ??? +5 V supply connected to PC/104 bus and auxiliary power connector (CN3) +5 V supplies.

+12 V ??? +12 V supply connected to PC/104 bus and auxiliary power connector (CN3) +12 V supplies.

???12 V ??? ???12 V supply connected to PC/104 bus and auxiliary power connector (CN3) ???12 V supplies.

+3.3 V ??? The +3.3 V pins on the PC/104-Plus (PCI) connector may be supplied by the onboard +3.3V power supply, however this is not the the default configuration. To supply +3.3V to PC/104-Plus or PCI-104 expansion cards via these pins, solder blob B3 must be modified. For more information refer toTable 58 on page 82.

VIO ??? This signal is typically the I/O power to the bus drivers on a PCI bus card. Signaling level is determined by solder blob B1. The default is +3.3 V. Refer to Table 58 on page 82 for solder blob settings.

ATX Power Management Signals (optional)

If an ATX power supply is connected to the system, the following signals listed below may be used to wake the system from low power modes. For more information on these signals, refer to the Power Management section on page 66.

+5V_STDBY ??? Some low power modes require that +5 V standby power is applied to the cpuModule during the wake event. This signal is an input to the CPU.

PME# ??? Power Management Event input

PSON# ??? This is an active low open-drain output used to turn the power supply on when the system is exiting a low power state.

Note Use of these signals will require board customization. For more information, contact the factory.

Bridge Link (CN4)

The Bridge Link connector allows devices that requires Legacy/ISA interrupts to inteface with the cpuModule. When ISA devices are installed in the system (via a PCI to ISA bridge card), the Bridge Link connector provides Legacy/ISA DMA request signals, as well as a serial interrupt signal which permits access to all available system interrupts.

Multiple devices may utilize the serial interrupt signal, SERIRQ, which is decoded on the cpuModule. Only one device may use the DMA request and grant signal pair.

Table 29 Bridge Link (CN4)

Facing the connector pins, the pinout is:

SERIRQGND

DMAGNT DMAREQ

External Power Management (CN12)

An external power management connector (CN12) is available for external devices to wake the system from low power states. Some low power modes require that +5 V standby power is applied to the cpuModule during the wake event.

For more information on power management, including a description of the board???s supported wake options, refer to the Power Management section on page 66.

Table 30 External Power Managment (CN12)

Optional RTC Battery Input (CN13)

The optional RTC battery input is the connection for an external backup battery. This battery is used by the cpuModule when system power is removed in order to preserve the date and time in the real time clock.

Connecting a battery is only required to maintain time when power is completely removed from the cpuModule. A battery is not required for board operation.

Table 31 Optional RTC Battery Input (CN13)

WARNING This optional RTC battery connector (CN13) should be left unconnected if the utility port connector (CN5) has a battery connected.

Fan Power, +5 V (CN14)

If a fan is required to cool the cpuModule, it can be wired to CN14, which provides a continuous connection to +5 V and ground.

Table 32 Fan Power, +5 V (CN14)

Note To utilize the thermal fan mode feature in the BIOS, the fan must be connected to CN15

The RTD Enhanced AMI BIOS

The RTD Enhanced AMI BIOS is software that interfaces hardware-specific features of the cpuModule to an operating system (OS). Physically, the BIOS software is stored in a Flash EPROM on the cpuModule. Functions of the BIOS are divided into two parts.

The first part of the BIOS is known as POST (power-on self-test) software, and it is active from the time power is applied until an OS boots (begins execution). POST software performs a series of hardware tests, sets up the machine as defined in Setup, and begins the boot of the OS.

The second part of the BIOS is known as the CORE BIOS. It is the normal interface between cpuModule hardware and the OS which is in control. It is active from the time the OS boots until the cpuModule is turned off. The CORE BIOS provides the system with a series of software interrupts to control various hardware devices.

Configuring the RTD Enhanced AMI BIOS

The cpuModule Setup program allows you to customize the cpuModule's configuration. Selections made in Setup are stored on the board and are read by the BIOS at power-on.

Entering the BIOS Setup

You can run Setup by rebooting the cpuModule and repeatedly pressing the Delete key. When you are finished with Setup, save your changes and exit. The system will automatically reboot

Field Selection

To movebetween fields in Setup, use the keys listed below.

Main Menu Setup Fields

The following is a list of Main Menu Setup fields.

Table 35 Main Menu Setup Fields

Note Future BIOS versions may have slightly different setup menus and options.

Power On Self Test (POST) Codes

Each POST Code represents a series of events that take place in a system during the POST. If the POST fails during a particular POST Code, the system will not boot as expected.

The BIOS uses I/O port 80h to store the active POST Code. A POST Code board is a tool that is used to display the POST Codes on I/O port 80h. This is usually accomplished with two 7-segment LEDs. Such a board is useful for debugging a system that is unable to boot.

Booting to Boot Block Flash with Fail Safe Boot ROM

Note Boards are shipped with Fail Safe Boot ROM enabled. When Fail Safe Boot ROM is enabled, the system will boot to it exclusively.

The Fail Safe Boot ROM is a minimal build of ROM-DOS??? located inside a surface-mounted Boot Block Flash chip. Boot Block Flash is a write-protected flash device that contains the BIOS and extra room where the Fail Safe Boot ROM is stored. Additionally, Fail Safe Boot ROM is an emergency interface accessible by an external computer. The ROM DISK contains utilities for remote access to the system???s disk drives. Due to the size of the flash chip, Fail Safe Boot ROM contains an abbreviated selection of the ROM-DOS??? utilities; however, the complete ROM-DOS??? is contained on a CD shipped with the cpuModule.

The purpose of the Fail Safe Boot ROM is to make the cpuModule bootable upon receipt. The Fail Safe Boot ROM can be used as an indicator of the module???s functionality when booting problems arise with another operating system. This test can be accomplished by enabling the Fail Safe Boot ROM in the Boot section of the BIOS Setup Utility. Enabling this option forces the cpuModule to boot to Fail Safe Boot ROM.

To boot to the Fail Safe Boot ROM, install jumper JP5, and apply power to the system.

Note If power is applied to the system while JP5 is installed, the multi-color LED will turn red.

I/O Address Map

As with all standard PC/104 boards, the I/O space is addressed by 10 address lines (SA0???SA9). This allows 210 or 1024 distinct I/O addresses. Any add-on modules you install must therefore use I/O addresses in the range of 0???1023 (decimal) or 000???3FF (hex).

Note If you add any PC/104 modules or other peripherals to the system you must ensure they do not use reserved addresses listed below, or malfunctions will occur. The exception to this is if the resource has been released by the user.

Table 37 lists I/O addresses reserved for the CMX58886CX cpuModule.

Table 37 I/O Addresses Reserved for the CMX58886CX cpuModule

1.If a floppy or IDE controller is not connected to the system, the I/O addresses listed will not be occupied.

2.If a PS/2 mouse is not connected to the system, the I/O addresses listed will not be occupied.

3.Only one of the I/O addresses shown for a serial port is active at any time. You can use Setup to select which one is active or to disable it entirely.

4.If aDIO is disabled, the I/O addresses listed will not be occupied.

5.If watchdog timer is disabled, the I/O addresses listed will not be occupied.

Hardware Interrupts

Note If you add any expansion modules or other peripherals to the system, you must ensure they do not use interrupts needed by the cpuModule, or malfunctions will occur.

The CMX58886CX cpuModule supports the standard PC interrupts listed in Table 38. Interrupts not in use by hardware on the cpuModule itself are listed as available. Similarly, if the operating system is using APIC, more IRQs will be available.

Table 38 Hardware Interrupts Used on the CMX58886CX cpuModule

1Keyboard

2Cascade of IRQ 8???15

3COM2

4COM1

5Available

61Floppy

7Printer

8Real Time Clock

9Available, routed to IRQ 2

10Available

11Available

12Bus Mouse

15ATA/IDE Disk Chip socket

1.Floppy disk interrupt, INT6, is available for use if no floppy disk is present in the system and floppy disk is disabled in Setup.

2.Hard disk interrupt, INT14, is available for use if no hard disk drive is present in the system and hard disk is disabled in Setup.

3.IRQs 14 and 15 may be available if the IDE controller is configured in Native Mode (refer to IDE Controller Configuration ???page 61)

Note The cpuModule has onboard PCI devices that will claim IRQ lines. In some instances, a PCI device will claim an IRQ line that is required by a legacy device. To reserve an IRQ for a legacy device, refer to the PnP/PCI Configuration Setup fields in the BIOS.

For external devices that require Legacy/ISA interrupts, a serial interrupt signal is available which permits access to the CPU???s hardware interrupts. One pair of Legacy/ISA DMA request/grant signals are also available. For more information on the serial interrupt signal, and the DMA request/grand pair, refer to Bridge Link (CN4) in Chapter 3, Connecting the cpuModule

multiPort: Advanced Digital I/O Ports (aDIO???)

Ensure that the BIOS setup has the multiPort set to aDIO mode. This board supports 16 bits of TTL/CMOS compatible digital I/O (TTL signaling). Use the BIOS setup to set the multiPort into its aDIO mode. These I/O lines are grouped into two ports, Port 0 and Port 1. Port 0 is bit programmable; Port 1 is byte programmable. Port 0 supports RTD???s Advanced Digital Interrupt modes. The two modes are match and event. Match mode generates an interrupt when an 8-bit pattern is received in parallel that matches the match mask register. Event mode generates an interrupt when a change occurs on any bit. In either mode, masking can be used to monitor selected lines.

When the CPU boots, all digital I/O lines are programmed as inputs, meaning that the digital I/O line???s initial state is undetermined. If the digital I/O lines must power up to a known state, an external 10 k?? resistor must be added to pull the line high or low.

The 8-bit control read/write registers for the digital I/O lines are located from I/O address 450h to 453h. These registers are written to zero upon power up. From 450h to 453h, the name of these registers are Port 0 data,

Port 1 data, Multi-Function, and DIO-Control register.

Note RTD provides drivers that support the aDIO interface on popular operating systems. RTD recommends using these drivers instead of accessing the registers directly.

Digital I/O Register Set

Table 39 Port 0 Data I/O Address 450h

Port 0 Data register is a read/write bit direction programmable register. A particular bit can be set to input or output. A read of an input bit returns the value of port 0. A read of an output bit returns the last value written to Port 0. A write to an output bit sends that value to port 0.

Table 40 Port 1 Data I/O Address 451h

Port 1 Data register is a read/write byte direction programmable register. A read on this register when it is programmed to input will read the value at the multiPort connector. A write on this register when it is programmed as output will write the value to the multiPort connector. A read on this register when it is set to output will read the last value sent to the multiPort connector.

Table 41 Multi-Function I/O Address 452h

The multi-function register is a read/write register whose contents are set by the DIO-Control register. See the DIO-Control register description for a description of this register.

Table 42 DIO-Control I/O Address 453h???Read Access

Table 43 DIO-Control I/O Address 453h???Write Access

A read to this register Clears the IRQs and a write to this register sets the DIO-Compare, DIO- Mask, DIO-Control, Port 1, and Port 0 to zeros. A write to this register is used to clear the board.

Port 0 Direction Register:

Writing a zero to a bit in this register makes the corresponding pin of the multiPort connector an input. Writing a one to a bit in this register makes the corresponding pin of the multiPort connector an output.

Mask Register:

Writing a zero to a bit in this register will not mask off the corresponding bit in the DIO-Compare register. Writing a one to a bit in this register masks off the corresponding bit in the DIO-Compare register. When all bits are masked off the aDIOs comparator is disabled. This condition means Event and Match mode will not generate an interrupt. This register is used by Event and Match modes.

Compare Register:

A Read/Write register used for Match Mode. Bit values in this register that are not masked off are compared against the value on Port 0. A Match or Event causes bit 6 of DIO-Control to be set and if the aDIO is in Advanced interrupt mode, the Match or Event causes an interrupt.

Table 45 Wake Control I/O Address 451h

Port 1 Data register is a read/write byte direction

Interrupts

In order to use an interrupt with aDIO, the interrupt must first be selected in the BIOS setup utility under

Advanced, I/O Devices, aDIO Configuration, aDIO Interrupt. The Digital I/O can use interrupts 3, 5, 6, 7, 10, 11, and 12. The interrupt must alsobe reserved so that is it not assigned to PCI devices. To reserve the interrupt, enter the BIOS under PCIPnP and change the interrupt you wish to use to ???Reserved.??? Then, select the appropriate interrupt mode in the DIO Control register. Also, verify that the Int Mask bit is cleared in the Wake Control register

Advanced Digital Interrupts

There are three Advanced Digital Interrupt modes available. These three modes are Event, Match, and Strobe. The use of these three modes is to monitor state changes at the multiPort connector. One way to enable interrupts is to set bit 4 of the DIO-Control register to a 1 and select Event or Match mode. The other way to enable interrupts is explained in Strobe Mode.

Event Mode

When this mode is enabled, Port 0 is latched into the DIO-Compare register at 8.33 MHz. The aDIO circuitry includes deglitching logic. The deglitching requires pulses on Port 0 to be at least 120 ns in width. As long as changes are present longer than that, the event is guaranteed to register. Pulses as small as 60 ns can register as an event, but they must occur between the rising and falling edge of the 8.33 MHz clock. To enter Event mode, set bits [4:3] of the DIO-Control register to ???10???.

Match Mode

When this mode is enabled, Port 0 is latched into the DIO-Compare register at 8.33 MHz. The aDIO circuitry includes deglitching logic. The deglitching requires pulses on Port 0 to be at least 120 ns in width. As long as changes are present longer than that, the match is guaranteed to register. Pulses as small as 60 ns can register as a match, but they must occur between the rising and falling edge of the 8.33 MHz clock. To enter Match mode, set bits [4:3] of the DIO-Control register to ???11???.

Note Make sure bit 3 is set BEFORE writing the DIO-Compare register. If you do not set bit 3 first, the contents of the DIO-Compare register could be lost because the Event mode latches in Port 0 into the DIO-Compare register at an 8.33 MHz rate.

Figure 5 aDIO Match Mode

Strobe Mode

Another interrupt mode supported by aDIO is Strobe mode. This allows the strobe pin of the DIO connector to trigger an interrupt. A low to high transition on the strobe pin will cause an interrupt request. The request will remain high until the Clear Register is read from. Additionally, the Compare Register latched in the value at Port 0 when the Strobe pin made a low to high transition. No further strobes will be available until a read of the Compare Register is made. You must read the Compare Register, and then clear interrupts so that the latched value in the compare register is not lost. To enter Strobe mode, set bits [4:3] of the DIO-Control register to ???01???.

Wake-on-aDIO

The aDIO Strobe, Match and Event interrupt can be used to generate a wake event. This event can wake the CPU from any power-down mode, including Soft-Off (S5). Wake from aDIO will work as long at +5V Standby power is applied to the board. To use the aDIO to wake the system, Wake from aDIO must first be enabled in the BIOS setup utility. Then the aDIO is configured in the appropriate interrupt mode. The ???Wake Enable??? bit is then set in the Wake Control Register at 0x454. The CPU can then be placed in a standby mode, and the aDIO interrupt will wake the system.

During system standby, a 32kHz clock is used for the aDIO instead of an 8.33 MHz clock. Therefore, transitions must be at least 30 us in order to trigger a wake event.

If the aDIO is to be used for a wake event only, and not an interrupt, the ???Int Mask??? bit can be set in the Wake Control Register. This will block the interrupt, but still allow a wake event to occur. The various settings for ???Wake Enable??? and ???Int Mask??? are shown in Table 46 below.

Table 46 Interrupt and Wake Event Generation

00 No Interrupt or Wake event is generated

multiPort: Parallel Port Control

The parallel port may be operated in SPP (output-only), EPP (bidirectional), and ECP (extended capabilities) modes. The mode may be selected in the BIOS, or by application software.

To configure the parallel port in the BIOS, enter the BIOS, and follow the steps below:

1.Under the ???Advanced??? menu in the BIOS, select the ???I/O Device Configuration??? submenu

2.Set the multiPort mode to ???Parallel Port???

3.When a new ???Parallel Port Configuration??? appears, select it and configure the parallel port base address, parallel port mode, and IRQ

multiPort: Floppy Drive

The multiPort connector can be configured as a floppy drive. To utilize the floppy controller, the multiPort mode must be first be set to Floppy Drive in the BIOS. The complete process for setting up the multiPort as a floppy drive is described below.

1.With the system powered off, attach a floppy drive with an adapter board to CN6.

2.Power on the system and enter the BIOS setup screen by pressing the delete key as the system boots.

3.Set Drive B to 1.44 MB in the Standard CMOS Settings section of BIOS Setup.

4.Set the multiPort to Floppy in the BIOS Setup.

5.If booting to the floppy drive is required, set the first boot device in the boot sequence to floppy drive

When the floppy drive is enabled, a special cable and adapter board is required. For more information about this cable kit, refer to the Cable Kits and Accessories section in page 5.

AC???97 Audio

To use the CPU???s onboard audio, it must first be enabled in the BIOS. Two signaling levels are supported, so a line out connection can be used for powered speakers, as well as a headphone connection for non-powered speakers.

Once enabled, two audio outputmodes can be selected:

???Line Out: This signaling level should be used for powered speakers.

???Headphone: This signaling level should be used for non-powered speakers.

Ethernet (10/100Base-T and -TX)

To use the onboard 10/100 Ethernet controller, Ethernet must first be enabled in the BIOS.

When enabled, the multi-color LED will blink to indicate an Ethernet connection. For more information, refer to the Multi-Color LED section on page 69.

IDE Controller Configuration

The CPU???s onboard EIDE connector (CN10) supports several different drive speed modes, which are BIOS configurable. Supported drive modes will depend on whether a 40-conductor or 80-conductor cable is connecting the EIDE device. The modes and cable detection schemes described below may be set in the BIOS Setup. Similarly, the ATA/IDE Disk Chip socket (U16) is BIOS configurable.

Cable Modes

There are two types of cables that may be used for connecting drives to the EIDE connector: 40 conductor cables or 80 conductor cables. Depending on the cable used, different drive speeds are supported. A 40 conductor cable can be used for speeds up to UDMA Mode 2 (Ultra ATA/33).

In order to use drive speeds faster than UDMA Mode 2 (Ultra ATA/33), an 80 conductor cable is required. The BIOS can be configured to detect the presence of an 80 conductor cable. The 80 conductor cable adds a ground wire between each signal, and uses standard 40 pin connectors, therefore an adapter board is required to connect an 80 conductor cable to CN10.

Cable Detection

Every time the cpuModule is powered on or a hardware reset is issued, the BIOS will automatically detect the presense of a 80 conductor cable connecting a device to CN10. The user selectable cable detection modes are described below.

Device and Host Mode

This method involves a capacitor on the PDIAG signal, which has a pull-up connection to a logic 1 voltage. To determine if the connected cable is 40 conductor or 80 conductor, the CPU first sends a command to the attached device. When the device receives the command, it asserts the PDIAG signal low, forcing the capacitor to discharge. The device then deasserts the PDIAG signal, and monitors the charging of the pulled-up capacitor.

If a 40-conductor cable is connected, the signal will still be low when sampled by the device. If an 80-conductor cable is connected, the capacitor will charge before the device samples PDIAG, and thus read a logic 1. Once the cable is determined, the device reports the type of cable to the CPU.

Host Determination of Cable Type

For this method of detection, the CPU reads the CPBLID pin, which determines if a 40-conductor or 80- conductor cable is connected between the CPU and device. The CPBLID signal is pulled low on the CPU end of the connection by default, indicating that a 40-conductor cable is used if the signal is not driven.

If an 80-conductor cable is connected, the device is able to drive CPBLID high, and the CPU can determine that an 80-conductor cable is connected. When a 40-conductor cable is used, this pin is not connected, and the CPU cannot read the the signal driven by the device.

Device Detect

For device detect mode, the CPU issues a command to the device, which tells the CPU the fastest drive speed mode it can use. The CPU then sets the transfer mode to the fastest speed supported by the device.

WARNING When this cable detection method is enabled, the highest transfer speed supported by the device will be used regardless of whether a 40-conductor or 80-conductor cable is used. If the device speed does not match the cable, data corruption and unexpected behaviors may occur. This mode should not be selected unless the user knows the cable type and the modes supported by the connected EIDE device.

Legacy Mode and Native Mode IDE

The onboard EIDE controller may be configured as a either a Legacy or Native Mode IDE controller in the BIOS Setup. However, the operating system must support the selected mode for the device to operate correctly. The default configuration for the controller is Legacy Mode, as this is supported by most operating systems.

Legacy Mode

Legacy mode is the default configuration of the onboard EIDE controller. When in this mode, the controller will be fixed to use two interrupts: IRQs 14 and 15. Similarly, the I/O address of the controller will be fixed in the system. When in Legacy Mode, only a primary and secondary channel m ay be used in the system.

Native Mode

Native Mode allows more flexibility, as the system resources used by the IDE controller may be modified. When in Native Mode, the IDE controller only requires a single IRQ. Unlike Legacy Mode, this IRQ may be changed by the user or the operating system for better distriution of the system IRQs. When IRQs in the system are more evenly distributed, interrupt latency is minimized. The base address of the controller may also be modified.

Configuring the ATA/IDE Disk Chip Socket

The cpuModule was designed to be used in embedded computing applications. In such environments, magnetic media like hard disks and floppy disks are not very desirable. It is possible to eliminate magnetic storage devices by placing your operating system and application software into the cpuModule's ATA/IDE Disk Chip socket.

Before installing a device in the ATA/IDE Disk Chip socket, it is highly recommend to first configure the secondary IDE controller and device mode in the BIOS setup.

The secondary IDE controller must be enabled in the BIOS to allow read and write access to the device. When a device is installed in the socket, it will always appear as a master on the cpuModule???s secondary IDE controller.

From the BIOS setup screen, the user can also configure whether the socket contains a DMA mode or PIO mode device.

???DMA Mode: DMA mode will reduce CPU overhead. This mode can be set use multi-word DMA.

???PIO Mode: When the socket is in PIO mode, PIO transfers are supported. PIO Mode supports write protection.

Real Time Clock Control

The cpuModule is equipped with a real time clock (RTC) which provides system date and time functions, and also provides 128 nonvolatile memory locations. The contents of these memory locations are retained whenever an external backup battery is connected, whether or not system power is connected.

You may access the RTC date, time, and memory using an index and data register at I/O addresses 70h and 71h. Address 70h is the Index register. It must be written with the number of the register to read or write. Refer to the map below for valid choices for the index. Data is then written to or read from the selected register by writing or reading (respectively) the data register at address 71h.

WARNING Do NOT change values stored in the RTC registers listed as RESERVED in the table below. Doing so will interfere with proper cpuModule operation.

Registers of the RTC are shown below.

Table 47 Real Time Clock Registers

Watchdog Timer Control

The cpuModule includes a watchdog timer, which provides protection against programs "hanging", or getting stuck in an execution loop where they cannot respond correctly. When enabled, the watchdog timer must be periodically reset by your application program. If it is not refreshed before the time-out period expires, it will cause a hardware reset of the cpuModule.

The watchdog time-out period is typically 1.1 seconds, but can vary between 550 ms and 1.65 seconds. Because of operating system latency, it is recommended that the watchdog be refreshed at half of the period, or every 275 ms.

Before using the Watchdog timer, it must be enabled in the BIOS setup utility. When it is disabled in the BIOS, the watchdog register does not appear in I/O space and it will not generate an a reset.

Note Enabling the watchdog timer in the BIOS does not actually arm it. The watchdog timer can be armed by accessing I/O address 455h, a explained below.

Three functions have been implemented on the cpuModule for controlling watchdog timer control. These are:

???Arm: The watchdog timer can be enabled by writing a 1 to bit 7 of I/O port 0x455. To ensure compatability with future designs, you should read the register and only change the bit you need to change.

???Disarm: The watchdog timer is disabled by writing a 0 to bit 7 of I/O port 0x455. To ensure compatability with future designs, you should read the register and only change the bit you need to change.

???Refresh: The watchdog timer is refreshed by reading from I/O port 0x455. After you enable the watchdog timer, you must refresh it at least once every 550 ms.

Table 48 Wake Control I/O Address 455h

1=Watchdog timer is disabled and will not generate an interrupt

0=Watchdog Timer is enabled and needs to be refreshed

Thermal Management

The cpuModule has several thermal features which can be used to monitor and control the board???s temperature when extreme operating conditions are prevalent.

Thermal Monitor and Thermal Throttling

In addition to the Thermal Monitor, conventional Thermal Throttling is also provided. This forces the CPU to skip clock cycles when it exceeds a thermal limit. The thermal limit and duty cycle of thermal throttling can be modified in the BIOS, where both the PCB and CPU temperature can be set to activate thermal throttling. The CPU and PCB temperature are displayed in the Thermal section of the BIOS setup..

Note The CPU and PCB temperatures displayed in the BIOS are approximate and should not be used to validate a cooling solution.

Fan Mode

The CPU fan can be controlled by the CPU when connected to the switched fan power connector (CN15). Two fan modes are supported, which can be toggled in the BIOS setup.

???Always On: When in this mode, the fan is always powered by the CPU.

???Auto: This mode allows the system to keep the fan turned off until the CPU is hot. When the fan mode is set to auto, the CPU???s power consumption is reduced.

Note If the CPU fan is connected to the continuous +5 V fan connector (CN14), changing the fan mode options in the BIOS will not affect the fan, as it will always be turned on.

Further Temperature Reduction

The cpuModule???s temperature is directly related to power consumption. Reducing the power consumption of the CPU will have an effect on the CPU???s temperature. Suggested methods for reducing the CPU???s power consumption can be found in the Power Management section on page 66.

Power Management

The CMX58886CX cpuModule supports various powering mechanisms which allow the cpuModule to monitor power consumption and temperature, and achieve minial power consumption states. These unique features include thermal monitoring and thermal throttling, as well as low power modes including APM and ACPI configurations. Various wake options are also available to resume normal system power when power modes are no longer necessary for the application.

Advanced Power Management (APM)

Legacy Advanced Power Management (APM 1.2) options such as setting suspend and standby timeout intervals, can be configured in the BIOS on the cpuModule.

Advanced Configuration and Power Interface (ACPI)

The cpuModule supports several different ACPI low power modes, including the S1, S3, S4, and S5 sleeping states. Suspend modes S1 and S3 can be enabled in the BIOS, where the soft power button on the utility port (CN5) can be setup as a suspend button (see Power Button Modes). Sleep modes S4 and S5 are typically setup by the operating system.

The cpuModule???s ACPI suspend modes are described below

???S1 (Power on Suspend): The S1 low power state consumes the most power of all supported ACPI sleep modes. In this mode, the CPU stops executing instructions, but power to the CPU and RAM is maintained.

???S3 (Suspend to RAM): Everything in the system is powered off except for the system memory. When the system wakes from this mode, operating systems typically allow applications to resume where they left off, as the state of the application is preserved in memory.

???S4 (Hibernate): When the system enters this state, the operating system will typically save the current state of applications and relevent data to disk, thus allowing the system RAM to be powered down.

???S5 (Soft-Off): The system is in a soft off state, and must be rebooted when it wakes.

Power Button Modes

The soft power button input of the utility port connector (CN5) can be configured as a suspend button to send a soft power signal to the system. The power buttons function can be changed to a suspend button in the BIOS. When configured in suspend mode, if S1 or S3 are enabled, pressing the power button will force the system into the specified sleep state.

Low-Power Wake Options

The cpuModule supports several methods of waking from a low power state. Several of these wake options are BIOS configurable, and can be accessed directly from the ???Power??? menu in the BIOS setup:

???Resume on Ring: While in a low power mode, the ring indicator input of either COM port may be used to wake the system.

???Resume on aDIO: This option allows the system to use an aDIO Strobe, Match, or Event interrupt to generate a wake event. This event can wake the CPU from any power-down mode, including Soft-Off (S5). For more information, refer to the section titled Wake-on-aDIO on page 59.

???Resume on PME#: When enabled, the system can wake when a signal is applied to the External Power Managment connector (CN12). This includes wake-up on onboard LAN controller. The PME# signal is also available on the PC/104-Plus (PCI) bus connector.

???Resume on RTC Alarm: The RTC Alarm allows the system to turn on at a certain time every day. This option is BIOS configurable.

AT vs. ATX Power Supplies

Both AT and ATX power supplies may be used with the CMX58886CX cpuModule, however AT power supplies do not provide any standby power to the cpuModule. When an AT power supply is used to power the system, low power modes that require a standby power to wake the system will not be fully supported.

ATX power supplies do provide a standby power, thus allowing the system to utilize all low power modes supported by the hardware. When an ATX supply is used to power the cpuModule, lower power modes can be acheived. During these low power modes, the standby power from the ATX power supply provides power to a small circuit on the CPU, which is used to watch for a system wake event.

ATX Power Supply Signals

The auxiliary power connector (CN3) provides two ATX style signals., +5V Standby and PSON#. The +5V Standby rail is used to power certain parts of the cpuModule when the main power supply is turned off, i.e. during Suspend-to-RAM (S3), Hibernate (S4), or Soft-Off (S5) power modes. The PSON# signal is an active low open-drain ouput that signals the power supply to turn on. Use of these signals allows the power consumption to drop to below 1W during standby modes, and still enable any of the wake events.

The CPU monitors power supply inputs, and also generates the ATX Power Good signal.

Reducing Power Consumption

In addition to the CPU???s low power modes, power consumption can further be reduced by making some modifications to the BIOS setup. When the following features are modified, the CPU???s power consumption will descrease:

???Memory Speed: Changing the DDR DRAM clock frequency will reduce power consumption, however memory performance will also be reduced.

???Ethernet: Can be disabled in the BIOS

???Serial Ports: Can be disabled in the BIOS

???LVDS Flat Panel: If an LVDS panel is not connected to the cpuModule while using a VGA monitor, setting the BIOS to use only a CRT (VGA) monitor will reduce power consumption.

???Fan Mode: Set the fan to auto mode so it is used only when the processor reaches high temperatures. This option will only effect the fan if it is connected to the switched fan power connector (CN15).

???Multi-Color LED: Can be disabled in the BIOS

Multi-Color LED

The CMX58886CX has a Multi-Color LED located beside the EIDE connector (CN10) which can be enabled or disabled in the BIOS setup screen. The color of the LED indicates the status of the board, as shown in Table 49.

1.If power is applied to the cpuModule while jumper JP5 is installed, the LED will be red. This does not indicate that the board is in reset

The LED can also be controlled manually by writing to I/O Port 456h, as shown in Table 50 and Table 51.

Table 50 Multi-Color LED I/O Address 456h

Note When writing to I/O Port 456h, only the lower three bits of the register should be modified.

Modifying the upper bits will effect the User EEPROM

The following table lists the color displayed and the value written.

1. Disabling the LED will reduce system power consumption.

Reset Status Register

The cpuModule has several different signals on board which can cause a system reset. If a reset occurs, the reset status register can be used to see which reset or resets have been asserted on the cpuModule.

The user has the ability to see which resets have been asserted. Resets can also be cleared.

???Examine Resets: Reading from I/O port 0x457 will indicate if a reset has been asserted. If a 1 is read, the corresponding reset has been assserted. If a 0 is read from the bit, the reset has not been asserted

???Clear Reset: Each reset can be cleared by writing a 1 to the selected bit of I/O port 0x457.

Table 52 Reset Status I/O Address 457h - Read Access

Table 53 Reset Status I/O Address 457h - Write Access

Features and Settings That Can Affect Boot Time

The boot time of a system is dependent upon numerous system settings as well as devices attached to a system.. This section addresses some devices and settings that can increase or decrease a system???s boot time.

Quick Boot

The BIOS contains a Quick Boot option that minimizes the boot time of the system. Quick Boot eliminates the exhaustive tests that are performed during Power On Self Test (POST) while maintaining the functionality of the board (see note 1 below). By enabling the Quick Boot feature, your system can achieve 5-second boot times.

Add-On Cards With BIOS Extensions

Some add-on cards have an integrated BIOS extension. The most common examples are SCSI controllers and network cards with boot ROMs. During POST, the BIOS executes the card's extension code. This extension code is third-party code, which is beyond RTD's control. The BIOS extension will most likely increase the boot time. Exactly how much it increases boot time will depend on the particular card and firmware version.

VGA Controller

VGA controllers have a VGA BIOS that must be initialized during POST. It can take some time to initialize the VGA BIOS. Exactly how long will depend on the particular VGA controller and BIOS version.

Hard Drive Type

During IDE initialization, each IDE device must be probed. Some devices take longer to probe. 2.5-inch hard drives tend to take longer than 3.5-inch ones, because they spin at a lower RPM.

Monitor Type

Some monitors take a while to power on. Desktop flat panels are especially slow. This does not affect the actual boot time of the CPU. However, the CPU may boot before the monitor powers on.

NVRAM Updates

System configuration data is stored in the onboard NVRAM. When the system configuration changes, this information must be updated. If an update is necessary, it will happen at the end of POST (the BIOS will display an "Updating NVRAM???" message). The NVRAM update takes a few seconds and increases the boot time. Once the NVRAM is updated, boot times will return to normal.

NVRAM updates only happen when the system configuration changes. They do not happen spuriously. They are usually triggered by adding or removing a PCI device from a stack. Updates can also be triggered by altering the Plug-n-Play configuration of the BIOS.

Boot Device Order

The BIOS contains a list of devices to try booting from. If you wish to boot to a particular device (for example, a hard drive), make sure that it is first in the boot order. This will speed up boot times.

System Recovery

Loading Default BIOS Settings

The default BIOS can be restored either by using the ???Load Defaults??? option in the BIOS, or by installing jumper JP5 (see Figure 6 on page 81). In most cases, the easiest way to load default settings is by setting them in the BIOS. For other unique cases, jumper JP5 provides an alternative method of restoring the BIOS settings.

To restore the default BIOS settings with jumper JP5, follow the procedure below.

1.Remove power from the system.

2.Install JP5.

3.Apply power to the system. The cpuModule will then load its default settings. Note that the multi-color LED will be red if power is applied while JP5 is installed.

4.Reboot and press Delete to enter BIOS Setup.

5.Save the BIOS settings and exit, allowing the system to boot to the FSBR.

6.The next time the system is powered, the BIOS Setup will be configured to use the default settings.

Booting to the Fail Safe Boot ROM (FSBR)

If your system is in configuration that will not allow it to boot, the Fail Safe Boot ROM is a minimal build of ROM-DOS which can be booted to for system debugging. To boot to the FSBR, follow the instructions below.

1.Remove power from the system.

2.Install JP5. This will force the cpuModule to boot using the default BIOS configuration.

3.Apply power to the system. The cpuModule will then boot to the Fail Safe Boot ROM image. Note that the multi-color LED will be red if power is applied while JP5 is installed.

4.Press the {Del.} key to enter Setup, or allow the cpuModule to boot to Failsafe

Basic Interrupt Information for Programmers

An interrupt is a subroutine called asynchronously by external hardware (usually an I/O device) during the execution of another application. The CPU halts execution of its current process by saving the system state and next instruction, and then jumps to the interrupt service routine, executes it, loads the saved system state and saved next instruction, and continues execution. Interrupts are good for handling infrequent events such as keyboard activity. Interrupts on this cpuModule are controlled by two Intel 8259-equivalent interrupt controllers containing 13 available interrupt request lines.

What happens when an interrupt occurs?

An IRQx pin on the PC/104 bus makes a low to high transition while the corresponding interrupt mask bit is unmasked and the PIC determines that the IRQ has priority, that is, the PIC interrupts the processor. The current code segment (CS), instruction pointer (IP), and flags are pushed onto the stack. The CPU then reads the 8-bit vector number from the PIC, and a new CS and IP are loaded from a vector???indicated by the vector number??? from the interrupt vector table that exists in the lowest 1024 bytes of memory. The processor then begins executing instructions located at CS:IP. When the interrupt service routine is completed the CS, IP, and flags that were pushed onto the stack are popped from the stack into their appropriate registers and execution resumes from the point where it was interrupted.

How long does it take to respond to an interrupt?

A DOS system can respond to an interrupt between 6 and 15 ??s. A Windows system can take a much longer time when a service routine has been installed by a device driver implemented as a DLL???from 250 to 1500 ??s or longer. The time the CPU spends in the interrupt depends on the efficiency of the code in the ISR. These numbers are general guidelines and will fluctuate depending on operating system and version. Minimum time between two IRQ requests is 125 ns per ISA specification.

Interrupt Request Lines

To allow different peripheral devices to generate interrupts on the same computer, the ISA bus has eight different interrupt request (IRQ) lines. On the ISA bus, a transition from low to high on one of these lines generates an interrupt request, which is handled by the PC???s interrupt controller. On the PCI bus, an interrupt request is level-triggered.

The interrupt controller checks to see if interrupts are to be acknowledged from that IRQ and, if another interrupt is already in progress, it decides if the new request should supersede the one in progress or if it has to wait until the one in progress is done. This prioritizing allows an interrupt to be interrupted if the second request has a higher priority. The priority level is based on the number of the IRQ; IRQ0 has the highest priority, IRQ1 is second-highest, and so on through IRQ7, which has the lowest. Many of the IRQs are used by the standard system resources. IRQ0 is used by the system timer, IRQ1 is used by the keyboard, IRQ3 by COM2, IRQ4 by COM1, and IRQ6 by the disk drives. Therefore, it is important to know which IRQ lines are available in your system for use by the cpuModule.

Intel 8259 Programmable Interrupt Controller

The chip responsible for handling interrupt requests in the PC is the Intel 8259 Programmable Interrupt Controller. To use interrupts, you need to know how to read and set the Intel 8259???s interrupt mask register (IMR) and how to send the end-of-interrupt (EOI) command to the Intel 8259.

Each bit in the IMR contains the mask status of an IRQ line; bit 0 is for IRQ0, bit 1 is for IRQ1, and so on. If a bit is set (1), then the corresponding IRQ is masked and will not generate an interrupt. If a bit is clear (0), then the corresponding IRQ is unmasked and can generate interrupts. The IMR is programmed through port 21h.

Note When in APIC mode, the PIC is programmed differently, and IRQ routing behaves differently. For more information, refer to the APIC datasheets and specifications provided by Intel.

PCI Interrupts

PCI devices can share interrupts. The BIOS or operating system may assign multiple PCI devices to the same IRQ line. Any interrupt service routine (ISR) written for PCI devices must be able to handle shared interrupts. Refer to Interrupt-Driven PC System Design (ISBN: 0-929392-50-7) for more information on PCI interrupts.

Writing an Interrupt Service Routine (ISR)

The first step in adding interrupts to your software is to write the ISR. This is the routine that will automatically be executed each time an interrupt request occurs on the specified IRQ. An ISR is different than standard routines that you write. First, on entrance, the processor registers should be pushed onto the stack BEFORE you do anything else. Second, just before exiting your ISR, you must clear the interrupt status flag and write an end-of-interrupt command to the Intel 8259 controller. Finally, when exiting the ISR, in addition to popping all the registers you pushed on entrance, you must use the IRET instruction and not a plain RET. The IRET automatically pops the flags, CS, and IP that were pushed when the interrupt was called.

Most C compilers allow you to identify a procedure (function) as an interrupt type and will automatically add these instructions to your ISR, with one important exception: most compilers do not automatically add the end-of-interrupt command to the procedure; you must do this yourself. Other than this and the few exceptions discussed below, you can write your ISR just like any other routine. It can call other functions and procedures in your program and it can access global data. If you are writing your first ISR, RTD recommends focusing on the basics, such as incrementing a global variable.

Most operating systems have restrictions on what instructions can be called in your ISR. Consult your OS documentation for details on writing your ISR.

Note A complete explanation of interrupt programming is beyond the scope of this manual. For more information on interrupts, refer to the Appendix.

Sample Code

RTD???s drivers provide examples of ISR???s and interrupt handling. Refer to them as working examples. These drivers were shipped with your cpuModule, but they they can also be downloaded from RTD???s website (www.rtd.com)..

Jumper Settings and Locations

Many cpuModule options are configured by positioning jumpers. Jumpers are labeled on the board as JP followed by a number.

Some jumpers have three pins, allowing three settings:

??? Pins 1 and 2 connected (indicated as ???1???2???)

??? Pins 2 and 3 connected (indicated as ???2???3???)

??? No pins connected

1 2 3

Some jumpers have two pins, allowing two settings:

??? Pins 1 and 2 connected (indicated as ???closed???)

??? Pins 1 and 2 unconnected (indicated as ???open???)

1 2

Solder jumpers are located on the cpuModule???s bottom side. Solder blobs are factory-set and rarely changed. Contact RTD Technical Support for further information.

Figure 6 shows the jumper and solder blob locations that are used to configure the cpuModule. In both top and bottom figures, the PC/104 bus connector is at the six o'clock position. Table 57 lists the jumpers and their settings. Table 58 lists the solder blobs and their settings.

Table 60 Troubleshooting (cont???d)

cannot enter BIOS

screen flickers at high resolutions when processor is fully utilized

quick boot enabled with no hard drives

memory with ECC enabled requires additional system memory resources; the integrated graphics engine has less memory bandwidth for access to the graphics frame buffer

???install JP5, reboot, and run qboot.exe and reboot.

???disable ECC

Troubleshooting a PC/104-Plus System

If you have reviewed the preceding table and still cannot isolate the problem with your CMX58886CX cpuModule, please try the following troubleshooting steps. Even if the resulting information does not help you find the problem, it will be very helpful if you need to contact technical support.

1.Simplify the system. Remove items one at a time and see if one particular item seems to cause the problem.

2.Swap components. Try replacing items in the system one-at-a-time with similar items.

How to Obtain Technical Support

If after following the above steps, you still cannot resolve a problem with your CMX58886CX cpuModule, please gather the following information:

???cpuModule model, BIOS version, and serial number

???List of all boards in system

???List of settings from cpuModule Setup program

???Printout of autoexec.bat and config.sys files (if applicable)

???Description of problem

???Circumstances under which problem occurs

Then contact RTD Technical Support:

Phone: 814-234-8087

Fax: 814-234-5218

E-mail: techsupport@rtd.com

Appendix C IDAN??? Dimensions and Pinout

cpuModules, like all other RTD PC/PCI-104 modules, can be packaged in Intelligent Data Acquisition Node (IDAN) frames, which are milled aluminum frames with integrated heat sinks and heat pipes for fanless operation. RTD modules installed in IDAN frames are called building blocks. IDAN building blocks maintain the simple but rugged PC/104 stacking concept. Each RTD module is mounted in its own IDAN frame and all I/O connections are brought to the walls of each frame using standard PC connectors. No connections are made from module to module internal to the system other than through the PC/104 and PC/104-Plus bus, enabling quick interchangeability and system expansion without hours of rewiring and board redesign.

The CMX58886CX cpuModule can also be purchased as part of a custom-built RTD HiDAN??? or HiDANplus??? High Reliability Intelligent Data Acquisition Node. This appendix provides the dimensions and pinouts of the CMX58886CX installed in an IDAN frame. Contact RTD for more information on high reliability IDAN, HiDAN, and HiDANplus PC/PCI-104 systems.

IDAN???Adhering to the PC/104 stacking concept, IDAN allows you to build a customized system with any combination of RTD modules.

IDAN Heat Pipes???Advanced heat pipe technology maximizes heat transfer to heat sink fins.

HiDANplus???Integrating the modularity of IDAN with the ruggedization of HiDAN, HiDANplus enables connectors on all system frames, with signals running between frames through a dedicated stack-through raceway.

IDAN Dimensions and Connectors

6-pin mini-DIN (female)

25-pin D (female)

module P/N: Adam Tech DB25SD

mating P/N: Adam Tech DB25PD

20-pin mini D (female)

module P/N: 3M 10220-6212VC

mating P/N: 3M 10120-3000VE

FRONT

9-pin D (female)

module P/N: Adam Tech DE09SD

mating P/N: Adam Tech DE09PD

15-pin high-density D (female)

module P/N: Adam Tech HDT15SD

mating P/N: Adam Tech HDT15PD

REAR

9-pin D (male)

module P/N: Adam Tech DE09PD

mating P/N: Adam Tech DE09SD

Figure 8 IDAN-CMX58886CX Connectors

Appendix D Additional Information

Application Notes

RTD offers many application notes that provide assistance with the unique feature set of the CMX58886CX cpuModule. For the lastest application notes, refer to the RTD website.

Drivers and Example Programs

To obtain the latest versions of drivers and example programs for this cpuModule, refer to the RTD website.

Interrupt Programming

For more information about interrupts and writing interrupt service routines, refer to the following book:

Interrupt-Driven PC System Design by Joseph McGivern

ISBN: 0929392507

Serial Port Programming

For more information about programming serial port UARTs, consult the following book:

Serial Communications Developer's Guide by Mark Nielson

ISBN: 0764545701

PC/104 and PC/104-Plus Specifications

A copy of the latest PC/104 and PC/104-Plus specifications can be found on the webpage for the PC/104 Embedded Consortium:

http://www.pc104.org

Appendix E Limited Warranty

RTD Embedded Technologies, Inc. warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from RTD Embedded Technologies, Inc. This warranty is limited to the original purchaser of product and is not transferable.

During the one year warranty period, RTD Embedded Technologies will repair or replace, at its option, any defective products or parts at no additional charge, provided that the product is returned, shipping prepaid, to RTD Embedded Technologies. All replaced parts and products become the property of RTD Embedded Technologies. Before returning any product for repair, customers are required to contact the factory for a Return Material Authorization number.

This limited warranty does not extend to any products which have been damaged as a result of accident, misuse, abuse (such as: use of incorrect input voltages, improper or insufficient ventilation, failure to follow the operating instructions that are provided by RTD Embedded Technologies, "acts of god" or other contingencies beyond the control of RTD Embedded Technologies), or as a result of service or modification by anyone other than RTD Embedded Technologies. Except as expressly set forth above, no other warranties are expressed or implied, including, but not limited to, any implied warranties of merchantability and fitness for a particular purpose, and RTD Embedded Technologies expressly disclaims all warranties not stated herein. All implied warranties, including implied warranties for merchantability and fitness for a particular purpose, are limited to the duration of this warranty. In the event the product is not free from defects as warranted above, the purchaser's sole remedy shall be repair or replacement as provided above. Under no circumstances will RTD Embedded Technologies be liable to the purchaser or any user for any damages, including any incidental or consequential damages, expenses, lost profits, lost savings, or other damages arising out of the use or inability to use the product.

Some states do not allow the exclusion or limitation of incidental or consequential damages for consumer products, and some states do not allow limitations on how long an implied warranty lasts, so the above limitations or exclusions may not apply to you.

This warranty gives you specific legal rights, and you may also have other rights which vary from state to state.

RTD Embedded Technologies, Inc. 103 Innovation Blvd.

State College PA 16803-0906

USA

Website: www.rtd.com