Contents

APPENDIX

(This specification is subject to change without further notice)

Contents

Specification Revision History

EM78P221/2N

8-Bit Microcontroller with OTP ROM

Read Me First !

Comparison between V-Package and U-Package version

This series of microcontrollers comprise of the older V-package version and the newer U-package version. In the newer U-package version, a Code Option NRM is added and various features such as Crystal mode Operating frequency range, IRC mode wake-up time, WDT Time-out time, Comparator function and Pins function have been modified to favorably meet users??? requirements. The following table is provided for quick comparison between the two package version and for user convenience in the choice of the most suitable product for their application.

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

1 General Description

EM78P221N and EM78P222N are 8-bit microprocessors designed and developed with low-power and high-speed CMOS technology. Each device in the series has as an on-chip 4K???13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). Each provides a protection bit to prevent intrusion of user???s OTP memory code. Two Code option bits are also available to meet user???s requirements.

With its enhanced OTP-ROM features, each device provides a convenient way of developing and verifying user???s programs. Moreover, this OTP devices offer the advantages of easy and effective program updates, using development and programming tools. User can avail of the ELAN Writer to easily program his development code.

(This specification is subject to change without further notice)

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

4Pin Description

4.1EM78P222N

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

4.2 EM78P221N

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

5 Block Diagram

Fig. 5-1 EM78P221/2N Functional Block Diagram

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6Function Description

6.1Register Configuration

Note: 1. All registers are 8 bits.

2.When using ICE, some registers code options are set. Refer to Section 6.2 for detailed Registers Description.

3.Registers with * can only be used in ICE220N simulator.

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.2 Registers Description

6.2.1 A (Accumulator)

Internal data transfer operation, or instruction operand holding usually involves the temporary storage function of the Accumulator. The Accumulator is not an addressable register.

Bit 7 (INTE): INT signal edge

0 = interrupt occurs at the rising edge on the INT0 and INT1 pin 1 = interrupt occurs at the falling edge on the INT0 and INT1 pin

Bit 6 (INT): Interrupt enable flag

0 = masked by DISI or hardware interrupt

1 = enabled by the ENI/RETI instructions This bit is readable only.

Bit 5 (TS): TCC signal source

0 = internal instruction cycle clock. If P56 is used as I/O pin, TS must be 0. 1 = transition on the TCC pin

Bit 4 (TE): TCC signal edge

0 = increment if the transition from low to high takes place on the TCC pin 1 = increment if the transition from high to low takes place on the TCC pin.

Bit 3 (PSTE): Prescaler enable bit for TCC

0 = prescaler disable bit. TCC rate is 1:1

1 = prescaler enable bit. TCC rate is set as Bit 2 ~ Bit 0.

Bit 2 ~ Bit 0 (PST2 ~ PST0): TCC prescaler bits

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.2.3 R0 (Indirect Addressing Register)

R0 is not a physically implemented register. Its major function is to perform as an indirect address pointer. Any instruction using R0 as a pointer, actually accesses the data pointed by the RAM Select Register (R4).

6.2.4 R1 (Memory Switch Register)

Bits 7~2: not used bits, fixed to 0 all the time.

Bits 1~0: used to select Banks 0 ~ 3 for R20~R3F and select Banks 0 ~ 3 for the control register.

See the table under Section 6.2 Registers Description for the data memory configuration.

6.2.5 R2 (Program Counter and Stack)

Fig. 6-1 Program Counter Organization

R2 and hardware stacks are 12-bit wide. The structure is depicted in the table under Section 6.1Register Configuration.

Generates 4K???13 bits on-chip ROM addresses to the relative programming instruction codes. One program page is 1024 words long.

The contents of R2 are all set to "0"s when a reset condition occurs.

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

"JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to jump to any location within a Page (1K).

"CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page (1K).

"LJMP" instruction allows direct loading of the lower 11 program counter bits. Therefore, "LJMP" allows PC to jump to any location within 2K (212).

"LCALL" instruction loads the lower 11 bits of the PC, and then PC+1 are pushed onto the stack. Thus, the subroutine entry address can be located anywhere within 2K (212).

"RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top of stack.

"ADD R2, A" allows a relative address to be added to the current PC, and the ninth and above bits of the PC will increase progressively.

"MOV R2, A" allows loading of an address from the "A" register to the lower 8 bits of the PC, and the ninth and above bits of the PC will remain unchanged.

Any instruction (except ???ADD R2,A???) that is written to R2 (e.g., "MOV R2, A", "BC R2, 6" etc.) will cause the ninth bit and above bits of the PC to remain unchanged.

All instructions are single instruction cycle (fclk/2) except ???LCALL??? and ???LJMP??? instructions. The ???LCALL??? and ???LJMP??? instructions need two instructions cycle.

6.2.6 R3 (Status Register)

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.2.7 R4 (Select Indirect Address)

Bits 7~6: not used, fixed to 0 all the time.

Bit 5 ~ Bit 0: used to select registers (Address: 00 ~ 3F) in indirect addressing mode.

6.2.8 Bank 0-R5 (Port 5)

Bits 7 ~ 0 (P57 ~ P50): I/O data bits

6.2.9Bank 0-R6 (Port 6)

Bits 7 ~ 0 (P67 ~ P60): I/O data bits

6.2.10 Bank 0-R7 (Port 7)

Bits 7 ~ 0 (P77 ~ P70): I/O data bits

[With Simulator]: P73 ~ P72 are input or open-drain output pins.

[With EM78P221/2N]: P73 ~ P72 are general input or output pins.

6.2.11 Bank 0-R8 (Port 8)

Bits 7~6, 4~2, 0: not used, fixed to 0 all the time.

Bit 5 (NREN): Noise rejection enable

0 = disable noise rejection (Default)

1 = enable noise rejection. However in crystal oscillator mode (LXT2), the noise rejection circuit is always disabled.

Bits 1 ~0 (P81~P80): I/O data bit.

6.2.12 Bank 0-R9~RD (Reserve)

Bits 7~0: not used, fixed to "0" all the time.

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.2.13 Bank 0-RE (WUCR: Wake-up Control Register)

Bit 7 (EX1IF): External interrupt flag. Set by INT1 pin, reset by software. 0 = no interrupt occurs

1 = with interrupt request

Bits 6~5, 3, 1: not used bits, fixed to 0 all the time

Bit 4 (ICWE): Port 6 input change to wake-up status enable bit 0 = Disable Port 6 input change to wake-up status 1 = Enable Port 6 input change wake-up status

When the Port 6 Input Status Change is used to enter interrupt vector or to wake-up EM78P221N//2N from sleep, the ICWE bit must be set to ???Enable???.

Bit 2 (CMPWE): Comparator wake-up enable bit

0= Disable Comparator wake-up

1= Enable Comparator wake-up

When the Comparator output status change is used to enter interrupt vector or to wake-up from sleep, the CMPWE bit must be set to ???Enable???.

Bit 0 (CMPIF): Comparator interrupt flag. Set when a change occurs in the output of Comparator. Reset by software.

0 = no interrupt occurs

1 = with interrupt request

NOTE

???Bank 0-RE <7, 0> can be cleared by instruction but cannot be set.

???Bank1-RE <0> is an interrupt mask register.

???Interrupt results from "logic AND" of Bank 0-RE <7, 0> and Bank 1-RE <0>, with instruction ???ENI???.

6.2.14 Bank 0-RF (Interrupt Status Register)

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

Bit 1 (ICIF): Port 6 input status change interrupt flag. Set when Port 6 input changes. Reset by software.

0 = no interrupt occurs

1 = with interrupt request

Bit 0 (TCIF): TCC overflow interrupt flag. Set when TCC overflows. Reset by software. 0 = no interrupt occurs

1 = with interrupt request

NOTE

???Bank 0-RF <2, 1, 0> can be cleared by instruction but cannot be set.

???Bank1-RF <2, 1, 0> is an interrupt mask register.

???Interrupt results from "logic AND" of Bank 0-RF <2, 1, 0> and Bank 1-RF <2, 1, 0> with instruction ???ENI???.

6.2.15 Bank 1-R5 ~R7 (I/O Port Control Register)

Bits 7~0: 0 = defines the relative I/O pin as output

1 = puts the relative I/O pin into high impedance Bank 1-R5, R6 and R7 registers are all readable and writable.

6.2.16 Bank 1-R8 (I/O Port Control Register)

Bits 7~2: not used, fixed to 0 all the time

Bits 1~0 (C81~C80): 0 = defines the relative I/O pin as output

1 = puts the relative I/O pin into high impedance

With Simulator]: P80 and P81 are General I/O pins

[With EM78P221/2N]: P80 is General input or output, but P81 is input or open-drain output pin.

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.2.17 Bank 1-R9 (Reserve)

Bits 7~0: not used, fixed to 0 all the time

6.2.18 Bank 1-RA (CMPCON: Comparator Control Register)

Bit 7 (EIS1): Control bit used to define the function of the P71 (/INT1) pin

0 = P71, normal I/O pin

1 = /INT1, external interrupt pin. In this case, the I/O control bit of P71 (Bit 1 of Bank 1-R7) must be set to "1"

Bit 6 (EIS0): Control bit used to define the function of the P77 (/INT0) pin

0 = P77, normal I/O pin

1 = /INT0, external interrupt pin. In this case, the I/O control bit of P77 (Bit 7 of Bank 1-R7) must be set to "1"

NOTE

??When EIS is "0," the path of /INT is masked. When EIS is "1," the status of /INT pin can also be read by way of reading Port 7 (Bank 0-R7). Refer to Fig. 6-4 (I/O Port and I/O Control Register Circuit for P77 (/INT0) and P71 (/INT1) under Section 6.4 (I/O Ports).

??EIS0 and EIS1 are both readable and writable.

??The highest priority of P71/INT1/CO2 is INT1. When EIS1=0, the working type of P71/INT1/CO is determined by CMPCOS1 and CMPCOS0.

Bit 5 (CMPOUT): The result of the comparator output

Bit 4 ~ Bit 3 (CMPCOS1 ~ CMPCOS0): Comparator Select bits

Bits 2~0: not used, fixed to 0 all the time

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.2.19 Bank 1-RB (Pull-down Control Register)

Bank 1-RB register is both readable and writable

Bit 7 (/PD7): Control bit used to enable the pull-down function of the P67 pin

0= Enable internal pull-down function

1= Disable internal pull-down function

Bit 6 (/PD6): Control bit used to enable the pull-down function of the P66 pin.

Bit 5 (/PD5): Control bit used to enable the pull-down function of the P65 pin.

Bit 4 (/PD4): Control bit used to enable the pull-down function of the P64 pin.

Bit 3 (/PD3): Control bit used to enable the pull-down function of the P63 pin.

Bit 2 (/PD2): Control bit used to enable the pull-down function of the P62 pin.

Bit 1 (/PD1): Control bit used to enable the pull-down function of the P61 pin.

Bit 0 (/PD0): Control bit used to enable the pull-down function of the P60 pin.

6.2.20 Bank 1-RC (Open-Drain Control Register)

Bank 1-RC register is both readable and writable.

Bit 7 (OD7):

Bit 6 (OD6):

Bit 5 (OD5):

Bit 4 (OD4):

Bit 3 (OD3):

Bit 2 (OD2):

Bit 1 (OD1):

Bit 0 (OD0):

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.2.21 Bank 1-RD (Pull-high Control Register)

Bank 1-RD register is both readable and writable.

Bit 7 (/PH7): Control bit used to enable the pull-high function of the P67 pin.

0= Enable internal pull-high

1= Disable internal pull-high

Bit 6 (/PH6): Control bit used to enable the pull-high function of the P66 pin.

Bit 5 (/PH5): Control bit used to enable the pull-high function of the P65 pin.

Bit 4 (/PH4): Control bit used to enable the pull-high function of the P64 pin.

Bit 3 (/PH3): Control bit used to enable the pull-high function of the P53 pin.

Bit 2 (/PH2): Control bit used to enable the pull-high function of the P52 pin.

Bit 1 (/PH1): Control bit used to enable the pull-high function of the P51 pin.

Bit 0 (/PH0): Control bit used to enable the pull-high function of the P50 pin.

6.2.22 Bank 1-RE (WDT Control Register)

NOTE

??Bank 1-RE <0> register is both readable and writable

??Individual interrupt is enabled by setting its associated control bit in the Bank 1-RF <0 > to "1."

??Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Fig. 6-8 (Interrupt Input Circuit) under Section 6.6 (Interrupt).

Bit 7 (WDTE): Control bit is used to enable Watchdog Timer 0 = Disable WDT

1 = Enable WDT

WDTE is both readable and writable. Bits 6, 1: not used, fixed to 0 all the time

Bit 5 (PSWE): Prescaler enable bit for WDT

0 = prescaler disable bit. WDT rate is 1:1

1 = prescaler enable bit. WDT rate is set as Bit 4~Bit 2

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

Bit 4 ~ Bit 2 (PSW2 ~ PSW0): WDT prescaler bits

Bit 0 (CMPIE): CMPIF interrupt enable bit 0 = Disable CMPIF interrupt 1 = Enable CMPIF interrupt

When the Comparator output status change is used to enter an interrupt vector or to enter next instruction, the CMPIE bit must be set to ???Enable???. But actually the output of the comparator must be read to latch the status first. Then the output of the comparator is compared to this latch to produce the information of output status change.

6.2.23 Bank 1-RF (Interrupt Mask Register)

NOTE

??RF register is both readable and writable.

??Individual interrupt is enabled by setting its associated control bit in the RF to "1."

??Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. Refer to Fig. 6-8 (Interrupt Input Circuit) under Section 6.6 (Interrupt).

Bits 7~3: not used bits, fixed to 0 all the time

Bit 2 (EXIE): EX0IF and EX1IF interrupts enable bit 0 = Disable EX0IF and EX1IF interrupts 1 = Enable EX0IF and EX1IF interrupts

Bit 1 (ICIE): ICIF interrupt enable bit 0 = Disable ICIF interrupt 1 = Enable ICIF interrupt

If Port 6 Input Status Change Interrupt is used to enter an interrupt vector or to enter next instruction, the ICIE bit must be set to ???Enable???.

Bit 0 (TCIE): TCIF interrupt enable bit 0 = Disable TCIF interrupt 1 = Enable TCIF interrupt

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.2.24 Bank 2-R5 (HDCR: High Drive Control Register for Port 6)

[With Simulator]: function nonexistent

[With EM78P221/2N]: General I/O pins

Bit 7 (HD67): Output High Drive Current Select for P67

Bit 6 (HD66): Output High Drive Current Select for P66

Bit 5 (HD65): Output High Drive Current Select for P65

Bit 4 (HD64): Output High Drive Current Select for P64

Bit 3 (HD63): Output High Drive Current Select for P63

Bit 2 (HD62): Output High Drive Current Select for P62

Bit 1 (HD61): Output High Drive Current Select for P61

Bit 0 (HD60): Output High Drive Current Select for P60

6.2.25 Bank 2-R6 (HSCR1: High Sink Control Register for Port 5)

[With Simulator]: function nonexistent

[With EM78P221/2N]: General I/O pins

Bit 7 (HS57): Output High Sink Current Select for P57

Bit 6 (HS56): Output High Sink Current Select for P56

Bit 5 (HS55): Output High Sink Current Select for P55

Bit 4 (HS54): Output High Sink Current Select for P54

Bit 3 (HS53): Output High Sink Current Select for P53

Bit 2 (HS52): Output High Sink Current Select for P52

Bit 1 (HS51): Output High Sink Current Select for P51

Bit 0 (HS50): Output High Sink Current Select for P50

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.2.26 Bank 2-R7 (HSCR2: High Sink Control Register for Port 6)

[With Simulator]: function nonexistent

[With EM78P221/2N]: General I/O pins.

Bit 7 (HS67): Output High Sink Current Select for P67

Bit 6 (HS66): Output High Sink Current Select for P66

Bit 5 (HS65): Output High Sink Current Select for P65

Bit 4 (HS64): Output High Sink Current Select for P64

Bit 3 (HS63): Output High Sink Current Select for P63

Bit 2 (HS62): Output High Sink Current Select for P62

Bit 1 (HS61): Output High Sink Current Select for P61

Bit 0 (HS60): Output High Sink Current Select for P60

6.2.27 Bank 2-R8 (Operating Mode Control Register)

Bits 7, 4~0: not used, fixed to "0" all the time.

Bits 6~5: not used, fixed to "1" all the time.

NOTE

???If user wants the MCU to work normally, user must set Bit 6 and Bit 5 of the R8 register to ???1??? and clear Bit 4 of R8 register to ???0???.

6.2.28Bank 2-R9~RF (Reserve)

Bits 7~0: not used, fixed to "0" all the time

6.2.29 Bank 3-R5 (Timer Clock/Counter)

??Incremented by an external signal edge through the TCC pin, or by the instruction cycle clock.

??External signal of TCC trigger pulse width must be greater than one instruction.

??The signals to increase the counter are determined by Bit 4 and Bit 5 of the CONT register.

??Writable and readable as any other registers.

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.2.30 Bank 3-R6 (IRC Control)-only for ICE

Bits 7 ~ 2:

[With Simulator (C3~C0, RCM1~RCM0)]: IRC calibration bits in IRC oscillator mode. In IRC oscillator mode of ICE220N simulator, these are the IRC mode selection bits and IRC calibration bits.

1.Frequency values shown are theoretical and taken at an instance of a high frequency mode. Hence, frequency values are shown for reference only. Definite values depend on the actual process.

2.Similar way of calculation is also applicable to low frequency mode.

Bits 1 ~ 0: are not used, fixed to "0" all the time.

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.2.31 Bank 3-R7 (Noise and LVR Control) - only for ICE

Bits 7 ~ 4: not used, fixed to "0" all the time.

Bits 3 ~ 0:

[With EM78P221/2N]: Unimplemented, read as ???0???.

[With Simulator]:

Bit 3 (NRHL): Noise rejection high/low pulses define bit. The INT pin is a falling edge trigger

0 = Pulses equal to 8/fc [s] are regarded as signal.

1 = Pulses equal to 32/fc [s] are regarded as signal (default)

NOTE

The noise rejection function is turned off in the LXT2 and sleep mode.

Bit 2 (NRE): Noise rejection enable

0 = disable noise rejection

1 = enable noise rejection (default). However in Low Crystal oscillator (LXT) mode, the noise rejection circuit is always disabled.

Bits 1 ~ 0 (LVR1 ~ LVR0): Low Voltage Reset enable bits. If Vdd has crossover at Vdd reset level as Vdd changes, the system will be reset.

6.2.32Bank 3-R8~RF (Reserve)

Bits 7~0: not used, fixed to "0" all the time.

6.2.33R10 ~ R1F

All of these are 8-bit general-purpose registers.

6.2.34Banks 0~3 - R20 ~ R3F

All of these are 8-bit general-purpose registers.

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.3 TCC/WDT and Prescaler

There are two 8-bit counters available as prescalers for the TCC and WDT. The PST0~PST2 bits of the CONT register are used to determine the ratio of the TCC prescaler, and the PWR0~PWR2 bits of the Bank 1-RE register are used to determine the WDT prescaler. The prescaler counter is cleared by the instructions each time such instructions are written into TCC. The WDT and prescaler are cleared by the ???WDTC??? and ???SLEP??? instructions. Fig. 6-2 depicts the block diagram of TCC/WDT.

TCC (Bank 3-R5) is an 8-bit timer/counter. The TCC clock source can be internal clock (Fosc) or external signal input (edge selectable from the TCC pin). If the TCC signal source is from an external clock input, TCC will be incremented by 1 at every falling edge or rising edge of the TCC pin. The TCC pin input time length (kept at High or Low level) must be greater than 1CLK. 1 CLK is always Fosc/2..Refer to Fig. 6-2.

NOTE

The internal TCC will stop running when in sleep mode.

The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even when the oscillator driver has been turned off (i.e., in sleep mode). During normal operation or sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled at any time during normal mode through software programming. Refer to WDTE bit of Bank 1-RE register (Section 6.2.10 Bank 1-RE (WDT Control Register). With no prescaler, the WDT time-out duration is approximately 18ms.1

1VDD=5V, WDT Time-out period = 15.2ms ?? 30%. VDD=3V, WDT Time-out period = 18ms ?? 30%.

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

Fig. 6-2 TCC and WDT Block Diagram

6.4 I/O Ports

The I/O registers (Port 5, Port 6, Port 7, and Port 8) are bidirectional tri-state I/O ports. The Pull-high, Pull-down, and Open-drain functions can be set internally by Bank 1-RB, Bank 1-RC, and Bank 1-RD respectively. The High Drive, and High Sink functions can be set internally by Bank 2-R5, Bank 2-R6, and Bank 2-R7 respectively. Port 6 features an input status change interrupt (or wake-up) function. Most I/O pin can be defined as "input" or "output" pin by the I/O control registers (P52, P53 are only used as output pins). The I/O registers and I/O control registers are both readable and writable. However, the initial states of these I/O ports (Port 5, Port 6, Port 7 and Port 8) are unknown input (high impedance). Then, if the I/O pin is pulled to a level at external circuit, the pin must induce a voltage. Hence, user must take into consideration whether the induced voltage causes a wrong action in the system. The I/O interface circuits for Port 5, Port 6, Port 7, and Port 8 are illustrated in Figures 6-3, 6-4, & 6-5 respectively. Port 6 with Input Change Interrupt/Wake-up is shown in Fig. 6-6.

Note: Pull-high and Open-drain are not shown in the figure.

Fig. 6-3 I/O Port and I/O Control Register Circuit for Port 5 , Port 7 and Port 8

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

Note: CO2, Pull-high and Open-drain are not shown in the figure.

Note: Pull-high (down) and Open-drain are not shown in the figure.

Fig. 6-5 I/O Port and I/O Control Register Circuit for Port 6

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

Fig. 6-6 Port 6 Block Diagram with Input Change Interrupt/Wake-up

6.4.1 Usage of Port 6 Input Change Wake-up/Interrupt Function

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.5 Reset and Wake-up

6.5.1 Reset and Wake-up Operation

A reset is initiated by one of the following events:

1.Power-on reset

2./RESET pin input "low"

3.WDT time-out (if enabled)

A device is kept in a reset condition for a duration of approximately 18ms2 after the reset is detected. When in LXT mode, the reset time is 500ms. Once a reset occurs, the following functions are performed (the initial address is 000h):

??The oscillator continues running, or will be started (if in sleep mode)

??The Program Counter (R2) is set to all "0"

??All I/O port pins are configured as input mode (high-impedance state)

??The Watchdog Timer and prescaler are cleared

??When power is switched On, the Memory switch register (R1) is set to 0

??The CONT register bits are set to all "0" except for Bit 6 (INT flag)

??The Bank 0-RF register bits are set to all "0"

??The Bank 1-RB register bits are set to all "1"

??The Bank 1-RC register bits are set to all "1"

??The Bank 1-RD register bits are set to all "1"

??The Bank 1-RE register bits are set to all "0"

??The Bank 1-RF register bits are set to all "0"

Executing the ???SLEP??? instruction will assert the sleep (power down) mode. While entering sleep mode, the Oscillator and TCC are stopped. The WDT (if enabled) is cleared but keeps on running.

The controller can be awakened by:

Case 1 External reset input on /RESET pin

Case 2 WDT time-out (if enabled)

Case 3 Port 6 input status changes (if ICWE is enabled)

Case 4 Comparator output status changes (if CMPWE is enabled)

2VDD=5V, Setup time period = 16.5ms ?? 30%. VDD=3V, Setup time period = 18ms ?? 30%.

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

The first two cases (1 & 2) will cause the EM78P221/2N to reset. The T and P flags of R3 can be used to determine the source of the reset (wake-up). Cases 3 & 4 are considered the continuation of program execution and the global interrupt ("ENI" or "DISI" being executed) decides whether or not the controller branches to the interrupt vector following a wake-up. If ENI is executed before SLEP, the instruction will begin to execute from Address 0x8 after wake-up. If DISI is executed before SLEP, the execution will restart from the instruction next to SLEP after wake-up. All sleep mode wake up time is dependent on the oscillator mode, no matter what the oscillator type or mode is (except when it???s in LXT2 mode). In LXT2 mode, wake-up time is 2 ~ 3 sec.

Only one of Cases 1 to 4 can be enabled before entering into sleep mode. That is:

Case [a] If WDT is enabled before SLEP, all of the RE bit is disabled. Hence, the EM78P221/2N can be awakened only with Case 1 or Case 2. Refer to the section on Interrupt (Section 6.6) for further details.

Case [b] If Port 6 Input Status Change is used to wake -up EM78P221/2N and ICWE bit of Bank 0-RE register is enabled before SLEP, WDT must be disabled. Hence, the EM78P221/2N can be awakened only with Case 3. Wake-up time is dependent on the oscillator mode. In RC mode (VDD: 5V, IRC: 4MHz), wake-up time is 10 ??s (for stable oscillators). In HXT2 mode (VDD: 5V, Crystal: 4MHz, C1/C2: 30pF), wake-up time is 800??s (for stable oscillators), and in LXT2 mode, wake-up time is 2 ~ 3 sec.

Case [c] If the Comparator output status change is used to wake-up the EM78P221/ 2N and the CMPWE bit of the RE register is enabled before SLEP, WDT must be disabled by software. Hence, the EM78P221/2N can be awakened only with Case 4.

Wake-up time is dependent on the oscillator mode. In RC mode (VDD: 5V,

IRC: 4MHz), wake-up time is 10??s (for stable oscillators). In HXT2 mode

(VDD: 5V, Crystal: 4MHz, C1/C2: 30 pF), wake-up time is 800??s (for stable oscillators), and in LXT2 mode, wake-up time is 2 ~ 3 sec.

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

If Port 6 Input Status Change Interrupt is used to wake up the EM78P221/2N (as in Case b above), the following instructions must be executed before SLEP:

Similarly, if the Comparator Interrupt is used to wake up the EM78P221/2N (as in Case [c] above), the following instructions must be executed before SLEP:

6.5.1.1Wake-up and Interrupt Modes Operation Summary

All categories under Reset, Wake-up and Interrupt modes are summarized below.

After wake up:

1.If interrupt enable ??? interrupt+ next instruction

2.If interrupt disable ??? next instruction

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

The controller can be awakened from sleep mode and idle mode. The wake-up signals are listed as follows:

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.5.1.2Register Initial Values after Reset

The following table summarizes the registers initialized values.

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.5.1.3Controller Reset Block Diagram

Fig. 6-7 Controller Reset Block Diagram

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.5.2 The T and P Status under Status Register

A reset condition is initiated by one of the following events:

1.Power-on reset

2./RESET pin input "low"

3.WDT time-out (if enabled)

The values of T and P as listed in the table below, are used to check how the processor wakes up.

* P: Previous status before reset

The following shows the events that may affect the status of T and P.

* P: Previous value before reset

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.6 Interrupt

The EM78P221/2N has four interrupts as listed below:

1.TCC overflow interrupt

2.Port 6 Input Status Change Interrupt

3.External interrupt INT0, INT1

4.When the Comparator 1 output status changes

Before the Port 6 Input Status Change Interrupt is enabled, reading Port 6 (e.g., "MOV R6, R6") is necessary. Each Port 6 pin will have this feature if its status changes. Port 6 Input Status Change Interrupt will wake up the EM78P221/2N from sleep mode if it is enabled prior to going into sleep mode by executing SLEP. When wake-up occurs, the controller will continue to execute the succeeding program if the global interrupt is disabled. If enabled, it will branch out to the interrupt vector 008H.

The external interrupt has a built-in digital noise rejection circuit (if the input pulse is less than 8-system clock time, it is eliminated as noise. Edge selection is possible with /INT. Refer to Word 1 Bits 8~7 (Section 6.13.2, Code Option Register (Word 1)) for digital noise rejection definition.

During a power source unstable situation, like during external power noise interference or EMS test condition, it will cause the power to vibrate fiercely. While Vdd is still unsettled, the supply voltage may be below working voltage. When the system supply voltage Vdd is below the working voltage, the IC kernel must automatically keep all register status.

Bank 0-RE and Bank 0-RF are the interrupt status register that records the interrupt requests in the relative flags/bits. Bank 1-RE and Bank 1-RF are interrupt mask registers. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When one of the interrupts (when enabled) occurs, the next instruction will be fetched from Address 008H. Once in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in Bank 0-RE and Bank 0-RF. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine to avoid recursive interrupts.

When interrupt mask bits is ???Enable???, the flag in the Interrupt Status Register (RF) is set regardless of the ENI execution. Note that the result of Bank 0-RE/RF will be the logic AND of BANK 0-RE/RF and Bank 1-RE/RF (refer to Fig. 6-8). The RETI instruction ends the interrupt routine and enables the global interrupt (the ENI execution).

When any interrupt occurs, the contents of ACC, R1 (Bits 5, 4, 1, 0), R3 (Bits 2 ~0), R4 registers are pushed to the corresponding stack (Fig 6-9). After the RETI instruction is executed, the content of the corresponding stack are popped to ACC, R1 (Bits 5, 4, 1, 0), R3 (Bits 2 ~0), R4 registers.

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

Fig. 6-8 Interrupt Input Circuit

Fig. 6-9 Interrupt Backup Diagram

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.7 Comparator

The EM78P221/2N has one comparator comprising of two analog inputs and one output. The comparator can be utilized to wake up the EM78P221/2N from sleep mode. The comparator circuit diagram is depicted in the figure below.

Fig. 6-10 Comparator Circuit Diagram & Operating Mode

6.7.1External Reference Signal

The analog signal presented at Cin??? compares to the signal at Cin+, and the digital output (CO) of the comparator is adjusted accordingly by taking the following notes into considerations:

NOTE

???The reference signal must be between Vss and Vdd.

???The reference voltage can be applied to either pin of the comparator.

???Threshold detector applications may be of the same reference.

???The comparator can operate from the same or different reference sources.

6.7.2Comparator Outputs

??The compared result is stored in the CMPOUT of Bank 1-RA.

??Bits 3 ~ 4 <CMPCOS1, CMPCOS0> of the Bank 1-RA register. See Section 6.2.18,

Bank 1-RA (CMPCON: Comparator Control Register) for Comparator select bits function description.

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

NOTE

???The highest priority of P71/INT1/CO is INT1. When EIS1=0, the working type of P71/INT1/CO is determined by CMPCOS1 and CMPCOS2.

???The CO and P71of the P71/CO pins cannot be used at the same time.

???The P71/CO pin priority is as follows:

P71/INT1/CO Pin Priority

The following figure shows the Comparator Output block diagram.

Fig. 6-11 Comparator Output Configuration

6.7.3Using a Comparator as an Operation Amplifier

6.7.3.1Bank 0-RE (WUCR: Wake-up Control Register)

Bit 2 (CMPWE): Comparator wake-up enable bit

0= Disable Comparator wake-up

1= Enable Comparator wake-up

When the Comparator output status change is used to enter an interrupt vector or to wake-up the EM78P221/2N from sleep, the CMPWE bit must be set to ???Enable???.

Bit 0 (CMPIF): Comparator interrupt flag. Set when a change occurs in the Comparator output. Reset by software

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.7.3.2Bank 1-RA (CMPCON: Comparator Control Register)

6.7.3.3Bank 1-RE (WDT Control Register)

Bit 0 (CMPIE): CMPIF interrupt enable bit 0 = Disable CMPIF interrupt 1 = Enable CMPIF interrupt

When the Comparator output status change is used to enter an interrupt vector or to enter the next instruction, the CMPIE bit must be set to ???Enable???. But actually the comparator output must be read to latch the status at first. Then the comparator output is compared to this latch to produce the information of output status change.

6.7.4 Comparator Interrupt

?? CMPIE must be enabled for the ???ENI??? instruction to take effect

?? Interrupt is triggered whenever a change occurs on the comparator output pin ?? The actual change on the pin can be determined by reading the Bit CMPOUT ?? CMPIF the comparator interrupt flag, can only be cleared by software

6.7.5 Wake-up from Sleep Mode

??If enabled, the comparator remains active and the interrupt remains functional, even in Sleep mode.

??If a mismatch occurs, the interrupt will wake up the device from Sleep mode.

??The power consumption should be taken into consideration for the benefit of energy conservation.

??If the function is unemployed during Sleep mode, turn off the comparator before entering sleep mode.

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.8 Oscillator

6.8.1 Oscillator Modes

The EM78P221/2N can be operated in six different oscillator modes, such as High Crystal oscillator mode (HXT 1, 2), Low Crystal oscillator mode (LXT 1, 2), External RC oscillator mode (ERC), and RC oscillator mode with Internal RC oscillator (IRC). Select one of such modes by programming the OSC2, OCS1, and OSC0 in the Code Option register.

The Oscillator modes defined by OSC2, OCS1, and OSC0 are described below.

1In ERC mode, OSCI is used as oscillator pin. OSCO/P52 is defined by code option Word 0 Bit 6 ~ Bit 4.

2In IRC mode, P53 is normal I/O pin. OSCO/P52 is defined by code option Word 0 Bit 6 ~ Bit 4.

3In LXT1, LXT2, HXT1 and HXT2 modes; OSCI and OSCO are used as oscillator pins. These pins cannot and should not be defined as normal I/O pins.

The maximum operating frequency limit of the crystal/resonator at different VDDs, are as follows:

6.8.2 Crystal Oscillator/Ceramic Resonators (Crystal)

The EM78P221/2N can be driven by an external clock signal through the OSCO pin as illustrated below.

OSCI

Ext.

Clock in

OSCO Clock out

Fig. 6-12 External Clock Input Circuit

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

In most applications, Pin OSCI and Pin OSCO can be connected with a crystal or ceramic resonator to generate oscillation. Fig. 6-13 below depicts such a circuit. The same applies to the HXT 1, 2 modes and the LXT 1, 2 modes.

Fig. 6-13 Crystal/Resonator Circuit

The following table provides the recommended values for C1 and C2. Since each resonator has its own attribute, user should refer to the resonator specifications for appropriate values of C1 and C2. RS, a serial resistor, may be required for AT strip cut crystal or low frequency mode. Fig 6-13-1 is a recommended PCB layout. When the system works in Crystal mode (16MHz), a 10K??? is connected between OSCI and OSCO.

Capacitor selection guide for crystal oscillator or ceramic resonators:

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

Fig. 6-13-1 Parallel Mode Crystal/Resonator Circuit Diagram

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.8.3External RC Oscillator Mode

In order to maintain a stable system frequency, the values of the Cext should not be less than 20pF, and the value of Rext should not be greater than 1M??. If the frequency cannot be kept within this range, the frequency can be easily affected by noise, humidity, and leakage.

The smaller the Rext in the RC oscillator, the faster its frequency will be. On the contrary, for very low Rext values, for instance, 1 K??, the oscillator will become unstable because the NMOS cannot discharge the capacitance current correctly.

Based on the above reasons, it must be kept in mind that all the supply voltage, the operation temperature, the components of the RC oscillator, the package types, and the PCB is layout, have certain effect on the system frequency.

The RC Oscillator frequencies:

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.8.4Internal RC Oscillator Mode

The EM78P221/2N offers a versatile internal RC mode with default frequency value of 4MHz. Internal RC oscillator mode has other frequencies (1MHz, 16MHz, and 455kHz) that can be set by Code Option (Word 1), RCM1, and RCM0. The Table below describes the EM78P221/2N internal RC drift with the variations on voltage, temperature, and process.

Internal RC Drift Rate (Ta=25??C, VDD=5.0V ?? 5%, VSS=0V)

Theoretical values are for reference only. Actual values may vary depending on actual process.

6.9Power-on Considerations

Any microcontroller is not warranted to start operating properly before the power supply stabilizes to a steady state. EM78P221/2N has a built-in Power-on Voltage Detector (POVD) with detection level range of 1.7V to 1.9V. The circuitry eliminates the extra external reset circuit. It will work well if Vdd rises quickly enough (50 ms or less). However, under critical applications, extra devices are still required to assist in solving power-on problems.

6.9.1External Power-on Reset Circuit

supply has a slow power rise time. Since the current leakage from the /RESET pin is about ??5??A, it is recommended that R should not be greater than 40K. This way, the voltage at Pin /Reset is held below 0.2V. The diode (D) functions as a short circuit at power-down. The ???C??? capacitor is discharged rapidly and fully. Rin, the current-limited resistor, prevents high current discharge or ESD (electrostatic discharge) from flowing into Pin /RESET.

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.9.2Residual Voltage Protection

When the battery is replaced, device power Vdd is removed but residual voltage remains. The residual voltage may trip below Vdd minimum, but not to zero. This condition may cause a poor power-on reset. Fig. 6-16 and Fig. 6-17 show how to create a protection circuit against residual voltage.

VDD

VDD

33K

Q1 10K

/RESET

Fig. 6-16 Residual Voltage Protection Circuit 1

R1

Q1

/RESET

Fig. 6-17 Residual Voltage Protection Circuit 2

6.10 Low Voltage Reset

Low voltage reset (LVR) is designed for unstable power situation, such as external power noise interference or in EMS test condition.

When LVR is enabled, the system supply voltage (Vdd) drops below Vdd reset level (VRESET) and remains at 10??s, system reset will occur and the system will remain at reset status. The system will remain at reset status until Vdd voltage rises above Vdd release level. Refer to Fig 6-18.

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

LVR characteristics are set at Code Option Word 0, Bits 10 and 9. Detailed operation mode is as follows:

Word 0

Bits 10~9 (LVR1 ~ LVR0): Low Voltage Reset enable bits. If Vdd has crossover at Vdd reset level as Vdd changes, the system will reset.

Fig. 6-18 LVR Waveform Situation

6.11 Code Option

EM78P221/2N has two Code Option Words and one Customer ID word that are not a part of the normal program memory.

6.11.1 Code Option Register (Word 0)

Word 0

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

Bits 12 ~ 11 (Type 1, Type 0): Type selection for EM78P221N or EM78P222N

Note: LVR1 and LVR0 are at Bank 3-R7, when using ICE.

Bits 10 ~ 9 (LVR1 ~ LVR0): Low Voltage Reset control bits

Bit 8 (CLKS): Instruction time period option bit 0 = two oscillator time periods

1 = four oscillator time periods (Default) Refer to Section 6.12 for Instruction Set

Bit 7 (ENWDTB): Watchdog timer enable bit 0 = Enable

1 = Disable (default)

Bits 6, 5 & 4 (OSC2, OSC1 & OSC0): Oscillator Mode Selection bits

1In ERC mode, OSCI is used as oscillator pin. OSCO/P52 is defined by code option Word 0 Bit 6 ~ Bit 4.

2In IRC mode, P53 is normal I/O pin. OSCO/P52 is defined by code option Word 0 Bit 6 ~ Bit 4.

3In LXT1, LXT2, HXT1 and HXT2 modes; OSCI and OSCO are used as oscillator pins. These pins cannot and should not be defined as normal I/O pins.

Bit 3: Not used (Reserved). This bit is set to 0 all the time

Bits 2 ~ 0 (PR2 ~ PR0): Protect Bits

PR2 ~ PR0 are protect bits. Each protect status is as follows:

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

6.11.2 Code Option Register (Word 1)

Word 1

Bit 12: Not used (reserved), fixed to ???1??? all the time.

Bit 11: Not used (reserved), fixed to ???0??? all the time.

Bit 10 (RESETENB): P81/RESET pin select bit 0 = P81 set as /RESET pin

1 = P81 is general purpose input pin or open drain for output port

(Default)

Bit 9 (RCOUT): System clock output enable bit in IRC or ERC mode 0 = OSCO pin is open drain

1 = OSCO output instruction clock (Default)

Bit 8 (NRHL): Noise rejection high/low pulse define bit. INT pin has a falling edge trigger.

0 = Pulses equal to 8/fc are regarded as signal

1 = Pulses equal to 32/fc are regarded as signal (Default)

NOTE

NRHL and NRE are at Bank 3-R7, when using ICE.

Bit 7 (NRE): Noise rejection enable

0 = disable noise rejection

1 = enable noise rejection (default). However in Low Crystal oscillator (LXT2) mode, the noise rejection circuit is always disabled.

NOTE

The noise rejection function is turned off in LXT2 and sleep mode.

Bit 6: Not used (Reserved). This bit is set to ???1??? all the time.

NOTE

C3, C2, C1, C0, RCM1 and RCM0 are at Bank 3-R6, when using ICE.

Bits 5~2 (C3~C0): Internal RC mode Calibration bits. These bits must always be set to ???1??? only (auto calibration)

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

Bit 1 & Bit 0 (RCM1 & RCM0): RC mode selection bits

6.11.3 Customer ID Register (Word 2)

Bit 12: Not used (reserved), fixed to ???0??? all the time

Bit 11 (NRM):

0 = Noise reject Mode 2. For multi-time circuit use, such as key scan and LED output.

1 = Noise reject Mode 1. For General input or output use. (Default) Bits 10~9: Not used (reserved), fixed to ???1??? all the time

Bits 8 ~ 0: Customer???s ID code

6.12 Instruction Set

Each instruction in the instruction set is a 13-bit word divided into an OP code and one or more operands. Normally, all instructions are executed within one single instruction cycle (one instruction consists of 2 oscillator time periods). Note the program counter is changed by instructions "MOV R2,A," "ADD R2,A," or by instructions of arithmetic or logic operation on R2 (e.g., "SUB R2,A," "BS(C) R2,6," "CLR R2," etc.). In this case, these instructions only need one instruction cycles

In addition, the instruction set has the following features:

1.Every bit of any register can be set, cleared, or tested directly.

2.The I/O registers can be regarded as general registers. That is, the same instruction can operate on I/O registers.

Convention:

R = Register designator that specifies which one of the registers (including operation and general purpose registers) is to be utilized by the instruction.

b = Bit field designator that selects the value for the bit located in the register R and which affects the operation.

k = 8 or 10-bit constant or literal value

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

Note: 1 This instruction is not recommended for RF operation

2 This instruction cannot operate under RF.

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

Internal RC Electrical Characteristics (Ta=25??C, VDD=5 V, VSS=0V)

Internal RC Electrical Characteristics (Ta=-40 ~85??C, VDD=2.1~5.5 V, VSS=0V)

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

8.1 Comparator (OP) Characteristic

Vdd = 5.0V, Vss=0V, Ta=25??C

Note: 1. The output voltage is in the unit gain circuitry and over the full input common-mode range.

2. The input common-mode voltage or either input signal voltage should not be allowed to go negative by more than 0.3V. The upper end of the common-mode voltage range is VDD-1.

3. The response time specified is a 100mV input step with 5mV overdrive.

9 AC Electrical Characteristic

Ta=25??C, VDD=5V??5%, VSS=0V

Note: *N = selected prescaler ratio

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

10 Timing Diagrams

AC Test Input/Output Waveform

AC Testing : Input is driven at VDD-0.5V for logic "1",and GND+0.5V for logic "0".Timing measurements are made at 0.75VDD for logic "1",and 0.25VDD for logic "0".

RESET Timing (CLK="0")

CLK

/RESET

Tdrh

TCC Input Timing (CLKS="0")

Tins

CLK

TCC

Ttcc

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

APPENDIX

A Package Type

Green products do not contain hazardous substances.

The third edition of Sony SS-00259 standard.

Pb contents should be less than 100ppm

Pb contents comply with Sony specs.

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

B Packaging Configuration

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

B.3 24-Lead Plastic Shrink Small Outline (SSOP) ??? 209 mil

TITLE:

SSOP-24L(209MIL) PACKAGE

OUTLINE DIMENSION

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

B.4 28- Lead Plastic Skinny Dual in line (SDIP) ??? 300 mil

A

TITLE:

PDIP-28L SKINNY 300MIL

PACKAGE OUTLINE

DIMENSION

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

(This specification is subject to change without further notice)

EM78P221/2N

8-Bit Microcontroller with OTP ROM

C Quality Assurance and Reliability

C.1 Address Trap Detect

An address trap detect is one of the MCU embedded fail-safe functions that detects MCU malfunction caused by noise or the like. Whenever the MCU attempts to fetch an instruction from a certain section of ROM, an internal recovery circuit is auto started. If a noise caused address error is detected, the MCU will repeat execution of the program until the noise is eliminated. The MCU will then continue to execute the next program.

(This specification is subject to change without further notice)