Other I/F

Other functions

Software

Basic CP/M

CP/M Expanded CP/M

MZ3500

1-2. MZ-1K01 (Keyboard) specification

MZ1K03: U.K. keyboard (ISO).

MZ1K05: French keyboard

80C49 or 8749

4049x2,4514

Mechanical contact key, with life of 10,000,000 operations.

61 Ten key 15 Function keys 6 Definable keys 10

1

Interfacing cables

Specification

Other

Cabinet

For data transfer with the CPU (serial) and power supply (transmission under 15,000 baud)

Use of coiled cable with 8-pin DIN plug

Automatic repeat occurs 0.64 seconds after

Repeat function. . . . . 2 Two-key rollover continuous depression of the same key.

Indicators (4 LED's) POWER, Alphanumeric keys

Outline

Optional board used graphic display functions with the Model-3500 series CPU. It includes 32KB of RAM. It is inserted through the slot on the front panel of the PU.

The MZ-1U02 expansion box is not required.

GDC Graphic controller

MPD7220

LSI

vinrn HAM

Basic (buit-in)

Expansion (optional)

16KDRAM x 16 (32KB)

Specifications

Graphic functions (Color must be specified for each dot. when the color video unit is in use)

~~~~~???____WDEO RAM

640 x 200 green monitor

640 x 200 color monitor

640 x 400 green monitor

640 x 400 color monitor

Software

Outline

Specifications

Optional board for memory expantion of the MZ-3500sries CPU.with this option the main memory (RAM) can be expanded up to a maximum of 256 KB.

This option plug into the expantion box in slot 1 or 3.

1-7. MZ-1D07

MZ3500

Outline

Specifications

High resolution MZ

Video tube

Display capacity

Display size

Input signals

Power supply

Cabinet

Adjusting knobs Accessories

CPU connection cable andpower cord and Tilt stand

12", 90" deflection

640 horizontal dots,

400 vertical lines

47 8 Hz

7.2kg

Memory will be operated under four states of SDO ~ SD3, depending on the hardware and software configurations. In the paragraphs to follow, description will be made for those four states.

MAIN CPU

MAS 00 1

MA2 001

MAI 001

MAO 011

2-1. SDO (INITIALIZE STATE)

SDO can only exist immediately after power on, and the system executes IPL under this condition and that the system thus loaded will automatically assign memory area

for SD1, SD2. and SD3.

SUB CPU

MS1 = ?? (D

MSO = 0 (L)

FFFF

V FFFF T

? IRAM(COM^ reoojOO1?????? ^\

M 7. 3500

Operational description

(1)Upon reset after power on, the main CPU loads the contents of the initial program loader (IPL) into RAM starting at address 4000H, during which time reset is applied to the sub-CPU.

TIMING OF RESET SIGNAL

Vtc-

S Y S K E S -

SKES-

(2)The main CPU then terminates resetting the sub CPU and starts the sub-CPU. At the same time, the ROM IPL is assigned to the sub-CPU.

(3)The main CPU then send the memory allocation (state) to SD1, and starts to load DOS from the system floppy disk.

Signal generated from the

CR network and power supply

Output signal from the main CPU port

MAIN CPU

START

Memory Map Data:

1.ROM-B is tested to determine if ROM's are present.

2.The ROM-IPL functions under control of the main CPU at first, but later it functions under the sub-CPU after the IPL program hasbeen loaded in RAM.

3.RAM-COM is shared by both the main CPU and the sub-

CPU.

a.Main CPU reset time

b.Main CPU IPL load time

4.Memories other than described above cannot be accessed under the SDOstate.

5.Bank select, MAO~MA3, is used within the address range ofCOOOH-FFFFH.

ROM-IPL

1.An 8KB ROM (2764 or mask ROM equivalent) is used for the ROM-IPL.

2.When the system reset signal turns from low to high state after power on, the main CPU starts to operate At this stage, the ROM-IPL is addressed.

3.The CPU starts from address OOOOIROM address 10000)

4.The main CPU sets the sub-CPU reset signal from low to high state as it goes out of its initial state via the memory mapper and the sub-CPU starts to operate. At this point, the ROM-IPL is addressed by the sub-CPU.

5.Address 0000 of the sub-CPU is ROM address (0000) The memory area above ROM address (1000) cannot be used by the sub-CPU because the mam CPU initial program has been loaded there.

2-2. SD1 (SYSTEM LOADING & CP/M)

SD1 determines which operating system ts in use. The system is loaded in the CP/M (Control Program for Micro- processors) mode.

V

4

3

i

f. ft f n

MZ3500

Mam CPU logical address (during IPL operation)

Logical address of the sub-CPU

ROM physical address

OfFF 1 FFF 1 FFF

ROM IPL

0000 1 OOP 1 OOP

OFFF OFFF

0800 0800 07FF 07FF

0000 0000

MS1 = 0( L)

MSO=l(Hj

\

^ \

\\

\\

\\

\\

RAM sn

\ \

\\

\ \

\ \ RAM SA

\\

\\

KAM??.(IH) 2000 1FFF

MZ3500

Operational description

(1)As soon as the sub-CPU is started, it initializes the I/O port and waits for program transfer (IOCS) from the main CPU. This IOCS (Input Output Control System) is the program resident at address 4000H-5FFFH.

(2)As the main CPU loads the information from sector

Communication between Main and SUB CPU

2:3. SD2 (ROM based BASIC)

SD2 is active when "SHARP BASIC" is executed via ROM.

"1" of track "0" of the floppy disk, it loads the IOCS and bootstrap routine to the sub-CPU.

(3)The bootstrap program is loaded next.

(4)The bootstrap program determines rnemory allocation.

BUSRQ H OUTPUT

| (ISOLATION OFCOM RAM)

-

1.Bank select, MAO-MA3. is effective for memory area COOOH-FFFFH.

2.Bank select, MOO-MO2, is effective for memory area 2000H-3FFFH.

SUB CPU

1

vx

\\RAN. SP

\\RAN SC

ROM BAS

k ' SUB CPU

3-1. Block diagram

1)Relation between MMR (Main Memory Mapper) and main memory.

, RAM

I (II'TION

I

R E C E I V F R

1

4- RAN

' 64KBV2)

VI ??l

1

1 OPTION

.

3-2. Main CPU and I/O port

^0 MFUC

???\J lUMr

5 O IOABCMEMORY MAPPER)

SFD interface FDC chip select.

AO used for RD and WR.

A1 is "don't care".

SFD interface I/O port and DMAC chip select.

Interrupt signal from the sub-CPU to the main CPU. Flipflop resetting signal.

MFD interface I/O port.

AO used for RD and WR.

AT is "don't care".

I/O port select in the memory mapper. AO and A1 used during ~W5. WR.

MZ3500

3-3. Sub CPU and I/O port

Shown at the left is the circuit used by the CPU to select the I/O ports The out put address from the sub CPU is decoded by the 74LS138to create the select signal. Shown below is the address map and select signals.

AS 7654 M??X\

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

74LS138

NOT USE

3-4. Memory mapper (MMR)SP6102R-001

1) Block diagram

INTB

WAIT

TIMING

WAITB GENERATOR

CLK

MZ3500

Memory mapping logic

A 15

AU

INTERRUPT

PRIORITY

ENCORDER

1 N T F I)

Polarity

Pin No.

Signal Name

32RF1B

33RF2B

34WATB

35RCMB

36ITFB

37ITOB

38IT1B

39TT2B

40MRQB

41WRB

42IT3B

43IT4B

44SEC

45GND

46Vcc

47SW1

48SW2

49AO

50RFSH

51SW3

52SW4

53GND

54FD1

55Vcc

56FD2

M 7, 3500

Interrupt input from the UPD765 FDC (Floppy Disk Controller).

IN

(Interrupt from Floppy)

Interrupt input from the sub-CPU.

IN

(Interrupt from No. 0)

Interrupt input from slot 1 or 2.

IN

(Interrupt from No. 1, 2)

Memory request signal from the main CPU.

IN

(Memory Request)

Write signal from the main CPU.

IN

(Write)

Interrupt input from slot 3 or 4.

IN

(Interrupt from No. 3, 4)

Input from the FDD (Floppy Disk Drive) assignment dip switch (A), No. 1.

IN 'See the dip switch description, provided separately. (Section)

IN Ground

Input from Thesvstem assignment dip switch,

IN

"See the dip switch description, provided separately.

Mam CPU address bus

IN

Used rn the I/O port select logic in the MMR to designate device number.

Refresh signal from the main CPU.

IN

(Refresh)

Input from the system assignment dip switch.

IN

???See the dip switch description, provided separately.

IN Ground

Input from the system assignment dip switch.

IN

'See the dip switch description, provided separately.

Input from the FDD assignment dip switch (A), No. 2.

IN

*See the dip swi'ch description, provided separately.

ADDKKSS

A7 A6 A5|A4|A3|A2|Al|AO H E X UHUS 1 O

01

r\i IT

DO

D7

1 1 1 1 1 1 0 KI)1 Dl

DO 1)7 D6 D5

D4 OUT

D2

Dl

1 1 1 1 1 1 1 0 FE DO D4 D3

D2 INI

Dl

DO

D7

D6

D5

1 1 1 1 1 1 1 1 FF 1)4 I N

D3

D2

Dl

DO

D7

D6

SKQB

1 1

SKI S

M S ]

M S O

M<\3

MA2

M A I

M A O

MO2

M O I

MOO

S W 4

b??3

M\2

Sttl

she

FD3

FD2

H>1

SKDY

SACK

1 N P 2

I MM

IN'1'0

M F 2

Mhl

SRQ Bus request from the mam CPU to the sob-CPU

Sub-CPU reset signal

Memory system define

Bank select signal to memory area of COOO-FFFF.

_J

Bank select signal to memory area of 2000-3FFF.

System assign switch

1.All output signals are reset to low level upon power on, except for SRBQ that goes high.

2.Noted with a star mark "??" are input/output signals, and rest of others are processedin the LSI.

#1 I/O port output of ME1 and ME2 uses the memory at the addresses.

( ME2->8000~BFFF

I ME1->-4000~7FFF

Mm i i -^. t <|,

"fJ~

11 1 H

" I "

H j H

M II TO t MOI??m

n (iHj 1I 1 H M 2hTisn 1 T4h TvfT J i\=TjTNT7 JM3

1 j X X

H 1 H | 1

H j H j H

H j H j H | H

01 iri T hkoM fMont

1 h

When ME1 and ME2 are in high state. RSAB (RASA) is inhibited during memory addresses in RAM-A that correspond to overlayed addresses for MET and ME2 This is not true during SD1 mode.

Wait timing generator

WAIT is issued once per main CPU fetch cycle. Its outut is tri state

1)ROM-IPL select by the main CPU

As ROM IPL turns to low level after power on address bus buffers (LS244, LS367) and data bus buffer (LS245) are enabled. S of the data selector 1C (LS157) is set to a low level to enable input 1A-4A. The 3Y and 2Y outputs of the LS157 then go low so that CE and OE of the ROM-IPL are from main CPU. The contents of the IPL-ROM are then read by the main CPU. Because the input pin (^16) of the address buffer (LS367) is connected to Vcc, IPL for the main CPU will be at address 1000 of the IPL-ROM. Switch SW2BA is the operation test dip switch which should be ON at all times.

2)RAM-COM select by the main CPU

When RAM COM is low, SRES high, and SACK low, the select input S of the selector 1C (LS157) is in low state so that input 1A-4A becomes effective. That is, the out- put 4Y is low and either 1Y (WE) or 2Y (OE) becomes low level, so asto enable to read or write RAM-COM.

3)ROM-IPL select by sub-CPU

Normally, the select signal S of the selector is pulled up to Vcc level that inputs 1B-4B are enabled by sub CPU. If A13 thru A15 were to be at low level, the output YO of the LS139 becomes low level so that the output 3Y of the LS147 or CE of the ROM-IPL should be at low level. Should SRD, SMRQ be at low lebel as well, the output 2Y of the LS157 or OE of the ROM-IPL turnde to low lebel to read the ROM-IPL. Though the sub-CPU can access an address range of 0000 to 1FFF theoretical- ly, it would be from 0000 to OFFF, actually.

4)RAM-COM select by sub-CPU

Y1 of the LS139 changes to low level when AS13 is high and AS14 and AS15 are low. In other words, the input 4B of the LS157 is at low level which brings the output Y4 to low level, so that CSof the RAM-COM chip select signal should become effective.

If SMRQ, SRD or SMRQ, SWR is in low level at this point, it enables read (OE) or write (WE). Address range, however, is 2000 to 3FFF

5)RAM (SA, SB, SC, SD) select by sub-CPU

SMRQ, SRD (Of) or SMRQ, SWR (WE) is at low level to select the sub-CPU dedicated RAM, SA-SD. Tne following chip select signal, then becomes valid under these conditions:

RAMSA .. ASVi, AS12, AS13, AS14, AST! (address 4000^17FF)

RAMSB .. AS11, AST2, AST3, AS14, AS15 (address 4800-4FFF)

RAMSC .. AS11, AS12, AS13, AS14, AS15 (address 5000-57FF)

RAMSD .. AS11, AS12, AS13, ASK, ASHi (address 5800-5FFF)

Color designation possible for each character

Color (one frame)

Blink, revers

Programmable for each character.

640 x 200 dots, B/W (Two frames)

Color designation possible for each character

640 x 200 dots. B/W (six frames)

Color designation possible for each character Color (Two frame)

^""~-\^ Type of monitor

Function^^\^^

Elements

Character structure

Medium resolution CRT (640 x 200 dots mode)

Screen structure (Characters x ines)

80 x 25 mode

80 x 20 mode

640 x 400 dot

40 x 25 mode

40 x 20 mode

Color

Basic

Option 1 (48KB)

designation

Option II (96KB)

Small tetter descenders

Line creation

Display memory

O

O

3KB32KB

One character screen igain-,t three graphic srrpens

One character screenagainst one graphic screen

One B/W character screen against three graphic screens

One color character screen against one graphic screen

Dip switch in the mam unit is used to select assignment of high resolution/medium resolution CRT.

Display mode must be chosen by programming.

1-2. Character structure and picture elements

M7 3500

W Whne

Three basic colors

4) Attribute

B/W Color

AT1 Vertical line B

AT2 Horizontal line R

AT3 Reverse G

AT4 Blink Blink

Designated for each chaia- cter.

Line and character r,,uy exist in the same element (Line may also be dis- played on the 80 charac ters x 25 lines screen.)

NOTE: In the case of 8 x 8 and 8 x 1 6 picture elements, vertically adjoining graphic symbols will joint together in the 25-line mode.

As for character structure of 6 x 14, 7 x 14, 6x7 , or 7 x 7, decision must be given on an actual dot pattern.

3)Color designation

Eight colors are usable (white, yellow, cyan, green, violet, red, blue, black)

Color designation

Background color

8 colors for designation

5} Screen overlay

It will be possible to have an overlaid screen that consists of one character (screen and a maximum of three graphic screens. (For detail of overlay screen, refer to Table 1.)

In the color mode, if there are two colors in the same screen and other designated for a dot on the graphic screen element ??? the one designated for a character on the character ??? both colors will be merged sltorjpther to produce image.

two color Jj>i"jrn*ion:.

MZ 3500

6)Screen overlay and displaying on two independent CRT's

As there are two video output channels it will be pos sible to display two independent screens on separate video display unit Overlay is possible on either of

screens (See preceding item 5) ) The following bit selection is needed for screen overlay

Function

Choice of outputting the character screen on CRT1 0 No 1 Yes Cho ce of outputting the character screen on CRT2 0 No 1 Yes

Choice of whether attribute or cursor be put on the frame that displayed on CRT2 (0 No 1 Yes)

Displays on CRT1 the blue elements contained in the VRAM Displays on CRT1 the red elements contained in the VRAM Displays on CRT1 the green elements contained in the VRAM Displays on CRT2 the blue elements contained in the VRAM Displays on CRT2 the red elements contained in the VRAM Displays on CRT2 the green elements contained m the VRAM

[ Choice of background color display

Color mode

Border color mode in effect

Defines the data size for the graphic RAM (0 8 bits, 1 16 bits) Defines display digits for the character screen

(0 40 digits 1 80 digits)

Connection of a 400 raster CRT

Connection of the 96K bytes VRAM

Connection of graphio GDC

25 lines/20 lines switching (0 25 lines, 1 20 lines)

7)ASCII CG

Uses an 8KB MROM contains two patterns'

640 x 400 dots ( 8 x 1 6 dots) and 640 x 200 dots (8x8 dots)

MZ3500

With 8 x 8 dot format

two kinds of patterns coexist Refer to ROM address and data code on separate information

1 5 2

IASCD/JIS]

8

Without line

[Graphic symbol

'With line

HL On 16th line

VL Line ot the right of element

In the case of graphic symbol display

Both HL and VLare overlaid to the pattern

MZ3500

2) 20 line display mode

2) 20 line display mode

8

20

Without line

10

\\NS\\\\Mi

ASCII

20

With line

HL On 18th raster

VL Line to the right of element

e VL does not join

a In the case of graphic symbol display, VL is overlaid to the pattern

Graphic symbol

j I Graphic symbol

9)Cursor

Sharp of the cursor: Same as seen in Model 3200 Reverse and blink)

10)Light pen input

Incorporates the light pen input connector and its inter- face. The light pen, however, is an option.

Accuracy: By each character

Function: Coordinates/charactercode

11)Difference in specification with that of Model 3200

(1)There are two modes for the Model 3200; normal mode ( 6 x 9 elements) and graphic mode ( 6 x 8 ele- ments). In the normal mode of 25-line displaying of the PC-3200, vertically adjacent graphic symbols do not joint. But, they will joint with the Model 3500.

4-2. Video RAM

1) Structure of VRAM

GDC1 (for character)

GDC2 (for graphic)

#BFFF

(D-RAM)

16Kh,t 1 6 K b i t

(2)No line will be displayed for the medium resolution CRT (640x200 dot).

It is possible to display line on the high resolution CRT, compatible to line the utilizing program of the Model 3200

ts-

2) Read/write from Z 80 to VRAM

(1)Timing period for display and V-RAM Read/write.

M 7 3500

//><-' Range wh??r? GDC can draw.

H ??? SYNC-

BLNK-

(2)Timing that the Z-80 can read/write VRAM The Z-80 can read/write VRAM when buffer is either empty or Full, and can be

3)Structure of character VRAM

(1)When read/write from GDC

#07FF(A)

2KX8

ASC I I

J

GDC FIFO accessed by

Fly back period

refreshing during the display period. Number of characters that can be read/write within one raster in any mode.

(A)(B)

ASCI I ( 8 b i t )

MZ3500

4)Graphic VRAM memory (MZIR03)

??? Block Diagram

1.read/write Mode

The select signal RASA, RASB and RASC are generate from RAS, A14 and A1 5 which is signal of GDC-2.

The address is allocated to each area selected by above signal.

Read/write by Z-80 via the GDC

(1) 640 x 200 dots display mode

Low High byte byte

+ 8000

#4000

A

B R 16K

#0000i

2.Display mode

A14 and A15 are not valid and RASA, RASB, RASC are selected together. By the DBIN signal from GDC-2. 08/16 signal isgener- ated by CSP-2.

The signal of 08/16 select, after P-5 conversion for RAMA, RAMB output signal then output to VB by serial signal, or sprit the signal to VB and VR.

(08/16 select: 08 for 200 rasters. 16 for 400 rasters)

During displaying

B/W: 3 frames

Color: 1 frame

#3FFF

16K

# 0 0 0 0

8bit 8bit 31,L

#3FFF

# 4 0 0 0

#0000

16K

# 0 0 0 0

16bit

5)Synchronize signal timing

(1)For 640 x 200 dots display mode

16K

16bit 16bit 16bit

(3)CRT synchronizing signal specification (400 raster

CRT)

1.Horizontal synchronization frequency (fH): 20.92kHz

2.Vercial synchronization frequency (fV): 47.3Hz

3.Total rasters: 441 rasters

4.Rasters used: 400 rasters

5.Display dots: 640 x 400 dots

6.Dot clock: (19.66MHz)

7.Timing

9.HS, VS, and VIDEO signals are supplied from the LS type TTL 1C(totem pole)

6)Setup of GCD master/slave

(1)Master/slave setup by combination

400 rasters

Master should be setup in the abovei.ia.

VFP: 11 rasters (0.5ms)

(CSP - 2)

VSYNC

Switching

Circuit

Priority

Signal Name

1 HSYi IN

2 NABC IN

3 CSR IN

4 - 6 ASO - AS2 IN

7 - 9 DSO - DS2 IN

10 G2 OUT

11 NWRO IN

12 NVB IN

13 NVR IN

14 NVB IN

15 FYD2 IN

16-18 AT2 - AT4 IN

19 CH IN

20.21 GND IN

22 DSP2 IN

23 VID2 OUT

24 LCD OUT

25 AT1 IN

26-28 LC1 - LC3 OUT

29 NCL4 OUT

30 HSYO OUT

31 RA40 OUT

32 VIDI OUT

33 B1 OUT

34 R1 OUT

35 Of OUT

36 SL1 IN

37 B2 OUT

38 R2 OUT

39 BLNK IN

40 Vcc IN

Horizontal synchronizing signal from the GDC1 Also, it becomes the refresh timing signal in the dynamic RAM mode.

Input from the UPD7220 GDC1. When the GDC1 is in the character display mode, the attribute, blinking timing and line counter ciear signals are multiplexed.

Input from the GDC1 which is the cursor display input when the GDC1 is in the character display mode.

Address bus input from the sub-CPU.

ABO = ASO, AB1 = AS1 , AB2 = AS2

Data bus input from the sub-CPU.

DBO = DBO, DB1 = DB1 , DB2 = DB2

Green image output to the CRT2.

CSP1 I/O port select signal (OUT #5X)

Input of the blue image from the graphic RAM(A) and (B).

Input of the red image from the graphic RAM (B), (C), and (D).

Input of the green image from the graphic RAM (E) and (F).

Input of the graphic RAM parallel/serial conversion 1C 74LS166 shift out clock. (Used to latch the image data in CSP1 .)

Attribute data input from the 2114A-1 attribute RAM.

Input of character display data signal.

0V supply

Input of display timing signal supplied from the CSP-2. (BLINK signal from the GDC2 is delayed by two flipflop intervals in the CSP-2 to creat this signal.)

VIDEO output to CRT2.

Character CG line counter output.

(Becomes address input to the CG when LCD = CG address AO.)

Attribute data input (vertical line/B) from the 2114A-1 attribute RAM.

Character CG line counter output.

(LC1 = A1, LC2 = A2, LC3 = A3CG = A3)

Character CG output data latch timing.

CRT1 , 2 horizontal synchronizing signal

The signal that turns high level when the 400-raster CRT is in connection. LDA, 01 H OUT??56

VIDEO output to the CRT1 .

Blue image output to the CRT1.

Red image output to the CRT1.

Green image output to the CRT1.

Character CG output parallel/serial converter 1C 74LS166 shift load signal, and character CG address latch signal input. (Used for the image data latch signal in the CSP-1 and horizontal synchronizing signal delay flipflop clock.)

Blue image output to CRT2.

Red image output to CRT2.

Erase signal from the GDC1 which becomes input at the following times.

1.Horizontal flyback period

2.Vertical flyback period

3.Period from the execution of the SYNC SET command to the execution of the DISP START command.

4.Line drawing period

+5V supply.

ASO

AS1

AS2

MkRO

DSO '

DS1

I)S2

HSYI

NABC

SL1

FYD2

BLNK

,r??T ,

K \ 400

I

' ???. >J

hI1 rn H 1

DSP2

ATI

AT 2

ATS

AT 4

CSR

CH

5-

HSYO

NVB -C

NVR

-c

D ???

F/F

J?^"

s

s ^ ' S ''

'"'

X

>- V I D 1

>

*??? ~*^

3>- V1D2

y-

???>-

Polarity

Horizontal synchronizing signal from GDC2 which also becomes the refresh tirniny . i j r . s ' i in the dynamic RAM mode.

Erase signal input from the GDC2 which is supplied 4T the following times:

1.Horizotal flyback period.

2.Vertical flyback period.

3.Period from the execution of the SYNC SET command to -be execution of the DISP START command.

4.Line drawing period.

WRITE ENABLE output for the graphic dynamic RAM.

Input of the display output signals (AD14, AD1 5) from GDC2. (Used to create DBIA-DBIC in the CSP-2.)

Input from the GDC2 by which the image memory output is sent on the data bus. (Used to create RASA-RASC, CAS, PS, OWE in the CSP-2.)

Input from the GDC1 by which the image memory output is sent on the data bus. (Used to create BUSG, SOE, SWE in the CSP-2.)

Gate signal of the bidirection bus buffer (LS245) which is used to read/write attribute, and character, data from the static RAM (21 14A-1 , 61 16P-3).

OUTPUT ENABLE for character static RAM (61 16P-3).

WRITE ENABLE for attribute, character static RAM.

8-bit/word and 16-bit/word select signal.

(8-bit/word chosen with LDA. OOH OUT#5D, and 16-bit/word is chosen with LDA, 01 H OUTiSD.)

Memory control signal RAS from GDC1. (Used to create CGOE, SL1 in CSP-2.)

Memory control signal RAS from CDC3.

(Used to create SL2, LOAD, RASA-RASC, CAS, FS. DBIA-DBIC. DSP2 in CSP-2.)

Address bus input from the sub-CPU (ASS = AB3)

Chip select (OUT#5X) of the I/O port in CSP-2.

Data bus input from the sub-CPU (DSO = DBO, DS1 = DB1 ).

The signal that goes to high level (input from CSP-1) when the 400-raster CRT is connected. (Used for clock frequency selection in CSP-2.)

Clock input from the clock generator (39.32MHz, for 400-raster mode.)

0V supply

Graphic DRAM output parallel/serial converter 1C 74LS166 shift load signal.

Graphic DRAM (A), (B) RAS signal.

Double character clock output. In the character display mode, a single phase clock of the half the one character wide frequency is supplied. In the graphic display mode, a single phase clock of 8/16 dot frequency is supplied to GDC2.

Graphic DRAM output parallel/serial converter 1C 74LS166 load timing clock.

+5V supply.

Graphic DRAM output parallel/serial converter 1C 74LS166 shift out clock.

Double character clock output same as 2CK2. In the character display mode, a single phase clock of one half the one character wide frequency is supplied to GDC1 .

Character CG output parallel/serial converter 1C74LS166 shift out clock.

Character CG output parallel/serial converter 1C LS166 shift load signal.

Character CG address.

Character CG output enable signal.

Timing signal by which the graphic DRAM output is sent on the data bus.

Graphic DRAM RAS (ROW ADDRESS SELECT) signal

RAS-B; RAM(C), (D) RAS-C; RAM (E), (F)

CSP 2 Block Diagram

S-RAM & CG control signal generator

t f

^??? Bl SC,

D- SOf

O- SHE

^

O???HB 1 A

1

2

3

4

5

6

7

8

9

10

11

12~19

20

21

22-34

HSYNC-REF OUT Memory contro' signal sent to the image memory from the GDC, which is the horizontal synchronizing signal.

???Since the image drawing process is automatically interrupted in the dynamic RAM mode the refresh address is output during the HSYNC period. It can also be used as the refresh timing signal.

???Refresh is accomplished by suppressing the CAS signal derived from the RAS signal in the external

circuit when the HSYC is at h gh lebel (Horizontal Synchronous - Refresh timing)

2.When the slave is operational : The synchronizing signal generationcounter is initialized by a high level input.

(Address/Data bus 0- 12)

4 8 CG Address Select Circuit

I

==

0020

8 b ts

M "

When 200 rasters on ASCII in use

(only the high order 8 bytes of 16 bytes are set to low level I

ASCII character structure of the 200 raster CRT

ASCII characterstructure of the 400 raster CRT

[Circuit description] (Purpose)

The character genrerator (CG) incorporates all character code^ used by the 200 raster video display unit of the \X 3500 and by the 400 raster video display unit of the \X 3500 The CG address select cirruit is therefore used to select those modes

[Operational description]

1When the 400 raster CRT is in use, RA40 is set to high level which sets A12 of the CG to high level at all times, so that the CG address above 1000 is selected Also, gate (1) opened so that LC3 is input to A3 of the CG At the same time, gate (3) is opened so that the gate of the LS240 is closed every 16 bytes

2When the 200 raster CRT is in use, RA40 is set turned to low level which sets A12 of the CG to low level continuously, so that the CG address 0000 OFFF is selected Also, gate (2) is opened so that the

CPU

- 45-

MZ 3500

4-9. VSYNC

0 40 Digit

From1 80 Digu

(8255 PB7) CH48

80 digit, 16bit/word Master is GDC-2

[Circuit description]

When more than two UPD7220 GDC's areto be operated in parallel, one must be assigned to the master and the other to the slave in order to mantain synchronous display timing. The master and the slave are determined according to the table below. The above circuit shoud be used to compare with the table description.

""~~~-~^GDC-1 (character)

The master GDC must be set as indicated above.

[Oprational example]

If it was set to 80 digit, 16 bit/word mode SRES will be 0 when CH48 = 1, 0816 = 1 when not in the reset condi- tion. These signals are supplied to terminal A (weight 1), B (weight 2), and G (gate), and set terminal Y3 of the decoder 1C LS139 to "0", so that the YSYNC output of the GDC2 is input to terminal EX SYNC of the GDC2.

SRES (From MMR)

40 digit. 16bu/word

80 digit, 8bit/word Master is GDC

40 digit, Sbit'word Master is GDC 1

MZ3500

4-12. Read/write from the Z-80 to V-RAM

Read/write of the Model 3500 V-RAM is done via the UPD7220GDC. There are two methods used to read/write data. The method (1) is used for the model 3500.

NO

YES

Set GDC command code

YES

Set parameter for the command

(1)Read/write via the 16 byte FIFO.

(2)Read/write of V-RAM in the DMA mode without intervention of the FIFO.

(Outline of the read/write data via the FIFO;

Method used to give a command to the GDC.

Example of graphic drawing by GDC

1) Dot display

VRAM 16-bit

structure

Example to display a dot on the fourth bit of the address

CSRW C 49H -COMMAND CODE

P1 01H ??? Low order one byte of the ab- solute address

P2 OOH ??? High order one byte of thp ah solute address

P3 30H - Dotaddress (dAD)

WRITE C 23H - COMMAND CODE

VECTE C 6CH - COMMAND CODE

5000 ??? 49 H

5001 ??? 01 H

5002 ??? 00 H

5003 ??? 30 H

CSRWdata

5004 ??? 23 H } W R I T E data 5005 ??? 6CH } VECTE data

C ???BOH (port address during graphic draw) B - Byte size CSRW data

HL - Topaddress of theCSRW data

Command, parameter of CSRW - GDC

B - Byte size of the WRITE data HL - Topaddress of theWRITE data

Command, parameter of W R I T E - GDC

B ??? Byte number of the VECTE data HL - Topaddress of theVECTE data

CSRW C 49H PI 28H P2 OOH P3 20H

TEXTW C 78H

PI FF

P2 FF

VECTW C 4 CH

PI OAH

P2 78H

P3 0 2 H

P4 88H

P5 H>H

P6 1 OH

P7 FBH

P8 O O H

P9 O O H

W R I T E C 23H

VECTE C 6CH

HAD I, ,H

dAU

Kind of line (solid line)

} Drawing direction

}

\1 AX I

1

5-1. Outline

Floppy disk is a disk which is made of a mylar sheet whose surface is coated with magnetic particles and set on the device to write and read data on the surface of the disk It will be necessary to know operating pnciple of the floppy disk unit and operational description, including recording method and format.

5-2. Floppy disk

As various recording methods and formats are used for floppy disk (F.D.) systems we will discuss some of them

3) Components of FD's:

1) Floppy disk nomenclature

Floppy disks called by different names dependng on the manufacturer

[>- Floppy media (or simply as medn) <???' Diskette

Floppy disk

2) Types of media

Four types are used at present depending on their storage capacity

(>- Single sided, double density (floppy disk-1)

[?? Double-sided, double density (floppy disk-2D)

Single sided media index detect hole

Double sided media index detect hole

Different write protects are adopted depending on the drive unit used.

Example-1: In the case of the CE331 the presence of light reflection is sensed by the photo coupler and decoded as write protect

Write enabled

Front side

- (Reflect"n<! r??ywing)

Two types of write protection are used and attention must bepaid to the presience of the label because it may cause a wrong result if the label is used improperly.

5)Media recording methods

Two recording methode are used:

???FM method (Single density)

This method is called the freqency modulation (FM)

n 1 n n 0

C D C D C

or double frequency (DF). Clock and data are written on the media which requires that a clock bit that precede the data.

Write current: The write data is input to the flipflop and is inverted each time a pulse is received to change the direction of writing current.

Read waveform: The peak of the waveform is detected at a change of magnetic flux. The waveform is than shaped to obtain read data identic it >.<_??? tlirf write data. Data cycle will be 4/^s.

o MFM method (double density)

The MFM method writes data on the basis of the condi tion metntioned below, and it yields a data density two

times the data density of the MFM mode (The unneceb sary clock pulse is eliminated using this method ) (Condition) Clock is written only when there is no data

The clock pulse (Ci will be eliminated in above illustra tion as there is no data preceding or following the clock Because the data rate is 2/Js for this method, it is possible to obtain twice the density of the FM method

6)Media recording format

Media is formatted according to the IBM format

For Double side media, data is written on the front side (head-1) and the reverse side (head-00)

NOTE Three types of write data cycl??- (2f ~>t"> SA*S) are used The read/write waveform is identical

to FM method

<[ t

I N D E X

\M

Start point

Hatched portion is a recording gap

I D

AM TT HH SS DL CRC CRC

ID section CRC check code

Size of data section

(00) H ??? 128 bytes

(01) H ??? 256 bytes

Sector number

Head number

(00) H -?? Head 0 (side 0)

(01) H -* Head 1 (side 1)

??? Track number

??? ID address mark which begins the ID section

7)Formatting

To write the above format (ID section, data section, gap) on an entire surface of a new floppy disk is called formatting

Note 1 Formatting may also be called initialization. The word "initialize" is also used as a software term to clear the data section or to partition data area. Keep the difference between formatting and initializing in mind.

Note 2 Unless formatting has been done on a properly adjusted floppy disk drive unit, an erroe may occur on another floppy disk drive unit

8)Data write procedure

Described next is the procedure to write data on the FD.

(1)The head is moved over the track to be written.

(2)The head is loaded

(3)ID section is read and repeated until the desired section is reached

(4)When the desired ID section is found, data is written on that area (DATA AM is also written )

(5)The data thus written is now checked if it was written correctly (read after write) The respective ID section is read while the media makes a full turn

51

DATA

AM DATA CRC CRC

'Data address mark

(or delete address mark)

NOTE The delete address mark

is written to indicate invalid data It is often written on

a new floppy disk as there are no valid data on it

(6)The sector of the identical ID is read and verified with the write data Because of thr pad dftei Ar.'e capability the possibility of an error in the written data is quite low

9)Data read procedure

Described next is the procedure to read data from the FD.

(1)The head is moved over the track tu -^ i ead

(2)The head is loaded

(3)The ID section is read and repeated until the desired sector is reached

(4)When the identical IDsection is found, the <~i-m IP that data section is then read

MZ3500

UPD765 signal description

Function

+5V

Single phase, TTL level clock

Set the FDC into an idle state, and all drive unit interface outputs, except PSO, 1 , and WDATA (don't care), are set to low level In addition, INT and DRW outputs are set to low level DB goes into an input state.

Validates RD and WR signals

Bidirectional, tri-state data bus

Control signal to write data to the FDC via the data bus

Control signal to read data from the FDC via the data bus

The signal used to indicate a service request from the FDC It is issued at every byte in the non- DMA mode, or upon completion execution of a command in the DMA mode

The signal used to select the status register or data register of the FDC for access via the data bus. When 0, it selects the status register When 1. it selects the data register.

FDC to memory data transfer request signal in the DMA mode

The signal that indicates use of the DMA cycle During the DMA cycle, it functions identically toCS.

Drive unit select signal, with which up to four drive units can be selected.

The signal used to designate the operation mode of the VFO circuit When 0, the MFM mode is assigned. When 1, the FM mode is assigned

The signal used to designate the operation mode of the VFO circuit When 1, it permits reading operation. When 0, it prohibits reading operation

Signal used to discriminate the read/write signal from the seek signal that used for drive unit interfacing signal. When 0, it indicates RW When 1 , it indicates

Signal used to load the read/write head

Signal used to select head #0 and head #1 for the double-sided floppy disk drive unit. When 0, it selects head 0. When 1, it selects head 1.

When the RW/seek signal is operating as RW, the signal works as LCT which indicates that the read/write head is selecting the cylinder above 43. When the RW/SEEK is operating as SEEK, it works as DIR which indicate seek direction When 0. seek is made towards outer side

When 1, seek is made towards inner side

When the RW/SEEK signal functions as RW, it works as F LTR which resets any fault condition as the seek step signal.

Signal used to indicate that the drive unit is ready for operation

When the RW/SEEK signal is operating as RW, it function as WPRT which indicates that the drive unit or the floppy disk is write protected. When the RW/SEEK is function as the SEEK signal produces 2 SIDE which indicates that a double sided media is in use.

Signal to indicate the physical start point of the track.

When the RW/SEEK signal is operating as RW. it works as FLT which indicates that the drive unit is in a fault condition. When the RW/SEEK is operating as SEEK, it works as TRKO which indicates that the read/write head is on cylinder 0.

Signal used to indicate the termination of a read or write operation

Data written on the floppy disk consists of clock bits and data bits

Signal to indicate write enable to the drive unit

Data write timing signal which is 250kHz in the FM mode or 500kHz in the MFM mode

22WINDOW

'

MZ350C

Function

Signal used to either advance or delay the write data in writi ng under the MFM mode, to obtain tir rung adjustment for reading. The WDATA signal is controlled as shown in the table be ow

Read data from the drive unit consists of clock bits and data bits.

Signal created in the VFO circuit which is used to sample RDATA. Phase syncroni^i carried out in the FDC for RDATA data bits and WINDOW.

5-5. Data recording method

There are two ways of recording data; FM recording method and MFM recording method.

2)MFM recording method

(1)Data bit is placed in a middle of a bit cell.

(2)When the data bit is "0", a clock bit is placed before the current bit cell. (See Fig. 1)

1) MF recording method

(1)Clock bit indicates a bit cell.

(2)Data bit is placed in a middle of a bit cell. (See Fig. I.

As seen from the above illustration, bit density of the MFM recording method is twice the FM recording method. In other words, data density of the MFM recording method doubles that of the FM recording method. For the

Model 3500, only side 0 of track 0 (128 bytes/sector) is written in the FM mode and rest of other tracks are recorded in the MFM mode.

5-6. I/O port in the MFD interface

I/O port used in the MFD interface is as follows.

D-BUS I/O

IOMF#F9-AO OUT

D7

D6

D5

D4

OUT

D3

IOMF#F8-AO 1)2

1)1

DO

U2

Dl IN

DO

DACK

ME

SCTRL

TC

TRIG SEL3

SKI. 2 SEL1

SELO

M . ON

INDEX

DRQ

Used for data transfer between the CPU and the FDC.

INT from the FDC is output enabled on INTFD. FDD select signal output is enabled.

TC to FDC.

Trigger (motor on) of the timer (555) Selects FDD 3

Selects FDD 2

Selects FDD 1

Selects F D D O

ON/OFF state of the motor

INDEX signal from the motor

DRO from the FDC.

(Fig. 2)

(Table!)

WDATA-

8MHz

CLOCK

EARLY-

NOMAL-

LATE-

(Fig.3)

The precompensate circuit is used to compensate the peak shift before writing.

The FDC sends out the compensation rate to PSO and PS1 and the data bit location is shifted according to this signal. With issuance of WDATA. the value dependent on PSO and PS1 is set in the LS163. (See Table 1.) For instance, when both PSO and PS1 are low, it will set "1101 (D)" to the LS163, counted up by the 8MHz clock, and QB is sent out When it becomes "1110, 1111". When in EARLY (PSO= "H", PS1="L"), the value "1110(E)" will be set to the LS163 so that the output is issued 125ns earier than "not changed". The QB output, however, will be supplied for a period of two clock cycles.

5-9. Controls during read, write, seek, and re- calibrate

Above operations are all controlled via the FDC. 1) Control during read and write

I

2) Control during seek and recalibration

SEEK (or RECALB) command to FDC

I

HALT

(waits for interrupt) Read'result status from FDC.

In the case of the MFM method, need to trace cycle fluc- tuation is further increased, as a peak shift is apt to occur because there are three write data cycles.

(Peak shift). Data read cycles fluctuate as the flux change point is moved forwards or backwards.

{VFO circuit): Variable frequency oscillator

6.0 40 20 0 20 40 60

( a )

When the output waveform is observed after writing a single pluse on the floppy disk, the waveform show in (a) appears. Shown in (b) is two pluses of 4jis interval.

5-10. VFO circuit

1) Purpose

String of data

pulses from the FDD.

Data window

String of separate data

MZ 3500

Write pulse

Polarity inversion

Read waveform

Regenerated pulse H

C b )

Polarity inversion

(c)

Deviation in the peak point is called peak shift. Since pluse intervals of the MFD in actual operation are 4ns, 6/JS, and 8/^s, the largest shift takes place when a pluse appears 8/Js before or after 4/JS,as shown in (c).

n n

Data from the clock or data portion must be differentiated when read from the FDD. For this purpose a window pulse is used. In order to increase read tolerance, the VFO circuit carses the window to trace phase changes in the read data that take place during a floppy disk drive motor speed change.

MZ3500

A 4M

B ( Q A )

C ( Q B )

D ( Q C )

WINDOW

E

F

L

Normal O

P

F

L

Advanced

Q

O

P

L

K

Delayed

Q

O

P

FM mode timing chart

1 1

2

,??? ^

UJ

s

..

5

S3

OS

UJ

H

.

^

o o O o 0 O

c o

(O

0

"c ???

CO

0

/

/

0

0

\\\\

/

/

o

-

t-

Q

-

^_t

u

TT

O

CTJ

U.

o

1

c o c o o

~

Q

0

I o

-

c-

o D o -

Q

U

00

(J

-

W

w

T??? 1

U,

CO

Q

-

to

U, U,

U- U.

a.s

5

"o s

u

ro

"O Q. J2

(U

??I 2

<u 00

????? of O "S'o

"*" 1C *"

i."6

6 O 4J

iui^

<u J: r "??

- ^J O o 2 r~ <??? >??-

02 - H h

H a

Q

CL

???

o

*#-

.2

73

QJ

L-i

O

O O

1 ?? O O

CD" ca cc

Csl m

8

?? U3

U

lO

10

UJ

0)

2

?????? , ^

I Fail name (8 bytes) Expander Volume name

cc M A,r,Ar . .4 (3 bytes) (8 bytes) FF No ALOAD command

80 File specification only

01 With operand

Drive NO

All "F" when ALOAD command

is not on

ALOAD

Status line No label (8 bytes)

(Sbytes)

Contents of X register

When used for the line number (when line No 1 23) These three bytes are in effect

34 35 36 3b>tesfj$!l

00 01 23

When used for a label (Wight bytes are in effect a n d r e s e a r e )

343C

I

39 B148 B149 B150 B151

2Kx 152 = 304K

Each track is blocked in the following manner:

I

38B72 B73

39B74 B75

2KX 76=152K

Input/output format

No of channels

Code used

Baud rate

Transmission system

Synchronization method

Communication control procedure

Data format

LSI used

RS-232C bit serial input/output

1 channel

JIS 7-channel/JIS 8 channel

110 to 9600 bits/sec

Half-duplex

Start-stop

Non-procedure

Stop bif 1/1.5/2, with or without even or odd parity.

8251 AC or8253C-5

(Programmable interval Timer)

8-bit

with parity

8-bit, without parity

Example: 7-bits, even parity, 1 stop bit

Stop bit of precedingdata

Stop bit

Parity bit Stop bit (1 or 2 bits)

,

Y

Stop bit (1 or 2 bit

Stop bit

MZ3500

6-3. Block diagram of the interface

6-4. System switch functions

ON

SW5 Causes an error when the ER signal is low or open during data output.

SW6 Always high when power is on to the main unit.

SW7 Causes on error when the PO signal is high during data output.

OFF

ER signal is disabled.

The CD signal is set high while data output, but would not be set high when the echo-back function is selected for the host computer.

Polarity is inverted.

6-5. 8251AC controls

There are two control words for the 8251AC.

(1)Mode instruction: Defining general operational para- meters, such as unit, stop bit, etc.

(2)Command instruction: Defining status words used for actual operation, such assend/receive enable, etc.

1)Definition of generation operational parameters

???Baud rate

???Character size

???Even/odd/off parity assignment

??????Stop bit size

"Corresponds to channel command of BASIC.

c START

8251AC internal reset

8251AC mode instruction

Set counter (200ms)

Stop

Output data to 8251AC

ERROR 101

The 8251 send data when CTS goes low. The 8251 AC would not output, unlessv

ERROR 101

6-6. 8253 Controls

Baud rate of this interface will be determined by the clock output of the 8253. The 8251 is configured such that its baud rate is 1/16 of the input clock and has the following relation between the 8253 output clock and the baud rate:

8253 input frequency: 2457.6kHz

8253 Mode set: Mode 3(rec'angle waveform rategenerator)

2)UPD8253C-5 (Programmable Interval Timer)

The UPD8253-5 is a programmable counter/timer speci- fically designed for the 8-bit microcomputer system. It consists of three sets of 16-bit counters that operate under a maximum counter rate of 4MHz. Timer and six operational modes are programmed to be used for a wide range of microcomputer system timing control.

Features

???Z-80 compatible

???Three sets of 16-bit counters

???DC-4MHz of count rate

???Programmable six operational modes and timer duration

???Choice of binary counter/BCD counter

???N-channel MOS, input/output TTLcompatible

???Single +5Vsupply, 24-pin DIP

???Intel 8253-5 compatible

Pin configuration (Top View)

.VCC

Block diagram

8 2 5 1

8253

INTO TO MAIN FROM SUB

INT TO SUB FROM KEY

STK= (L)

M 2 3500

READY

CS

PO (MPER SUT), ER

CD

RD

OUT 0 of 8253

SD

To 3iil>CPU of

8253 OUT

v DS6

^ DS7

*2,4,6,... 28areGND.

*Ahnwp nin numbers are of the model-3

Function

Data is transfered to printer when STROB is high.

Data output to the printer

7-3. General description of the parallel interface

The 8255 is used for the LSI to control the parallel inter- face. The 8255 can be set in the following mode.

/PORT A: MODE 0

IPORTB: MODE 1

C:Output

74.Data transfer timing

BUSY

ACK

( 8255 A v PC-7J

DATA

STROBE

( M 1 N ) l^s(MIN)

Because it is not possible to directly it uses interrupt for key processing ACK signal is latched by means of

sense the ACK signal as and RS232C input, the the OBF pin function

M / 3500

7-6. I/O port map

8255 ON SUB CPU BUS

I N

OUT

8255

chip address(0011/xxxxj

Group A: Mode 1

Group B: Mode 0

INPUT P O R T C 7 4 L S 2 4 4

7 4 L S 2 4 4

port address[0100/xxxx]

IN

#4X

OUT

PA7

PA6

i'A5

I'A4

I'A3

PA2

PA1

PAO

PC7

PC6

PCS

PC4

PCS

PC 2

PCI

PCO

PB7

O PB6

3

PBS

PB4

PBS

PB2

PB1

PBO

C D S 7 D

C D S 6 D

CDS5D

C D S 4 3

CDS33

C D S 2 D

cosn

C D S O D

DATA8

DATA"

DATA6

I) AT A5

C2

Clock

Cl

CO

STRB

HLT KEY

STK -i

Keyboard

DK J

PUTR

PE Printer

BUSY

Reads the 8255 OBF (PC7) output or timer output.

Description

Holds 40-bit S/R

Data input/output

Data of the 40-bit S/R is preset to the time counter.

Data in the time counter is read to the 40-bit S/R.

8-2. Voice input/output circuit

Music output waveform

??? Tonal signal OUT1

???Sustain PC4

???2SC458 emitter

???2SC458u collector

???Speaker -Tlj output

??GETE1 J

PD8255

mmmil

1

8 4 System SW1 (DIP SW) (User operative through the cabinet bottom)

M 7 3500

No

1

2

3

4

5

6

7

8

9

10

Description

SW2 SW1

ON ON CE332P

OFF ON MZ1P02

ON OFF IO2824

OFF OFF

High resolution CRT (MZ1D02. MZ1D03)

Medium resolution CRT (MZ1D01, MZ1D06)

A period is output for a decimal point

A comma is outputted for a decimal point

Low state or open ER signal during data output will result in anerror

The signal ER becomes invalid

CD is high as long as power is on to the main unit

CD goes high only during data output However, it would not go high if the echo back function is on the host side

An error is cause when the PO signal is high during data output

Polarity is inverted for the above

Normally in capital letter, but in small letter when shifted

Normally small leter and in capital letter when shifted

3500 CG will be assigned when the 200 raster CRT is in use

2000 CG will be assigned when the 200 raster CRT is in use

#47 pin of MMR

??48 pin of MMR

#51 pin of MMR

#52 pin of MMR

ToCTS, DSR

of the 8251

ToCTS of the 8251

#54 pin of MMR (FDD

P/M signal (To A3 CG)

NC

WhenSH in use

When DH in use

???

???

Use of the CE330M as an expansion unit Use of the CE331M asan expansion unit Check mode *1

Check mode *2

X ><^ OFF OFF OFF

\(f Canbe in either state

???

Switches are set in this manner before shipment of machines this us the single-sided minifloppy disk drive.

Switches are set in this manner when the SH is used for the optional MFD

Switches are set in this manner when the DH is used for the optional MFD

Test mode *1

Test mode "2

Individual CPU PWB test

A. +5V and +12V supplies

1.Functions

a.Supply voltage is first rectified in the rectifier circuit and sent out to the switching regulator via the over- current detector provided in the overcurrent protect circuit.

b.Next, the voltage is converted to the +5/+12V output in the switching regulator and sent out to the noise

???Nfilter.

c. Change in the switching regulator output voltage is sensed by the control circuit and is fed back to the switching regulator after being amplified in the amplifier located in the control circuit, for maintaining the output voltage to a constant level.

d. The signal from the oscillator is supplied to the switch- ing regulator through the control circuit for driving the switching regulator.

e. For prevention of overcurrent, the protect circuit is used for stopping the oscillator when an overcurrent is met, and it makes the switching regulator to halt in order to shut off +12V/+5V supply.

2. Description of each block

a.Overcutrentprotect (control/protect) circuit

When an overcurrent is met in the +5V/+12V circuit, it causes to increase the voltage at both ends of the over- current detector resistor R1, which in turn causes to increase the Q3 collector current, for, there arises larger voltage difference between the emitter and base of the

transistor Q3. This makes the gate voltage of the thyns- tor increased owing to activation of SR. Witr, jctivation of SR it makes the oscillator voltage dropped to the GND level at the point "a" to stop oscillation, which also makes the switching regulator stopped by the de- activation of the transistor Q5 oscillation. This causes the transistor Q5 inactive, and it shuts off the +5V/

+ 12V supply,

b.Oscillation circuit

As the Q1 emitter voltage is at almost GND level whe- the transistor Q1 is active, the Q2 base voltage tem- porarily drops close to the GND level by means of C6, which in turn makes Q2 inactive and the Q2 emittei voltage increases.

Then, the Q2 base voltage comes to rise as C6 begins to be charged through R6, and the transistor Q2 starts to activate again. With activation of the transistor Q2, the Q2 emitter voltage starts to drop and the Q1 base voltage is temporarily dropped by means of C5, to shut off the transistor Ql, which causes to increase the transistor Q1 emitter voltage.

Next, as C5 is charged by R5, it makes the Q1 base voltage increased which puts the transistor Ql into activation. In this manner, transistors Q1 and O2 are alternately turned on and off to keep oscillating.

C5 and C6 are charged through R5 and R6 by on/off action of the Q1 and Q2, and discharged through Ql and

Q2.

1)Input Buffer Capacity: 64 bytes

???Key-in data is written to the input buffer first, and is supplied to the CPU, byte by byte.

???When an overflow is detected, the overflow code is affired to the key-in data already sent, before being sent to the CPU.

2)Rollover

???2 key rollover (exemption in the CTRL mode)

(Entry of the second key depression can be accepted even if more than one key is pressed at same time.)

???Simultaneous depression of more than three keys is ingnored.

3)Key bounce

15msec (Key spec is5-10msec)

(Indicates unstable state as shown in Fig. 3-2 that key signal does not turn off immediately after releasing of finger from the key.)

4)Key

5msec (norma), 20msec (max), 15msec (allows for key bounce)

5)DEF Key

Twenty definable keys are available in combination with the CTRL key.

[ DFK1-DFK10(DEF1A-DEF10A) DEF1-DFK10 in conjunction with the CTRL key

-- - (DEFIB-DEF10B)- (DEF1B-DBF10B)

6)Handling of functional symbols and graphic symbols See the code table.

7)Useof the CTRL key to discriminate RUN and CONT of the DEB key.

Push the DEB in conjunction with the CTRL key to start running.

8)Handling of special codes

COPY command: CTRL | 1 J (ten key) ESCape CTRL

BRKCTRL

9)PRO/OP

Sent to the CPU after power on and when PRO/OP is changed.

10)HOME key

CTRL [ HOME] Returns home after clearing the display screen.

[HOME] Only the cursor returns home.

12) Mode indication on LED

13)REP

Key repetition will take place when a key depressed for more than 0.64second. Entry of other keys is permitted during key repetition. When two keys are depresssd at the same time, an alternate key entry will not be accepted. This rule does not apply to simultaneous depression of more than three keys.

RET

DATA (1)

OUT

n n n n

n n n

MZ 3500

???Command flag: "0" when succeedeing 8 bits are akey data. "1" when it is a command or a graphic control data.

???Data: Positive logic (negative logic on thecable)

???Parity: Oddparity up to 27 bit from thecorrection flag.

???ST(K): D(K) strobe signal. Also use for Active H interrupt to the CPU.

???ACK(C): Acknowledge signal form the Active H

CPU. Also use for the data transfer interrupt disable signal.

??? D(C): Output data from the CPU. Positive logic

??? ST(C): D(C)strobe signal. Also use for Active L interrupt to the keyboard side.

3) Protocol

Key to sub CPU

???Keyboard to the sub-CPU data transfer tapes place with interrupt applied at every signal word (STK).

???As the sub-CPU detects a next strobe (STK) after going into the interrupt routine, it read data (K) as far as the final parity bit, and the ACK (C) signal is sent back to the keyboard side when the check-sum is correct.

???If the ACK (C) signal returns with normal timing, the keyboard controller accepts it. Unless the ACK signal was detected, the same data is sent again assuming a transmission error.

??? Case when the error data link (sub-CPU not enable to receive data properly) is established.

1)When parity error is found after the check-sum test.

2)When the sub-CPU is in execution of the NMI routine or when NMI is applied during data tranJ.jj,

3)When an error is detected in the couting of strobe (STK(K)) due to noise.

When one of above conditions is detected, data will be sent again until received correctly. Key entries during this periode are strobe in the key buffer. Should the key buffer overflow, key entry will not be stored in the key buffer.

???When a key buffer overflow is detected a KBOF error code is inserted in the area vacant immediately after

transmission of one key-in data, without clean '~ " key buffer contents.

SUB CPU TO KEYBOARD

???Basically the same as the above cases.

???Data is 3 bits plus parity bit.

???Return acknowledge pluse: Parity OK . .. STK + DK

Parity NO ... STKonly

D(K)

ST(K)

n__TL_n

D ( K )

Ji

n

Function

Output data signal from the sub CPU (D(O)

Internal clock oscillator crystal input

Internal clock oscillator crystal input

Processor initialize

+ 5V

Strove of D(C) that also is used for interrupt to the keyboard side (ST(O)

GND

NC

NC

NC

NC

RETURN signal from the keyboard is input when a key is pushed during key search

0V supply

Output data signal from key (D(K))

Strobe of D(K) which also is used for interrupt to the CPU side (ST(K))

Not used

NC

+ 5V

Strobe to the keyboard unit by which a hexadecimal code is sent out for generation shift pulses to terminals X O X 1 5 o f t h e 4 5 1 5 decorder during key search

NC

Pins used to activate the keytop embeded LED #32 pin Alphabets and symbols (LOCK) #33 and #34 are not used

Not used

Keyboard type identifier pin Keyboard type is identified by mears of KSO, KS1, KS2 of KUC1 an KUS2. whether it is GND or NC

Acknowledge input from the CPU (ACK(O) Sent only when the CPU receives a correct data

+ 5V supply

SIDE 1 (reverse side)

11-2. Sub-CPU side

block mut be traced by "FFH".

[Test items]

Memory, VRAM, GDC peripheral, clock, speaker, printer interface, light pen. and RS232C interface.

GO/NO GO of the test must be confirmed on the video screen. Moving from test to test is done by depressing the HALT key.

POSITION OFF ON ON

[Procedure]

(1)Turn OFF all dip switch of the 4 bits unit located in the middle of the front side of the board and turnOFF all dip switches of the 2 bits unit.

(2)Set the system dip switch levers (10 bits) located on the reverse side of the board to the foilowing positions.

ON ON OFF OFF ON ON ON

1) Memory test

Sub-IOCS RAM (4000H-5FFF) Shared RAM (2003H-23FFH) Shared RAM (2440H-27FFH) Above are tested.

[Display]

(1)Normal test ending

RA OK: SUB-IOCS RAM

RA OK

Shared RAM

RA OK

Above information are displayed on three display lines.

(2)Abnormal test ending

RA ER

3)CRT inter face test

Performance of the CRT is tested. To move into each test phase, push the HALT switch. Test No.1-No.8 test the 400-raster CRT, and test No.9-No.16 test the 200 rasters

CRT.

'Procedure and display] (TestNo.1)

Confirm all patterns on the display screen of 40 digits and 20 lines.

(Test No.2)

Confirm all patterns on the display screen of 80 digits and 25 lines.

(Test No.3)

(1)Confirm that an entire screen is Filled with "H".

(2)Confirm that attributes areshown asillustrated.

2)VRAM check

Proceed to test for ASCI! and atnbute VRAM [Display]

During test penode, display shows under following.

(1)Display reviced "U" for entire screen Irom top side.

(2)Display blinking "I'' with under! ne for entire screen.

(3)Display entire screen by space.

Test end

1.Normal

VR OK

2.Abnormal

VR ER

8

9

0

Vertical line

Horizontal line

Highlight

Blink

MZ3500

( Check No. 4 )

Border in black

!??? "H" in whi

Backroung in red

L "H" in blue

L "H" in green

[??? "H" in white

4) Speaker test

Performance of the speaker and the volume control are tested. Listen carefully to detect any abnormal sound or mulfunction. Adjust the volume control to a suitable listen- ing level.

5) Printer interface test

Performance of the printer interface signal lines and action of the 8255 are tested.

[Dispaly]

(1)Normal test ending

PR OK

(2)Abnormal test ending

PR ER

6)Light pen interface test

Performance of light pen interface signal lines and the action of the GDC are tested.

[Display]

On the upper left corner of the screen is displayed character and line.

(1)Normal test ending

LP OK

(2)Abnormal test ending

LP ER

7)RS232C interfacetest

Performance of RS232C interface signal lines and the action of the 8251 are tested.

[Display]

(1)Normal test ending

RS OK

(2)Abnormal test ending

RS ER

( Check No. 5 )

Kff

"H" inred

"H" in green

"H" in white

^n O_ 1 _ 5 c *^ O" 2

RCD

SDR O.7 29

3

It will need wiring connection as illustrated in the figure in order to test the RS232C interface. Pins of the RS232C interface edge connector must be wired in the following manner:

Front side

/*

7 5 3 1

MZ3500

SUB CPU CHECKER FLOW CHART 2/3

Sei th?? timer to 23 hourt. 59 minuiei. 58 **corxii

Oc*mb??r 3 III

Printer int M??c* tt??t

SUB CPU CHECKER FLOW CHART 3/3

11-3. Keyboard unit test functions

1)Keyboard controller ROM test

(1)After power on in a normal condition, it starts to carry out the ROMself-test.

If the alpha/symbol (LOCK) LED were to turn on, it indicates a failure in KBC. If not, KBC is satisfactory. t Key self check functional specification (simplified check)

2)Keyboard test

(1)As the power is turned on with the "DEB" in depres- sion, it goes into the keyboard self-test mode.

(2)Depress key in a given sequence. If key is depressed in a correct sequence, it makes the alpha/symbol (LOCK) LED activated each time a key is pushed.

If the key was pushed in a wrong sequence or when a failure is met in the key, it makes the LED blinked.-

(3)It returns to the normal mode upon completion of testing all keys. With this, the LED goes out.

(4)Observe the following key-in sequence to test.

i)Turn the OP/PRO siwtch to the OPside.

ii)Turn on power while pushing the "DEB" key.

iii)Turn the PO/PRO which to the PROside.

iv)Push a key one at a time in accordance with the given sequence.

ROM/RAM test S**ect memory location

SUM IPL START

Check MFD

Index itgnal

Contents of parameter sector

1.Kind of MFD

Single-side double-deneity or double side double dencity.

2.Track and sector where IOCS is stored, Loadi vj '. and Truch

Number of sectors

Note' The sub loader is contained m the leading sector.

YES

LOAD IOCS

SEEK& READ

Transfer the IOCS program to shared RAM

8000H~-??-F800H~ -

LOAD BOOT

LOAD BOOT

SSEK& READ

ret rys ^ ???

JUMP ^\

BOOT ADDRESS )

I/O SYSTEM

LOAD ERROR transfer

c HALT

CPU STOP

???SEEK, READ

ERROR

ERROR

BOOT: Program used to start the system.

Position of boostrap program on the media: Sector 2 thru 5 of Track 0.

ERROR

1

CBOOTERROR on disp.

*

122. SUB CPU IPL FLOW CHART

( POWER ON A

SUB CPU IPL J

T,m??,

1

In t,alize8255

A Mode 0.8 Mode 1.

C OUT

1

SUB CPU READY OFF

1

Rest GDC

1

Check ROM sum

Initialize GDC and check G VRAM

Set the custom LSI CSPI and

CSP2 control boards

Initialize GDCagatr

C-GDC, G-GDC command transfer

MZ-3500

IPL ROM is broke u indicated on display

13-18. PIN CONFIGURATION OF 1C & LSI

Mz-roo

74 LS 00

m R R R R R F1

LJ LJ U U U LJ U

IA IB \\ A H ^> ( M

m m

LJ LiJ LiJ LJ LL! LiJ LJ

1 Y IA IB 2Y 2A 2B C^D

74 LS 03

Vet +B 4A 4Y 3B 3A 3Y

LJ LJ LJ LJ LJ LJ LJ

IA IB 1Y 2A 2B 2Y GND

74 tS 04

6A 6Y SA^ 5Y 4A 4Y^

LJ LJ LJ LJ LJLJ LJ

IA IY 2A 2Y 1A 1Y CM>

74 IS 08

\tc 4B 4A 4Y 3B 3A IY

LJ LJTJLJ LJ LJ LJ

IA IB I Y 2A 2B 2Y GN1>

Vg 1C IY 3C 3B 3A 3Y

M R R R R R m

jTj UTJ LJ LJ LJ

IA IB 2A JB ^C 2Y CM>

PARAI IH if

sim i/ INIVT airuT ^~

Va I OAJ H UH (,

1C 1AI 2Y4 IA?? 'V3 IA3 'Y' IA4 2Y] CM

NtC K 1Y1

JjuJTUL??J I sITTTT' I I ej LH T??I

1C IA1 2Y4 1A2 2Y3 1A3 2Y2 lAi ZY] GND

LULU LD LJ LU LU LU LJ LU Lll

LJLJLJLiJLJLJLJLJLJL J

CLEAW 1Q ID 2V 2Q 3Q 3D 4Lt *Q GND

M 7. - 3500

171m nyi ryirTi n

UUU LJ U U LT

U U U LJ U U U

I 'K IK l> -A h "i < M

/^PDI 99OC

\l \-' 111 I ! IK H I I ! l\

m M M r^n R m

LU L^JHI L??J 111LlJ LJ

<. 2 l~l LO S 1 )t (_S |)| N IAD

T A 7 3 1 3

UPHc

17D \\7

16D \\8

D ws- 1 >

1.D \ < \M'C

D M} 'u i C f. 103 V. \\2C 7

K \M

14 D' "i

13D 1 <>2

12 3 1 03

H D 1 <>4

D??h10

64K 0 3 B

65HDD

66(.1 k

67K 0 4 B

68M P X

69(,M>

70C ASB

MZ-3500

li Exteriors

NO PARTS CODE

1C C A B C 1 0 0 7 A C Z Z

2G F T A F 1 0 0 1 A C Z Z

31 H B D G B 3 0 0 4 G E S A

4| T L A B Z 1 0 0 3 A C Z Z

!> T L A B Z 1 0 0 8 A C Z Z

6Q C N C W 1 0 0 8 A C 0 1

7Q P W B F 1 0 0 5 A C Z Z

8V H P G L 9 P R 2//- 1

9G C A B A 1 0 0 3 A C Z Z

10G F T A U 1 0 0 5 A C Z Z

11P S P A G 1 0 0 4 A C Z Z

12T L A B Z 1 0 1 7 A C Z Z

16X B P S F 3 0 P 0 6 K O O O U N T - 1 0 1 8 A C Z Z

D U N T - 1 0 3 5 A C Z Z

18G C A B B 1 0 0 4 A C Z Z

19G C O V H 1 0 0 1 A C Z Z

20L A N G T 1 0 0 3 A C Z Z

21L A N G T 1 0 1 0 A C Z Z

22L C H S M 1 0 0 8 A C Z Z

23L X - l Z 6 0 2 3 R C Z Z

24N F A N P 1 0 0 1 A C Z Z

25R M E M R 1 0 0 2 A C Z Z

26G L E G P 0 0 1 0 U C Z Z

27X B P S D 3 0 P 0 8 K S O

28X B P S D 4 0 P 0 6 K S O

29L X-B Z 1 0 0 1 ACZ Z

30X B P S D 4 0 P 0 6 K O O

31X B T S C 4 0 P 0 6 0 0 0

32X B T S F 4 0 P 0 8 0 0 0

33X C P S D 4 0 P 1 2 0 0 0

34P H O G - 1 0 0 1 A C Z Z

35G F T A F 1 0 0 2 A C Z Z

36L H L D W 6 6 5 5 R C Z Z

37Q L U G L 0 0 0 6 U C Z Z

38X B P S D 3 0 P 3 0 K S O

39VR S-PT 3 L B3 3 0 J

40L H L D W 6 6 5 5 R C Z Z P S L D M 1 0 0 3 A C Z Z T L A B Z 1 4 0 0 C C Z Z

D E S C R I P T I O N

series series

1

1

[2] PWB & Fixing angles

8X B P S D 3 0 P 0 6 K O O A A D U N T K 1 0 8 2 A C Z Z

**

9D U N T K 0 8 3 A C Z Z

**

(1-22)--

NC Fixing angle for speaker C Connector

NB HALT switch

B Variable resistor C Speaker

C Screw

E CPU PWB unit (Model 3541)

NC Connector for CRT ???2 C Screw

C Screw

NC Insulator for MFD C Connector

NC Connector (18pm) C Screw

C Screw

13. Connector

NO PARTS CODE

11 O C N C P 6 0 4 1 Q C Z Z T Q C N C P 4 8 4 1 Q C Z Z

3Q C N C W 1 0 0 1 A C Z Z

4Q C N C M 1 0 0 4 A C Z Z

6 QC N W- 1 0 0 7 AC Z Z 9 QCN CWO 2 0 7 HC Z Z

10Q C N C M 1 0 0 9 A C Z H

11QCNCM 1 0 0 9 A C Z i

12Q C N C M 1 0 0 9 A C Z B

13Q C N C M 1 0 0 9 A C Z G

14Q C N C M 1 0 0 9 A C Z E

1&1 Q C N C W 1 0 0 8 AC 0 1

17QC NCW 1 0 0 8 AC 0 2

18QC NW??? 1 0 4 7 AC Z Z

19QC NW??? 1 0 4 4 AC Z Z

20Q C N W - 1 0 0 4 A C Z Z

21QCNW - 1 0 0 3 ACZ Z

26L H L D F 6 6 4 8 R C Z Z

18

M2-3500

D E S C R I P T I O N

MZ-3500

[41 Others

CPU PWB

BDipSW

BDip SW

BDipSW

CCapacitor

B X-Tal (3932MHz)

B X-Tal (32MHz)

BX-Tal (245MHz)

BX-Tal (32KHz)

CBlock resistor (1/8W 33KOX4)

CBlock resistor (1/8W 68KOX4)

BBlock resistor (33KQX 8 1/8W??10%)

ABattery

CCapacitor (50V 10PF)

CCapacitor (50WV 33PF)

CCapacitor (50V 47PF)

CCapacitor (16WV 10,, F)

CCapacitor (16WV lOO^F)

CCapacitor (16WV 33WF)

CCapacitor (25WV 10j.F)

CCapacitor (25WV 100,uF)

CCapacitor (25WV 220,/F)

CCapacitor (50WV 1 O^F)

CCapacitor (50WV 33^F)

CCapacitor (50WV 4 7^F)

CCapacitor (50WV 680PF)

CCapacitor (50WV 680PF)

CCapacitor (50WV 220PF)

CCapacitor (50WV 560PF)

CCapacitor (12WV 0 10,, F)

CCapacitor (12WV OlO^F)

CCapacitor (25WV OOIO^F)

B Diode (1S1588L1)

B 1C

B 1C

B 1C

B 1C

B 1C

B 1C

B 1C

B 1C

B 1C

B 1C

B 1C

B 1C

B 1C

B 1C

B 1C

B 1C

B 1C

B 1C

B 1C

B 1C

NO. PARTS CODE

1L B N D J 0 0 0 9 F C Z Z

2S P A K A 1 0 1 6 A C Z Z

3S P A K C 1 0 8 2 A C Z Z 4 T i N S J 1 0 0 9 A C Z Z

5T i N S M 1 0 1 7 A C Z Z

6Q S O C Z 6 4 1 6 A C Z Z

7V C E A A A 1 C W 4 7 6 M

8V C T Y P A 1 N X 1 0 4 M

9V H i M 7 4 L S 3 6 7 - l

10V H i S N 7 4 1 5 7 / ??? 1

11 V H i 4 1 6 4 ??? 1 5 0 - H

12V RD - R V 2 E Y 1 0 1 J

13D U N T K 1 0 2 8 A C Z Z

D E S C R I P T I O N

1

j

I n d e x

MZ-3500

PARTS CODE [C]

C C A B C 1 007ACZZ

[D]

DUNT-1 0 18ACZZ DUNT-1 035ACZZ DUNTK 10 2 5ACZZ DUNTK 102 8ACZZ DUNTK 1 060ACZZ DUNTK 1064 ACZZ D U N T K 1 082ACZZ DUNTK 1083 ACZZ DUNTK1085ACZZ

[G]

GCABA 100 1ACZZ G C A B A l 003ACZZ GCABB1002ACZZ GCABB1004ACZZ GCOVH1 00 1ACZZ GFTAF1 001ACZZ G F T A F 1 002ACZZ G F T A R 1 0 0 3 A C Z Z GFTAR1004ACZZ GFTAU1005ACZZ GLEGG1001ACZZ

G L E G P O O 10UCZZ GLEGP1001CCZZ GSTN-100 1ACZZ

[H]

HBDG83004GESA

n

[J ]

JKNBM0004PAZZ

[L]

LANGK1007ACZZ L A N G Q l 004ACZZ

//

LANGQ1005ACZZ

//

LANGS1006ACZZ L A N G T 1 0 0 1 ACZZ L A N G T 1 002ACZZ LANGT1003ACZZ LANGT1008ACZZ LANGT1010ACZZ LBNDJ0009FCZZ LCHSM1008ACZZ LHLDF6648RCZZ

II

II

LHLDW6655RCZZ

//

LHLDZ1 00 1ACZZ L P L T P 1 0 0 1ACZZ LPLTP1072CCZZ LX-BZ1001 ACZZ LX-LZ6023RCZZ

[N]

N F A N P 1 0 0 1ACZZ

[P]

PCUSG1 00 1 ACZZ

H

H

PCUSU1003ACZZ PHOG-1 001ACZZ PHGG-1002ACZZ PSLDM1 001ACZZ PSLDM1003ACZZ PSLDP 100 1ACZZ PSPAG1 004ACZZ P S P A X 1 00 1ACZZ PZETY 100 1ACZZ

//

[Q]

QCNCMl 0 02 ACZZ

//

QCNCMl 004 ACZZ

//

QCNCMl 009ACZB

//

Q C N C M l 009ACZE

PARTS CODE

Q C N C M l 0 0 9 A C Z E Q C N C M l 0 0 9 A C Z G

//

Q C N C M l 0 0 9 A C Z H

//

//

Q C N C M 1 0 0 9 A C Z i

it

Q C N C M l 0 0 9 A C Z J Q C N C P 4 8 4 1 Q C Z Z

//

Q C N C P 6 0 4 1 Q C Z Z

it

Q C N C W 0 2 0 7 H C Z Z

//

Q C N C W 1 0 0 1 A C Z Z

ii

Q C N C W 1 0 0 6 A C Z Z Q C N C W 1 0 0 7 A C Z Z Q C N C W 1 0 0 8 A C O 1

//

Q C N C W 1 0 0 8 A C O 2

ii

QCNW-1 00 1 A C Z Z Q C N W - 1 0 0 2 A C Z Z QCNW-1 0 0 3 A C Z Z

//

Q C N W - 1 0 0 4 A C Z Z

II

Q C N W - 1 0 0 7 A C Z Z

//

//

QCNW-1 04 4 A C Z Z

//

QCNW-1 04 7 A C Z Z

//

Q L U G L 0 0 0 6 U C Z Z Q P I N - 2 0 0 5 S C Z Z QPWBF 1 0 0 5 A C Z Z Q S O C Z 6 4 1 4 A C Z Z Q S O C Z 6 4 1 6 A C Z Z

;/

//

Q S O C Z 6 4 2 4 A C Z Z Q S O C Z 6 4 2 8 A C Z Z Q S O C Z 6 4 4 0 A C Z Z

//

//

//

QSW-K 1 0 02 A C Z Z QSW-K 1 0 0 3 A C Z Z QSW - K1 0 0 4 A C Z Z QSW-K 1 0 0 5 A C Z Z QSW-K 1 00 7 A C Z Z Q S W - S 1 0 0 6 A C Z Z Q S W - Z 1 0 0 2 S C Z Z Q S W - Z 2 0 0 5 S C Z Z Q S W - Z 9 6 6 0 K C Z Z

[ R ]

RC-CZ 1 O O O Q C Z Z

u

H

R C - K Z 1 0 1 8 C C Z Z R C - S Z 2 0 0 1 H C Z Z R C R S - 1 0 0 1A C Z Z R C R S - 1 0 0 2 A C Z Z R C R S - 1 0 0 3 A C Z Z R C R S - 1 0 0 4 A C Z Z R C R S P 1 0 0 3 C C Z Z RMEMR 1 0 0 2 A C Z Z RMEMR 1 0 04 ACO 7 R M P T C 4 3 3 1 Q C K B R M P T C 4 3 3 3 Q C K B R M P T C 4 6 8 2 Q C K B R M P T C 8 3 3 3 Q C K B R M P T C 8 3 3 3 Q C K J R V R - A 5 4 5 2 Q C Z Z R V R - M C 3 2 1 Q C Z Z

I S]

S P A K A 1 0 0 3 A C Z Z

NO.

5- 6

3- 13

5- 7

3- 10

5- F*

9- 101

3- 11

5- 9

9- 102

3- 2

5- 10

3- 1

5- 11

3- 9

5- 3

3- 3

5- 4

9- 103

9- 104

1- 6

3- 16

2- 4

3- 17

9- 13

9- 14

2- 16

3- 21

2- 17

3- 20

2- 29

3- 6

8- 6

2- 19

3- 19

2- 18

3- 18 IT 37 8- 7 1- 7 5- 12 5- 13

10- 7

11- 6

5- 14

5- 15

5- 16

8- 8

9- 105

10- 8

9- 43

9- 43

9- 43

9- 43

2- 5

9- 9

5- 17

5- 18

5- 19

8- 9

9- 106

10- 9

5- 20

10- 10

5- 21

5- 22

5- 23

9- 107

5- 24

1- 25

4- 1

8- 10

5- 25

5- 26

5- 27

9- 108

2- 6

8- 11

4- 10

PRICE NEW PART

RANK MARK RANK

MZ-3500

PRICE NEW PART

PARTS CODE NO RANK MARK RANK

PARTS CODE

VH i HM4 7 2 1 1 4 - 1

VH i HM6 1 1 6P3 - 1

VHi L H 0 0 8 0 A/- 1 VH I M 5 K 4 1 1 6P-2 VH i M 5 8 7 25P - 1 5 V H i M 7 4 L S O 0/-1

//

V H i M 7 4 L S O 2/-1

//

VH iM7 4LS03/ - 1 VH IM74LS04/ - 1 VH . M74LS08/ - 1

//

VH I M 7 4 L S 1 0/-1

//

V H I M 7 4 L S 1 25-1 V H I M 7 4 L S 1 2 6 - 1 V H I M 7 4 L S 1 3 8 - 1 V H I M 7 4 L S 1 3 9 - 1 VH I M 7 4 L S 1 4/-1 V H i M 7 4 L S l 57-1

//

//

VHiM74LS161 - l V H i M 7 4 L S l 63-1 VH I M 7 4 L S 1 66-1

//

VH . M74LS21/ - 1 V H I M 7 4 L S 2 2 1 - 1

U B A T N l 001ACZZ UBNDA1 008CCZZ

[V]

VCCCPU1HH20 1J VCCCPU1HH680J

V C C S P U 1 H L 1 O D D

//

V C C S P U 1 H L 3 3 0J

//

V C C S P U 1 H L 4 7 0J

//

H

V C E A A A 1 C W 1 0 6 Q V C E A A A 1 C W 1 07M

II

V C E A A A 1 C W 3 3 6 M V C E A A A 1 C W 4 7 6 M V C E A A A 1 E W 1 0 6 M V C E A A A 1 E W 1 07M VCEAAA1EW227M V C E A A A 1 H W 1 0 5M V C E A A A 1 H W 2 25M V C E A A A 1 H W 3 3 5 M V C E A A A 1 H W 4 7 5 M V C E A A U 1 C W 1 07M V C E A A U 1 C W 3 3 6 M

//

V C E A A U 1 C W 4 7 5 M V C E A A U 1 E W 1 07M V C K Y P A 1 H B 3 3 IK V C K Y P A 1 H B 6 8 IK

H

V C K Y P U 1 H B 1 02K

//

V C K Y P U 1 H B 2 2 IK V C K Y P U 1 H B 5 6 1K V C S A T U 1 VE 1 04M V C T Y P A 1 N X 1 04M

V C T Y P U 1 EX 10 3M

//

//

V H D D S 1 58811-1

//

//

V H E R D 5 6E5/-1 VH iDB 7 4 9 H A C O 5

NA

D

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

B

B

B

B

N B

V H i M 7 4 L S 2 4 4 - l

//

V H I M 7 4 L S 2 4 5 - 1 VHiM74LS27/ - l V H i M 7 4 LS273 - 1

//

//

VH I M 7 4 L S 2 9 3 - 1 VH IM74LS32/-1

//

V H i M 7 4 L S 3 6 7 - l

//

//

V H I M 7 4 L S 3 7 3 - 1

II

VHiM74LS74/ - l

//

VH iM74LS75/ ??? 1 VH IM74LS86/ ??? 1 VH.M74LS93/-1 VH .M7438///-1 _^ VH .NE555///-1 VH i S N 7 4 04//-1 VH i S N 7 4 04N/-1

//

VH i SN7406N/-1

V H I SN 7 4 1 4 N/??? 1

VH i S N 7 4 1 57/-1 VH i S N 7 4 157N-1 VH I S N 7 5 188N-1 VH I S N 7 5 1 89A-1 V H i S P 6 1 0 2 C 0 0 2 VH i S P 6 1 0 2 C 0 0 3 VH i SP6 1 0 2 R O O 1 VH i T A 7 3 13AP-1 VH ITC4049P/ - 1

//

VH i T C 4 5 14P/-1 VH i TL4558//-1 V H i U P D l 9 9 0 A C C V H . U P D 7 2 2 0 D - 1

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VH i UPD7 6 5//-1 VH i UPD8255/ - 1 VH i 2764//AC0 1 VH i 2 7 6 4 / / A C 0 2

n

VH i 27 64//AC0 3

;/

VH i 2 7 64//AC0 4

//

PARTS CODE

VH i 4 1 64 - 1 50-H

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VH i 825 1 AC//-1 VH i 8253////-1 V H P G L 3 P R 2 / / - 1 VHPGL9PR2// - 1

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V R O - R V 2 E Y O O 0 J V R D - R V 2 E Y 1 0 1 J V R D - R V 2 E Y 6 8 2 J V R O - S T 2 E Y 100 J

H

V R D - S T 2 E Y 1 0 1J

//

//

//

V R D - S T 2 E Y 1 02 J

//

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NO

5- 89

11- 11

5- 90

5- 91

5- 92

1- 8

9- 6

5- 95

11- 12

5- 105

6- 77

6- 105

5- %

8- 45

9- 126

10- 27

5- 97

6- 78

6- 86

PRICE NEW

RANK MARK

AZ

A2

AY

BA f t

AC

AC '

AA

PART

RANK

B

B

B

B

B

B

B

C

C

C

C

C

C

C

C

C

C

C

C

PARTS CODE

VRD-SU2 E Y8 24 J VRN-RT2 EK 10 2F V R N - R T 2 E K 1 05F V R N - R T 2 EK 12 3F VRN-RT 2EK2 2 2F V R N - R T 2 E K 472F V R N - R T 2 E K 9 1 2F V R S - P T 3 A B 1 00 J

//

V R S - P T 3 A B 1 02 J V R S - P T 3 D B 1 02 J V R S - P T 3 D B 1 52K VRS - PT3DB680K VRS-PT3LB330 J VSP0080P-608N VS2SA673-C/-1 VS2SA673-D1-1 VS2SC4 58KC/-1

[X]

//

//

//

V R D - S T 2 E Y 1 03 J

//

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V R O - S T 2 E Y 1 04 J

//

V R O - S T 2 E Y 1 51 J V R D - S T 2 E Y 1 5 2 J

//

II

V R D - S T 2 E Y 1 82 J V R D - S T 2 E Y 2 2 0 J

//

V R D - S T 2 E Y 2 2 2 J

//

ii

H

V R O - S T 2 E Y 2 72 J V R D - S T 2 E Y 3 3 1J

//

//

//

//

//

//

//

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VRD ??? S T 2 E Y 3 3 2 J

H ii ti

V R D - S T 2 E Y 3 3 3 J

//

//

//

V R D - S T 2 E Y 3 9 0 J

//

V R D - S T 2 E Y 3 9 1 J V R D - S T 2 E Y 3 9 2 J V R D - S T 2 E Y 4 R 7 j V R D - S T 2 E Y 4 70 J V R D - S T 2 E Y 4 7 1J

n

V R D - S T 2 E Y 4 7 2 J

//

V R D - S T 2 E Y 5 6 1 J V R D - S T 2 E Y 6 8 1J

ii

II

H

V R D - S U 2 E Y 1 0 1J V R D - S U 2 E Y 1 5 2 J V R D - S U 2 E Y 3 9 1 j V R D - S U 2 E Y 4 7 0 J

//

V R D - S U 2 E Y 6 8 1J V R D - S U 2 E Y 8 2 1 J V R D - S U 2 E Y 8 2 2 J

//

6- 93

6- 97

6- 98

5- 98

9- 127

10- 28

5- 99

9- 128

6- 103

6- 72

6- 75

6- 91

6- 90

6- %

6- 114

5- 100

6- 92

6- 94

9- 129

6- 85

5- 93

5- 101

6- 83

6- 89

6- 99

6- 100

6- 106

8- 46

10- 29

5- 102

8- 47

9- 130

10- 30

5- 103

6- 73

6- 74

9- 131

6- 102

6- 113

6- 87

6- 115

6- 80

5- 94

6- 88

9- 132

6- 107

8- 48

5- 104

6- 95

6- 109

6- 110

9- 133

8- 49

5- 106

8- 50

5- 107

10- 31

5- 108

5- 109

5- 110

8- 51

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

C

c

[_

1

XBBSC26P04000

XBBSC30P06000

XBPSD30P06KSO

//

//

XBPSD3 O P O 6 K O O

//

XBPSD30P08KSO

XBPSD30P08000 XBPSD30P1 0000

II

XBPSD30P30KSO

XBPSD40P06KSO X B P S D 4 0 P 0 6 K O O XBPSD40P06000 XBPSD4 OP08KSO XBPSF3 O P 0 6 K O O XBTSC4 OP06000 XBTSD30P04000 XBTSF40P08000 XCPSD40P12000 XNESD30-24000

n

II

XUPSC26P06000

XUPSC30P08000

XUPSD26P06000

[0 1

O A E 1 0447 1 OO// O A E 1 0 4 4 7 1 13// OAE104803 87// O A E 1 0 5 0 0 6 23// O A E 1 0 5 0 4 9 1 7// O A E 1 0504933// O A E 1 0507778// OAE1050778 I//

OAE 105 184 8 2//

OAE 10526940//

O A E 1 052 798 I//

OAE 1053 1087// OAE 1 0538909// OAE 105389 1 2// O A E 1 0 5 4 3 4 8 6// O A E 2 0 4 9 0 4 4 5// OAE205 10574// O A E 2 0 5 1 2336/X O A E 2 0 5 2 1 194// OAE20527978// OAE22830579// OAE 2283 1688//

OAE 23 594 924//

O A E 3 0 1 0 9 0 6 6//

n

II n

OAE 30 1167 29//

u

O A E 3 0 1 2 0 4 56//

//

OAE 30 1 20524//

//

PARTS CODE

O A E 3 0 1 20524//

//

O A E 3 0 1206 5 O// O A E 3 0 1 2 1 8 6 6// O A E 3 0 1 2 1 9 2 1 / /

//

//

//

//

O A E 3 0 1 2 1 9 4 7// O A E 3 0 1 29460//

//

//

//

O A E 3 0 143284// O A E 3 0 1 4 3 5 7 2//

//

O A E 3 0 1 59870// O A E 3 0 164409//

//

O A E 3 0 16526 2// O A E 3 0 1 6 5 5 7 6//

//

O A E 3 0 1 67370//

O A E 3 0 1 69653/7

//

;/

O A E 3 0 17 0008//

//

O A E 3 0 1 95258/7 OAE30200774//

//

O A E 3 0 2 13525// O A E 3 0 2 169 0 4// O A E 3 0 2 2 1 5 1 7// OAE30221520// O A E 3 02 2 1 546// OAE30227236// OAE30250326// OAE30258784// O A E 3 0 2 6 1 658// O A E 3 0 2 6 3 0 2 5//

//

//

//

//

//

//

O A E 3 0 2 6 9 4 3 O// OAE30272391// OAE30279844// O A E 3 0 2 8 0 6 7 I// OAE30362052// OAE30362081// OAE30379029//

//

OAE30490940// O A E 3 049 11 69// O A E 3 0 4 9 9 8 3 I// OAE30500979// OAE30500982// O A E 3 0 5 0 1868// O A E 3 0 5 0 8 0 4 9// OAE30508528// O A E 3 0 5 0 8 5 3 I// OAE30508557// O A E 3 0 50856 O//

//

OAE30509721//

//

OAE30509941// O A E 3 0 5 1 13 53// O A E 3 0 5 154 6 9// O A E 3 0 5 2 3 3 7 O// O A E 3 0 564 740// O A E 3 0 5 6 6 3 5 3 / / O O P A 7 K F 0 9 5C// O O P A 7 K F 1 0 2B// 0 O P A 7 K F1 03B// O O P A 7 K F 1 0 4 B//

PRICE NEW PART

NO RANK MARK RANK