INTEGRATED CIRCUITS
PTN3501
Maintenance and control device
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DESCRIPTION
The PTN3501 is a general purpose maintenance and control device. It features an
The eight quasi bidirectional data pins can be independently assigned as inputs or outputs to monitor board level status or activate indicator devices such as LEDs.
The PTN3501 has six address pins allowing up to 64 devices to share the common two wire I2C software protocol serial data bus.
The PTN3501 supports live insertion to facilitate usage in removable cards on backplane systems.
The PTN3501 is an alternative to the functionally similar PTN3500 for systems where a high number of devices are required to share the same
PIN DESCRIPTION
ORDERING INFORMATION
FUNCTIONAL DIAGRAM
CHARACTERISTICS OF THE
The
Bit transfer
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A
One data bit is transferred during each clock phase. The data on the
SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (See Figure 3).
System configuration
A device generating a message is a ??transmitter??, a device receiving is the ??receiver??. The device that controls the message is the ??master?? and the devices which are controlled by the master are the
??slaves?? (see Figure 5).
SDA
SCL
SW00542
Figure 3. Bit transfer
Figure 4. Definition of start and stop conditions
SDA
SCL
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Figure 5. System configuration
Acknowledge (see Figure 6)
The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra acknowledge related clock pulse.
A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked
out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse, set??up and hold times must be taken into account.
A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition.
Figure 6. Acknowledgment on the
FUNCTIONAL DESCRIPTION
WRITE PULSE
DATA FROM
SHIFT REGISTER
RESET
READ PULSE
DATA TO
SHIFT REGISTER
100 ??A
D Q
FF
CI
S
VDD
P0 TO P7
VSS
TO INTERRUPT LOGIC
SW00788
Figure 7. Simplified schematic diagram of each I/O
Addressing
For addressing, see Figure 8.
Figure 8. PTN3501 slave addresses
Asynchronous Start
Following any Start condition on the bus, a minimum of 9 SCL clock cycles must be completed before a Stop condition can be issued. The device does not support a Stop or a repeated Start condition during this time period.
I/O OPERATIONS (see also Figure 7)
Each of the PTN3501's eight I/Os can be independently used as an input or output. Input I/O data is transferred from the port to the microcontroller by the READ mode (See Figure 10). Output data is transmitted to the port by the I/O WRITE mode (see Figure 9).
Figure 9. I/O WRITE mode (output)
Figure 10. I/O READ mode (input)
Interrupt (see Figs 11 and 12)
The PTN3501 provides an open drain output (INT) which can be fed to a corresponding input of the microcontroller. This gives these chips a type of master function which can initiate an action elsewhere in the system.
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time tiv the signal INT is valid.
Resetting and reactivating the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from or written to the port which has generated the interrupt.
Resetting occurs as follows:
???In the READ mode at the acknowledge bit after the rising edge of the SCL signal
???In the WRITE mode at the acknowledge bit after the
HIGH??to??LOW transition of the SCL signal
???Returning of the port data to its original setting. A second port state change will require an SCL rising clock edge to be captured as an INT event.
???Interrupts which occur during the acknowledge clock pulse may be lost (or very short) due to the resetting of the interrupt during this pulse.
Each change of the I/Os after resetting will be detected and, after the next rising clock edge, will be transmitted as INT. Reading from or writing to another device does not affect the interrupt circuit.
MICROCONTROLLER
INT
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Figure 11. Application of multiple PTN3501s with interrupt
Figure 12. Interrupt generated by a change of input to I/O P5
A
Figure 13. Transient
MEMORY OPERATIONS
Write operations
Write operations require an additional address field to indicate the memory address location to be written. The address field is eight bits long providing access to any one of the 256 words of memory. There are two types of write operations, byte write and page write.
Byte Write (see Figure 14)
To perform a byte write the start condition is followed by the memory slave address and the R/W bit set to 0. The PTN3501 will respond with an acknowledge and then consider the next eight bits sent as the word address and the eight bits after the word address as the data. The PTN3501 will issue an acknowledge after the receipt of both the word address and the data. To terminate the data transfer
the master issues the stop condition, initiating the internal write cycle to the non??volatile memory. Only write and read operations to the quasi??bidirectional I/Os are allowed during the internal write cycle.
Page Write (see Figure 15)
A page write is initiated in the same way as the byte write, if after sending the first word of data, the stop condition is not received the PTN3501 considers subsequent words as data. After each data word the PTN3501 responds with an acknowledge and the four least significant bits of the memory address field are incremented. Should the master not send a stop condition after 16 data words the address counter will return to its initial value and overwrite the data previously written. After the receipt of the stop condition the inputs will behave as with the byte write during the internal write cycle.
Figure 15. Page Write
Read operations
PTN3501 read operations are initiated in an identical manner to write operations with the exception that the memory slave address' R/W bit is set to a one. There are three types of read operations; current address, random and sequential.
Current Address Read (see Figure 16)
The PTN3501 contains an internal address counter that increments after each read or write access, as a result if the last word accessed was at address n then the address counter contains the address n+1.
When the PTN3501 receives its memory slave address with the
R/W bit set to one it issues an acknowledge and uses the next eight clocks to transmit the data contained at the address stored in the address counter. The master ceases the transmission by issuing the stop condition after the eighth bit. There is no ninth clock cycle for the acknowledge.
Random Read (see Figure 17)
The PTN3501's random read mode allows the address to be read from to be specified by the master. This is done by performing a dummy write to set the address counter to the location to be read.
The master must perform a byte write to the address location to be read, but instead of transmitting the data after receiving the acknowledge from the PTN3501 the master reissues the start condition and memory slave address with the R/W bit set to one. The PTN3501 will then transmit an acknowledge and use the next eight clock cycles to transmit the data contained in the addressed location. The master ceases the transmission by issuing the stop condition after the eighth bit, omitting the ninth clock cycle acknowledge.
Sequential Read (see Figure 18)
The PTN3501 sequential read is an extension of either the current address read or random read. If the master doesn't issue a stop condition after it has received the eighth data bit, but instead issues an acknowledge, the PTN3501 will increment the address counter and use the next eight cycles to transmit the data from that location. The master can continue this process to read the contents of the entire memory. Upon reaching address 255 the counter will return to address 0 and continue transmitting data until a stop condition is received. The master ceases the transmission by issuing the stop condition after the eighth bit, omitting the ninth clock cycle acknowledge.
Figure 18. Sequential Read
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied.
DC ELECTRICAL CHARACTERISTICS
Tamb = ??40_C to +85_C unless otherwise specified; VCC = 3.3 V
NOTE:
1. All the timing values are valid within the operating supply voltage and ambient temperature range and refer to VIL and VIH with an input
voltage swing of VSS to VDD.
SW00561
Figure 19.
NOTE:
1.tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. These parameters are guaranteed by design.
WRITE CYCLE LIMITS
NOTE:
1. tWR is the maximum time that the device requires to perform the internal write operation.
Write Cycle Timing
Figure 20.
SOLDERING
Introduction
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when
This text gives a very brief insight to a complex technology. A more
DIP
Soldering by dipping or by wave
The maximum permissible temperature of the solder is 260??C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds.
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the
Repairing soldered joints
Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300??C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400??C, contact may be up to 5 seconds.
SO and SSOP
Reflow soldering
Reflow soldering techniques are suitable for all SO and SSOP packages.
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the
Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300
seconds depending on heating method. Typical reflow temperatures range from 215 to 250??C.
Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45??C.
Wave soldering
Wave soldering is not recommended for SSOP packages. This is because of the likelihood of solder bridging due to
If wave soldering cannot be avoided, the following conditions must be observed:
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???The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end.
Even with these conditions, only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369??1) or SSOP20 (SOT266??1).
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.
Maximum permissible solder temperature is 260??C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150??C within 6 seconds. Typical dwell time is 4 seconds at 250??C.
A
Repairing soldered joints
Fix the component by first soldering two diagonally opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to
10 seconds at up to 300 ??C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320??C.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011.
Data sheet status
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Limiting values definition ?? Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information ?? Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support ?? These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes ?? Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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??? Copyright Philips Electronics North America Corporation 2001 All rights reserved. Printed in U.S.A.
Date of release:
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