Philips_Handheld_TV

Small signal combination IC for black/white TV

TDA8303

TDA8303A

FEATURES

???Video IF amplifier with synchronous demodulator

???Automatic gain control (AGC) detector suitable for negative modulation

???AGC tuner

???Automatic frequency control (AFC) circuit with sample-and-hold

???Video preamplifier

???Sound IF amplifier and demodulator

???DC volume control or separate supply for starting the horizontal oscillator

???Audio preamplifier

???Horizontal synchronization circuit with two control loops

???Vertical synchronization (divider system) and sawtooth generation with automatic amplitude adjustment for 50 and 60 Hz

???Transmitter identification (mute)

GENERAL DESCRIPTION

The TDA8303/TDA8303A combines all small signal functions (except the tuner) which are required for a monochrome television receiver. For a complete black and white receiver only the output stages for video, sound, horizontal and vertical deflection and a tuner have to be added.

The TDA8303 is for applications with npn tuners and the TDA8303A for pnp tuners.

FUNCTIONAL DESCRIPTION

Video IF ampli???er, demodulator and video ampli???er

Each of the three AC-coupled IF stages permits the omission of DC feedback and possesses a control range in excess of 20 dB. An additional advantage is the symmetry of the amplifier which results in a less critical application.

ORDERING INFORMATION

The IF amplifier is followed by a passive synchronous demodulator providing a regenerated carrier signal. This is limited by a logarithmic limiter circuit prior to its application to the demodulator. The limiter has a very low differential phase shift which results in good differential gain and phase figures.

The video amplifier also contains a white spot inverter and a noise clamp which limits interference pulses to a point below the peak sync level. This circuit is more effective than a noise inverter and results in an improved picture stability, with respect to interference.

AFC-circuit

The reference signal for the AFC circuit is obtained from the demodulator tuned circuit. In this way only one tuned circuit needs to be applied and only one adjustment has to be carried out. The disadvantage with this method is that the frequency spectrum of the signal fed to the detector is determined by the SAW filter characteristic. This spectrum is asymmetrical with respect to the picture carrier so that the AFC output voltage is dependent on the video signal.

To overcome this video frequency dependency of the AFC output, the demodulator output is followed by a sample-and-hold circuit which samples during the sync level of the signal. This means that only the carrier signal is available to the AFC and it will not be affected by the video information.

At very weak input signals the drive signal of the AFC circuit will contain substantial noise. This noise has an asymmetrical frequency spectrum causing an offset in the AFC output voltage. This effect can be minimized by applying a notch in the demodulator tuned circuit. The sample-and-hold circuit is followed by an amplifier with high output impedance, therefore the steepness of the of the AFC control voltage is dependent on the load impedance.

Note

1. SOT117-1; 1996 December 3.

Philips SemiconductorsPreliminary speci???cation

Notes to the quick reference data

1.Pin 11 has a double function. When during switch-on a current of 9 mA is supplied to this pin, it is used to start the horizontal oscillator. The main supply can then be obtained from the horizontal deflection stage. When no current is supplied to this pin it can be used as a volume control.

2.On set AGC.

3. The output signal is measured at f = 7.5 kHz and maximum volume control.

4.The minimum value is obtained by connecting a 1.8 k?? resistor and a 470 nF capacitor in series between the video output and pin 25. The slicing level can be varied by changing the value of this resistor (higher resistance value results in a larger value of the minimum sync pulse amplitude). The slicing level is independent of the video information.

PINNING

AGC circuit

The AGC circuit of the TDA8303/TDA8303A is a top-sync detector. The video signal coming from the video amplifier passes a 2nd order low-pass filter before it is compared with an internal reference level. The comparator stage is gated when the horizontal oscillator is synchronized with the video signal, such that interference pulses outside the gating time have no influence on the gain control.

Sound circuit

The sound quality of the TDA8303/TDA8303A compared with the predecessors has been improved at weak signal conditions. The improvement has been achieved by the new IF amplifier which is less sensitive for radiation from the sound IF amplifier and by change of the ground and supply connections in the IC. When out-of-sync condition is detected by the coincidence detector the sound output is muted. When no mute is required the minimum voltage level on pin 22 should be clamped to a high level of 5 V. At this level the gating of the AGC is switched off and the phase 1 detector has a high output current for reliable catching of a new transmitter.

Vertical synchronization

The TDA8303/TDA8303A embodies a synchronized divider system for generating the vertical sawtooth at pin 2 having several advantages and features such as:

???The vertical frequency is alignment free. The divider automatically adapts to a vertical frequency of 50 Hz or 60 Hz including automatic amplitude correction and its operating modes offer maximum interference/disturbance protection.

???A discriminator-window checks the accuracy of the vertical trigger pulse. Internally clock pulses are generated by doubling the line frequency. The divider operates in the 60 Hz mode when the trigger pulse appears before count 576, otherwise the 50 Hz mode will be active.

???The divider system operates with two different reset windows for maximum interference/disturbance protection. The windows are activated via an up/down counter. The counter increases its counter-value by 1 for each time the separated vertical sync pulse appears within the selected window, otherwise the counter value is decreased by 1.

Modes of operation

Large search window: divider ratio between 488 and 576.

This mode is valid for the following conditions:

???Divider is looking for a new transmitter

???Divider ratio found does not comply with the narrow window specification limits

???Up/down counter value of the divider system, operating in the narrow window mode, drops below count 10

Small signal combination IC for black/white TV

TDA8303

TDA8303A

Narrow window mode: divider ratio between 522 and 528 (60 Hz); or 622 and 628 (50 Hz).

???The divider system switches over to narrow window mode when the up/down counter has reached his maximum value of 15 approved vertical sync pulses

???When the divider operates in the narrow window mode and a vertical sync pulse is missing within the window, the divider is reset at the end of that window and the counter value is decreased by 1

???At a counter value below 10 the divider system switches over to the large window mode

???The divider system also generates an anti-top-flutter pulse which inhibits the phase 1 detector during the vertical sync pulse. The pulse width is dependent on the divider mode. For the large window mode the start is generated at the reset of the divider. In the narrow window mode the anti-top-flutter pulse starts at the beginning of the first equalizing pulse. The anti-top-flutter pulse ends at count 10 for the 50 Hz mode and count 12 for the 60 Hz mode

VCR switch

An extra time constant switch in the horizontal phase detector makes an external VCR switch redundant. The time constant is automatically switched depending on the signal strength of the IF input (pins 8/9) and the coincidence detector.

When a strong signal is detected (V8/9 > 2.2 mV) and the circuit is synchronized the time constant of the phase

detector is optimum for VCR playback, a fast time constant during the vertical retrace to correct head errors of the VCR and during scan a sufficient time constant to correct fluctuations of the horizontal sync

During weak signal and synchronized conditions the time constant is enlarged and the phase detector is gated. This

LIMITING VALUES

ensures a stable display which is not disturbed by the noise in the video signal. When the circuit is not synchronized the time constant is fast and not gated to ensure a short catching time.

Combination of DC volume control and start-up feature

Pin 11 of the IC can be used as a DC volume control or as a start-up feature of the horizontal oscillator/output circuit dependent on the application.

Volume control is achieved by connecting a 4.7 k?? potentiometer or a DC voltage of 0 to 3 V to pin 11. When a current of 9 mA is supplied to pin 11 the volume control is set to a fixed output signal level and the circuit will generate drive pulses for the horizontal deflection and the main supply can be derived from the deflection.

Application when external video signals require synchronization

The input to the sync separator is externally available via pin 25. For normal application the video output signal at pin 17 is AC-coupled to the sync separator input. It is possible to interrupt this connection and drive the sync separator from other sources.

When external signals are applied to the sync separator the connections between the two parts must be interrupted. This can be achieved by connecting pin 22 to ground, which results in the following conditions:

???AGC detector is not gated

???Mute circuit not active, sound channel remains switched on

???Phase detector 1 has an optimum time constant for external video sources and is not gated

In accordance with the Absolute Maximum System (IEC 134)

Philips SemiconductorsPreliminary speci???cation

2.On set AGC.

3.The input impedance has been chosen such that a SAW filter can be employed.

4.Measured with 0 dB = 450 ??V.

5.Measured at 10 mV RMS top sync input signal.

6.Projected zero point; i.e. with switched demodulator.

7.White 10% of the top sync amplitude.

8.Measured according to the test line illustrated by Fig.2. The differential gain is expressed as a percentage of the difference in peak amplitudes between the largest and smallest value relative to the subcarrier amplitude at blanking level. The differential phase is defined as the difference in degrees between the largest and smallest phase angle. The differential gain and phase are measured with a DSB signal.

9.This figure is valid for the complete video signal amplitude (peak white-to-black); see Fig.3. The non???linearity is expressed as a percentage of the maximum deviation of a luminance step from the mean step, with respect to the mean step.

10.The test set???up and input conditions are illustrated by Fig.4. The figures are measured at an input signal of 10 mV RMS.

11.Measured with a source impedance of 75??.

VO black-to-white

The signal-to-noise ratio = 20 log -----------------------------------------------------------

Vn (RMS) at B = 5 MHz

12.The sound circuit is measured (unless otherwise specified) with an input signal of V15 of 50 mV RMS, a carrier frequency of 5.5 MHz at a f of 27.5 kHz. The QL of the demodulator tuned circuit is 16 and the volume control is

Small signal combination IC for black/white TV

TDA8303

TDA8303A

connected to the supply. The reference circuit must be tuned in such a way that the output is symmetrical clipping at maximum volume.

13.The test set-up is illustrated by Fig.6. The AM rejection curve (typical) is illustrated by Fig.7.

14.The output signal is measured at a f = 7.5 kHz and maximum volume control.

15.The demodulator tuned circuit must be tuned at minimum distortion.

16.Weighted noise, measured in accordance with CCIR 468.

17.See also note 1. The volume can be controlled by using a potentiometer connected to ground (value 4.7 k??) or by means of a variable direct voltage. In the latter event the relatively low input impedance must be taken into account.

18.The AFC control voltage is obtained by multiplying the IF output signal (which is also used to drive the synchronous demodulator) with a reference carrier. This reference carrier is obtained from the demodulator tuned circuit via a 90 degree phase shift network.The IF output signal has an asymmetrical frequency spectrum with respect to the carrier frequency. To avoid problems due to this asymmetrical signal the AFC circuit is followed by a sample-and-hold circuit which samples during the sync level. As a result the AFC output voltage contains no video information. The specified control slope decreases when the AFC output is loaded with two resistors between the voltage supply and ground.

19.At very weak input signals the drive signal for the AFC circuit will have a high noise content. This noise input has an asymmetrical frequency spectrum which will cause an offset of the AFC output voltage. The characteristics given for

weak signals are measured with a SAW filter (OFW 1956) connected in front of the IC input signal such that the input signal of the IC is 150 ??V RMS.

20.The minimum value is obtained by connecting a 1.8 k?? resistor between pins 17 and 25. The slicing level can be varied by changing the value of this resistor (higher resistor value results in larger value of the minimum sync pulse amplitude). The slicing level is independent of the video information.

21.Frequency control is obtained by supplying a correction current to the oscillator RC network via a resistor connected between the phase 1 detector output and the oscillator network. The oscillator can be adjusted to the correct frequency by short circuiting the sync separator bias network (pin 25) to the voltage supply. To avoid the need of a VCR switch the time constant of the phase detector at strong input signals is sufficiently short to obtain a stable

picture during VCR playback. During the vertical retrace period the time constant is even shorter so that the head???errors of the VCR are compensated at the beginning of scan. During conditions of weak signal (information derived from the AGC circuit) the time constant is increased to obtain a better noise immunity.

22.This figure is valid for an external load impedance of 82 k?? between pin 28 and the phase adjustment potentiometer.

23.The functions in-sync/out-of-sync and transmitter identification have been combined on pin 22. The capacitor is charged during the sync pulse and discharged during the time difference between gating (6.5 ??s) and the sync pulse.

24.The vertical scan is synchronized by means of a divider system. Therefore no frequency adjustment is required for the ramp generator. The divider detects whether the incoming signal has a vertical frequency of 50 or 60 Hz and corrects the vertical amplitude.

25.These figures are based on test samples.

26.Measured at an input signal amplitude of 150 ??V RMS (pin 18).

Small signal combination IC for black/white TV

TDA8303

TDA8303A

38.9 MHz

34.5 MHz

3.2 dB

13.2 dB

30 dB

BLUE

Input signal conditions

SC = Sound carrier

CC = Chrominance carrier

PC = Picture carrier

All with respect to top sync level

gain setting adjusted for blue or yellow

MLA666

10 dB

13.2 dB

30 dB

MBC213

YELLOW

Fig.4 Test set-up intermodulation.

Small signal combination IC for black/white TV

TDA8303

TDA8303A

SOLDERING

Introduction

There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used.

This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our ???IC Package Databook??? (order code 9398 652 90011).

Soldering by dipping or by wave

The maximum permissible temperature of the solder is 260 ??C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds.

The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.

Repairing soldered joints

Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 ??C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 ??C, contact may be up to 5 seconds.

DEFINITIONS

Data sheet status

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the speci???cation is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speci???cation.

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.