7. Internal Memory

8. Bus Controller (BC)

8.13External Memory Space Access

8.13.116-bit Bus with Fixed Wait States, in Synchronous Mode

iii

8.13.216-bit Bus with Handshaking, in Synchronous Mode and in

8.13.316-bit Bus in Asynchronous Mode and in Address/Data

8.13.48-bit Bus with Fixed Wait States, in Synchronous Mode

8.13.58-bit Bus with Handshaking, in Synchronous Mode and in

8.13.68-bit Bus in Asynchronous Mode and in Address/Data

8.13.716-bit Bus with Fixed Wait States, in Synchronous Mode

8.13.816-bit Bus with Handshaking, in Synchronous Mode and

8.13.916-bit Bus in Asynchronous Mode and in Address/Data

8.13.108-bit Bus with Fixed Wait States, in Synchronous Mode

8.13.118-bit Bus with Handshaking, in Synchronous Mode and in

8.13.128-bit Bus in Asynchronous Mode and in Address/Data

9. Interrupt Controller

10. 8-bit Timers

iv

11. 16-bit Timers

12. Watchdog Timer

13. Serial Interface

v

14. A/D Converter

15. I/O Ports

vi

16. Internal Flash Memory

vii

List of Figures and Tables

List of Figures

1.General Specifications

2. CPU

3.Extension Instruction Specifications

4.Memory Modes

5.Operating Mode

6.Clock Generator

7.Internal Memory

8.Bus Controller (BC)

viii

ix

9.Interrupt Controller

x

10. 8-bit Timers

11. 16-bit Timers

xi

12. Watchdog Timer

13. Serial Interface

14. A/D Converter

xii

15. I/O Ports

16. Internal Flash Memory

xiii

17. Ordering Mask ROM

Appendix

xiv

List of Tables

1.General Specifications

2. CPU

3.Extension Instruction Specifications

4.Memory Modes

5.Operating Mode

6.Clock Generator

8.Bus Controller (BC)

9.Interrupt Controller

xv

10. 8-bit Timers

11. 16-bit Timers

12. Watchdog Timer

13. Serial Interface

14. A/D Converter

15. I/O Ports

xvi

16. Internal Flash Memory

xvii

General Specifications

1.1 Overview

The MN1030 Series is a 32-bit microcontroller that maintains the software assets of Matsushita Electronics' 16-bit MN102 Series of microcontrollers by offering ease of use and excellent cost-performance with a simple, high- performance architecture.

Built around a compact 32-bit CPU core with a basic instruction word length of one byte, the MN103001G (mask ROM version) includes ROM, RAM, a bus control circuit, interrupt control circuit, timers, a serial interface, A/D converter, and input/output ports in a 100-pin QFP. The MN1030F01K (flash memory version) is equipped with flash memory instead of mask ROM, has the same on-chip peripheral functions as the MN103001G, and has the same package and pin specifications. This microcontroller is ideal for multimedia devices, which must be able to process large volumes of data (for audio, stills, video, etc.), as well as for real-time control equipment that requires fast and precise control. When supplied with power supply voltage of 3.3 V, the MN103001G operates at 60 MHz and achieves performance of 60 MIPS.

1.2 Features

Low voltage, high-speed processing, low power consumption

???Minimum instruction execution time:

16.7ns (during 3.3 V internal 60 MHz operation *MN103001G) 25 ns (during 3.3 V internal 40 MHz operation *MN1030F01K)

???Power consumption (TYP.):

300 mW (during 3.3 V internal 60 MHz operation *MN103001G) 270 mW (during 3.3 V internal 40 MHz operation *MN1030F01K)

Compact and high-performance CPU core

???Simple and highly efficient instruction set

(Number of basic instructions: 46; number of extension instructions: 24; number of addressing modes: 6)

???Excellent coding efficiency with instructions that have a basic word length of one byte

???Load/store architecture with 5-stage pipeline organization provides fast instruction execution

???High-speed branch processing

???Supports linear address space of up to 4 GB (External extension 8 Mbytes x 4 = 32 Mbytes)

Extension operation functions

???Multiply-and-accumulate operation instructions (32 bits x 32 bits + 64 bits = 64 bits; throughput: 2 clocks)

???Saturation operation instructions

???Bit search instructions

???Swap instructions

Large on-chip memory

???128 Kbytes of on-chip ROM/256 Kbytes of flash memory

???8 Kbytes of on-chip RAM (for data storage)

Flexible clock control

???Self-excited/externally excited oscillation

???Maximum 60 MHz internal operation when a 15-MHz oscillator is connected or a 15-MHz clock is input (in the case of the MN103001G)

???Can switch between using PLL (programmable: multiply by four, multiply by two, multiply by one)/not using PLL (divide by two)

???Low power consumption mode

???HALT, STOP, SLEEP mode

1-2

General Specifications

High-speed/high-performance bus interface

???Can select either separate address/data buses or multiplex address/data bus

???Address: 24 bits/Data: 8/16 bits

???External memory space can be partitioned into four blocks

???Chip select signal output for each block

???Blocks 2 to 3 can be switched between fixed wait insertion or handshaking

???Blocks 0 to 3 can be switched between synchronous mode and asynchronous mode

???Blocks 1 and 2 can be used as DRAM space

???DRAM control circuit on chip

???Address multiplexing function

???Programmable RAS/CAS timing setting

???Refresh control

-CAS-before-RAS refresh support

-Programmable refresh interval

???High-speed page mode support

???One store buffer on chip

???Avoids time penalty when performing a store operation in an internal peripheral or an external device

Input/output interface

??? Supports 3.3 V, CMOS-level input/output interface

Wide variety of internal peripheral functions

???Interrupts

???38 sources

_____________

-External interrupts: 9 sources (IRQn (n=7 to 0) x 8, and NMIRQ x 1)

-Internal interrupts: 29 sources (timers: 18; Serial I/F: 8; WDT: 1; A/D: 1; system error: 1)

???Timers

???Twelve 8-bit timers (all are down-counters)

-Format: Reload timer

-Cascaded connection possible (permits use as 16- to 32-bit timers)

-Timer output possible (duty ratio; 1:1,12 outputs)

-PWM output possible (8 outputs)

-Internal clock source or external clock source can be selected

-Serial interface clock generation

-A/D converter start timing generation

???One 16-bit timer (up-counter)

-Internal clock source or external clock source can be selected

-Input capture function (rising edge, falling edge, or both edges can be selected)

-PWM generation functions

-2 compare and capture registers

???Three 16-bit timers (down-counter)

-Format: reload timer

-Internal clock source or external clock source can be selected

???One watchdog timer

???Serial interface

???UART/synchronous system/I2C (multipurpose) x 1 channel

???UART-serial interface x 1 channel (maximum bit rate: 230.4 kbit/s)

???Synchronous x 2 channels

???A/D converter

???10 bits: 4 inputs

-Automatic scanning possible (0 to 3 channels can be set)

1-3

General Specifications

???Input ports:

???4 (all multipurpose)

???Output ports:

???15 (all multipurpose)

???Input/output ports:

???53 (all multipurpose)

Flash microcontroller specifications

???Performance identical to that of a mask ROM product guaranteed

???Overwriting while on board possible through serial communications

???Batch/block erase possible

Block units 8 KB (multiple blocks can be selected simultaneously)

Package

???LQFP100-P-1414

1.3Block Diagram

Fig. 1-3-1 MN103001G Block Diagram

* The MN1030F01K (flash version) is equipped with 256 KB of flash memory instead of 128 KB of ROM.

1-4

General Specifications

1.4 Pin Description

1.4.1 Pin Assignments

The pin assignments are shown in Fig. 1-4-1 and Table 1-4-1.

Fig. 1-4-1 Pin Assignments Diagram

* "VDD2" in the case of the MN103001G, "VPP" in the case of the MN1030F01K.

1-5

General Specifications

??? Pins for which two or more names are shown are multipurpose pins.

* "VDD2" in the case of the MN103001G, "VPP" in the case of the MN1030F01K.

1-6

General Specifications

1.4.2 Pin Functions

Table 1-4-2 shows the function of each pin of this microcontroller.

Table 1-4-2 Pin Function Table (1/2)

1-7

General Specifications

Table 1-4-2 Pin Function Table (2/2)

Notes:

1.A number that is not enclosed in parentheses in the ???Number of pins??? column indicates the main pins, while a number enclosed in parentheses indicates multipurpose pins.

2.After the reset condition is released, maintain the NMIRQ pin at the high level until the initialization routine (which sets the stack pointer SP) is completed. If the NMIRQ pin is not used, connect it to VDD via a resistor.

1-8

CPU

2.1 Basic Specifications of CPU

2-2

CPU

2.2 Block Diagram

The block diagram for this microcontroller, focusing on the CPU, is shown below.

Bus contol block

Fig. 2-2-1 CPU Core Block Diagram

2-3

CPU

2.3 Programming Model

2.3.1 CPU Registers

???The register set is divided into data registers that are used for arithmetic operations, etc., address registers that are used for pointers, and a stack pointer. This arrangement contributes greatly to the improved performance of the internal architecture, through reduction of instruction code size, improved parallelism in pipeline processing, etc.

???This register enables programming in C and other high-level languages.

Fig. 2-3-1 CPU Registers

???The loop instruction register (LIR) and the loop address register (LAR) are used to provide high-speed execution of branch instructions. High-speed loop control is performed by loading the branch target instruction and following fetch address with the SETLB instruction and forming the loop using the Lcc instruction.

2-4

CPU

???Data Register (32-bit x 4)

This register can be used generally for all operations. Operations are performed with a 32-bit length and the data size is converted when sending data to and from the memory or by executing the EXTB or EXTH instructions. When loading data, 8-bit data is zero-extended to 32 bits and sent to the register. When storing data, the lower 8 bits of the register are sent to the memory. When handling the loaded 8-bit data as a signed integer, the data is sign-extended from 8 bits to 32 bits with the EXTB instruction. When loading data, 16-bit data is zero-extended to 32 bits and sent to the register. When storing data, the lower 16 bits of the register are sent to the memory. When handling the loaded 16-bit data as a signed integer, the data is sign-extended from 16 bits to 32 bits with the EXTH instruction.

???Address Register (32-bit x 4)

This register is used as an address pointer, and only instructions (addition, subtraction and comparison) for address calculation are supported.

The address register data is used for pointers, and data is normally sent to and from the memory with a 32-bit length.

???Stack Pointer (32-bit x 1)

This pointer designates the first address of the stack region.

???Program Counter (32-bit x 1)

This counter designates the address of the command being executed.

???Multiply/Divide Register (32-bit x 1)

This register is provided for multiply and divide instructions. It holds the upper 32 bits of 64-bit multiplication results for multiply instructions and the remainder (32 bits) for divide instructions. Also, the upper 32 bits of the dividend are loaded to this register before executing divide instructions.

???Processor Status Word (16-bit x 1)

This register indicates the CPU status, and contains the operation result flags and interrupt mask level, etc.

2-5

CPU

Z: Zero Flag

This flag is set when an operation result is all zeroes, and is cleared by any other result. This flag is also cleared by a reset.

N: Negative Flag

This flag is set if the MSB of an operation result is "1", and is cleared if the MSB is "0". This flag is also cleared by a reset.

C: Carry Flag

This flag is set when a carry or borrow to or from the MSB is generated in the course of executing an operation, and is cleared if no carry or borrow is generated. This flag is also cleared by a reset.

V: Overflow Flag

This flag is set when an overflow occurs in a signed value in the course of executing an operation, and is cleared if no overflow is generated. This flag is also cleared by a reset.

IM2 to IM0: Interrupt Mask

These bits indicate the CPU interrupt mask level. The three bits define the mask level from level 0 (000) to level 7 (111), with level 0 being the highest mask level. The CPU accepts only those interrupt requests of a level higher than the mask level indicated here.

When an interrupt is accepted, the IM bits are set to the priority level of that interrupt. Until the processing of the accepted interrupt is completed, the CPU does not accept interrupts with the same interrupt level or lower.

The interrupt mask level is set to level 0 (000) by a reset.

IE: Interrupt Enable

Setting this bit to ???1??? allows interrupts to be accepted.

Once the CPU accepts an interrupt request, the IE bit is cleared to "0" and further acceptance of interrupts is prohibited. Accordingly, the IE bit must be reset when processing nested interrupts. This bit is cleared when the system is reset.

S1 to S0: Software Bits

These are the software control bits for the operating system. These bits cannot be used by general user programs. These bits are cleared by a reset.

For details on changes of these flags, refer to the "Instruction Manual".

???Loop Instruction Register (32-bit x 1)

This register is provided for the branch instruction (Lcc), and is used to load branch target instructions with the SETLB instruction. This register works together with the Lcc instruction to enable high-speed loop control.

???Loop Address Register (32-bit x 1)

This register is provided for the branch instruction (Lcc), and is used to load following fetch addresses with the SETLB instruction.

2-6

CPU

2.3.2Control Registers

This microcontroller uses the memory-mapped-I/O method and allocates the peripheral circuit registers to the internal I/O space between addresses x'20000000 and x'3FFFFFFF.

The registers listed below are described in this section. For details on other control registers, refer to the respective sections that explain the various internal peripheral functions.

Table 2-3-1 List of Control Registers

2-7

CPU

Interrupt Vector Register (IVARn) (n = 0, 1, 2, 3, 4, 5, 6)

The interrupt vector register (IVAR0 to IVAR6) contains the lower 16 bits of the start address of the interrupt handler for interrupts of the level accepted by the CPU. IVAR0 corresponds to level 0 interrupts; in similar fashion, IVAR1 to IVAR6 correspond to levels 1 to 6, respectively. IVAR0 to IVAR6 are allocated to the internal I/O space between addresses x'20000000 to x'20000018, respectively.

The IVARn register should be accessed by halfwords (16 bits). Byte and word access is not supported. Note that the upper 16 bits of the start address of the level interrupt handler are fixed to x'4000.

Core's Internal Memory Control Register (MEMCTRC)

The core's internal memory control register (MEMCTRC) sets the number of waits for the memory mounted inside this microcontroller. This register is allocated to the internal I/O space at address x'20000020.

Writing these bits is prohibited, since operation is guaranteed only with the settings that are in place after a reset.

2-8

CPU

CPU Mode Register (CPUM)

The CPU mode register (CPUM) sets the clock operating mode for the CPU and peripheral blocks. This register is allocated to the internal I/O space at address x'20000040.

The various operating modes can be set by setting the bits as shown in the table below.

Oscillation control and operating mode control

The CPUM register should be accessed by halfwords (16 bits). Byte and word access is not supported.

If the CPUM register is accessed to make a transition to an operating mode of SLEEP/HALT/STOP during execution of a program in external memory, a branch instruction should not be located within the three instructions immediately following the CPUM register access instruction.

2-9

CPU

2.4 Instructions

2.4.1Addressing Modes

The 32-bit microcontroller is equipped with the following 6 addressing modes which are frequently used with compilers.

All 6 addressing modes of register direct, immediate value, register indirect, register indirect with displacement, absolute and register indirect with index can be used with data transfer group instructions.

The 2 addressing modes of register direct and immediate addressing can be used with register operation instructions. Register indirect with index addressing is an addressing mode used to efficiently access arrays and other data.

Table 2-4-1 Addressing Mode Types

When accessing data using the register indirect with displacement and register indirect with index modes, the base address (the contents of Am, An and SP) and the effective address must be located within the same address space. For details on memory spaces, refer to section 4.1, "Memory Mode Types and Selection."

2-10

CPU

2.4.2Data Types

Data types can be processed in the four types of bit, byte, halfword and word data. Byte data, halfword data and word data can be handled as signed and unsigned data. The sign bit is MSB.

The data in the memory must be aligned data. In other words, the two bits on the LSB side of addresses containing word data must be "00" (addresses which are a multiple of 4), and the LSB of addresses containing halfword data must be "0" (addresses which are a multiple of 2).

Byte and bit placement conforms with the Little Endian format. Therefore, the address of the byte data on the MSB side of halfword data is the LSB side byte data address + 1,and the address of the byte data on the MSB side of word data is the LSB side byte data address + 3. The bit number for bit data starts at 0 on the LSB and increases towards the MSB.

Fig. 2-4-1 Little Endian Format

2-11

CPU

2.4.3Instruction Set

The instruction set has a simple organization, and features the generation of compact and optimized code through a C compiler.

The instruction code size is reduced by making the basic instruction word length one byte. As a result, increases in the code size of the assembler program can be kept to a minimum even though the instruction set is simple, with data transfers to and from memory limited to load and store operations.

Table 2-4-3 Instruction Types (All 46 types and extension instructions)

2-12

CPU

Note:

Interrupts are prohibited and the bus is locked (occupied by the CPU) when executing BSET or BCLR, however, if a BSET or BCLR instruction is executed during program execution in external memory, a bus authority release due to an external bus request may be interposed between the data read and data write by the BSET or BCLR instruction. If the atomic bus cycles (i.e. bus lock) of the BSET or BCLR instruction need to be guaranteed in a system that uses multiple processors, either of the following measures should be taken.

1. A program in which a BSET or BCLR instruction is executed should be placed in internal memory.

_____

2. Designate the bus authority request pin (BR) as a general-purpose input port, and the bus authority release pin

_____

(BG) as a general-purpose output port, for instance, so that bus requests cannot be accepted during execution of a BSET or BCLR instruction.

2-13

CPU

2.5 Interrupts

2.5.1Overview of Interrupts

The most important key to real-time control is the ability to shift quickly to interrupt handler processing.

If an interrupt is generated during the execution of an instruction that requires multiple cycles for execution (multiplication or division instructions, for example), interrupt response is improved by aborting the execution of the instruction and immediately accepting the interrupt. After control returns from the interrupt processing program, the aborted instruction is re-executed.

In addition, by minimizing the resources saved to memory to just the 6 bytes of the PC and the PSW when an interrupt is generated, the speed of interrupt processing is improved, as is the flexibility of software control. Furthermore, fast response and optimal program allocation are possible by placing interrupt processing programs at different addresses for each interrupt level.

This microcontroller has the interrupts shown below. When any of these interrupts occurs, control is shifted to the appropriate processing program in accordance with the cause.

Fig. 2-5-1 shows an overview of the interrupt system. This microcontroller is equipped with 19 interrupt group control blocks outside the CPU, and controls the interrupts of each group separately. Each interrupt group control block can accept up to 4 interrupt requests. This allows the controller to support to 38 interrupt factors, providing it with high expandability and enabling flexible ASIC support.

Except for the reset interrupt, all interrupts from the timer and other peripheral circuits and external pin interrupts are registered in the interrupt group control blocks. Then, the interrupt requests which pass the interrupt priority level (level 0 to 6) set in the interrupt group control blocks are output to the CPU. Groups 0 is assigned to non- maskable interrupts only.

CPU

Interrupt controller (INTC)

Fig. 2-5-1 Overview of the Interrupt System

2-14

CPU

2.5.2Registers

[Flags in the PSW] (CPU)

Interrupt-related flags in the processor status word (PSW) include interrupt enable and interrupt mask level.

IE (Interrupt Enable) R/W

???This flag allows all interrupts to be accepted except for non-maskable interrupts and reset interrupts. Interrupts are allowed when IE = 1. IE = 0 when the system is reset.

???When an interrupt is accepted, IE is cleared (interrupt prohibited). Set IE when accepting nested interrupts within the interrupt handler.

IM2 to IM0 (Interrupt Mask Level) R/W

???This holds the current interrupt mask level. When IE = 1, CPU accepts interrupts with levels higher than IM2 to IM0. Level 0 (000) when the system is reset.

???The following table shows the relationship between mask levels and acceptable interrupt levels.

Table 2-5-1 Relationship between Mask Levels and Interrupt Levels that Can Be Accepted

[Interrupt Control Registers (GnICR)] R/W halfword/byte access

Interrupt control registers (GnICR: n = 0, 2 to 19) combine interrupt priority level, interrupt enable, interrupt request and interrupt detect fields into a single register in order to control CPU external peripheral interrupts. There are 19 interrupt control registers, one for each group, and they are located in the internal I/O space from x'34000100 to x'3400014C. Register G0ICR is dedicated for non-maskable interrupts, and G0ICR is called NMICR (from the least significant bit: external pin non-maskable interrupt, watchdog timer overflow interrupt, system error interrupt). Fig. 2-5-2 shows the interrupt control register (GnICR) configuration, and each field is described in detail as follows.

Fig. 2-5-2 Interrupt Control Register (GnICR)

2-15

CPU

LV2 to LV0 (Interrupt Priority Level) R/W

???This 3-bit field sets the interrupt priority level. When the interrupt priority level set in LV2 to LV0 is higher than the interrupt mask level set in IM2 to IM0 in the PSW (i.e., the value set in LV2 to LV0 is smaller than the value set in IM2 to IM0), interrupts in the corresponding interrupt group are enabled. All interrupts (max. 4) in the same interrupt group have the interrupt priority level specified by LV2 to LV0.

???When interrupt requests are asserted simultaneously from multiple interrupt groups, the group with the highest interrupt priority level is accepted. Also, when multiple interrupt groups are set to the same interrupt priority level, the interrupt from the group with the highest priority ranking (the interrupt group with the smallest group number) is accepted.

???All bits are cleared to "0" when the system is reset.

IE3 to IE0 (Interrupt Enable) R/W

???This field has up to 4 bits which specify interrupt approval. The IE3 to IE0 bits correspond to each interrupt factor (max. 4) in the interrupt group. Interrupts are enabled when the corresponding IE3 to IE0 bit is "1".

???Interrupt occurs when IR3 to IR0 and IE3 to IE0 are set.

???All bits are cleared to "0" when the system is reset.

IR3 to IR0 (Interrupt Request) R/W

???This field has up to 4 bits which register interrupt requests. The IR3 to IR0 bits correspond to each interrupt. After the interrupts are accepted, IR3 to IR0 should be cleared by the software during the interrupt handler.

???All bits are cleared to "0" when the system is reset.

???Conditions for setting and clearing IR3 to IR0 are listed below.

ID3 to ID0 (Interrupt Detect) R/W

???This field has up to 4 bits which contain the logical product of IE3 to IE0 and IR3 to IR0. When an interrupt allowed by IE3 to IE0 occurs, the bit corresponding to that interrupt goes to "1". This field is used to specify interrupts within groups during interrupt processing.

???Interrupt requests are canceled by writing the specified values in IR3 to IR0 and ID3 to ID0 and clearing the interrupt request field.

2-16

CPU

[Interrupt Accept Group Register (IAGR)] R halfword/byte access

During a register read, the interrupt accept group register (IAGR) indicates the smallest group number of the groups that are generating an interrupt of the interrupt levels accepted by the CPU, which are indicated by IM2 to IM0 of the PSW. This register is allocated to address x'34000200 in the internal I/O space. The GN4 to GN0 field (5 bits) corresponds to the interrupt group number. A branch destination of the interrupt program for each group can be found, for example, by referencing the contents of the address obtained by adding the interrupt accept group register value to the leading address of the interrupt vector table. The interrupt accept group register is a read only register, and writing cannot be performed. When there are no interrupt factors of the applicable interrupt level, IAGR becomes 0.

Accessing IAGR is meaningless during non-maskable interrupts.

Fig. 2-5-3 Interrupt Accept Group Register

[Interrupt Vector Address Register (IVARn)] R/W halfword access

The interrupt vector register (IVAR0 to IVAR6) contains the lower 16 bits of the start address of the interrupt handler for interrupts of the accepted level. This register is allocated between addresses x'20000000 to x'20000018 in the internal I/O space. The start address of interrupt levels 0 to 6 correspond to IVAR0 to IVAR6. When an interrupt occurs, control is transferred to the address which is comprised of the upper 16 bits (x'4000) and the lower 16 bits (IVARn). This register is undefined when the system is reset.

IVARn

Fig. 2-5-4 Interrupt Vector Address Register

2-17

CPU

2.5.3Interrupt Types

The three types of interrupts are listed below:

[Reset interrupt]

The reset interrupt is the interrupt with the highest priority level, and is generated by setting the RST pin to "L" level. As a result of the reset interrupt, the registers, etc., are initialized. When the RST pin goes to "H" level, the microcontroller waits until the oscillation of the internal clock stabilizes, and then begins executing program instructions starting from address x'40000000.

[Non-maskable Interrupts]

Non-maskable interrupts are accepted regardless of the PSW interrupt enable (IE) and interrupt mask level IM2 to IM0 values. These interrupts include external pin non-maskable interrupt, watchdog timer overflow interrupt and system error interrupt.

When a non-maskable interrupt is accepted, control transfers to an interrupt processing program located at x'40000008 or beyond.

The interrupt handler accesses NMICR to analyze the interrupt factor, performs interrupt processing, cancels the interrupt factor, and then returns to the normal program using the RTI instruction.

External pin non-maskable interrupt

External pin non-maskable interrupt is generated when the NMIRQ pin goes to "L" level. If an external pin non-maskable interrupt is generated, the external non-maskable interrupt request flag (NMIF) in the non- maskable interrupt control register (NMICR) is set to "1".

Watchdog timer overflow interrupt

Watchdog timer overflow interrupt occurs when the watchdog timer count operation control flag (WDCNE) in the watchdog timer control register (WDCTR) is "1" and the watchdog timer overflows. If a watchdog interrupt is generated, the watchdog timer overflow interrupt request flag (WDIF) in the non-maskable interrupt control register (NMICR) is set to "1".

System error interrupt

System error interrupt occurs when an unaligned memory access or an unimplemented instruction is executed or other fatal error occurs. If a system error interrupt is generated, the system error interrupt request flag (SYSEF) in the non-maskable interrupt control register (NMICR) is set to "1".

Note: Do not change the interrupt enable (IE) in PSW during non-maskable interrupt processing.

2-18

CPU

[Level interrupts]

Level interrupts are interrupts for which the interrupt level can be controlled through the interrupt enable (IE) and interrupt mask (IM2 to IM0) bits in the PSW. Level interrupts are interrupts from the interrupt group controllers external to the CPU (in other words, peripheral interrupts). There are 18 groups, or 35 interrupt factors.

Each interrupt group controller includes an interrupt control register (GnICR); the interrupt priority level can be set independently for each interrupt group. It is also possible to set the same interrupt priority level for different interrupt groups. If interrupts of the same priority level are generated simultaneously, the interrupts are accepted in the sequence set by the hardware (the lower the interrupt group number, the higher the priority).

When a level interrupt is accepted, the hardware causes the program to branch to an address with the upper 16 bits being "x'4000" and the lower 16 bits indicated by the interrupt vector address register IVARn corresponding to the interrupt level.

The interrupt handler accesses IAGR to analyze the interrupt group, accesses GnICR (n = 2 to 19) to analyze the interrupt factor, performs interrupt processing, cancels the interrupt factor, and then returns to the normal program using the RTI instruction.

2.5.4Interrupt Definition

When this microcontroller accepts an interrupt, first the sequences automatically processed by the hardware are executed. Then control transfers to interrupt handler by the software and the interrupt handler is started up.

The interrupt processing sequences are described below.

(Interrupt processing sequences executed by the hardware)

1.The PSW is saved to the stack (SP-8).

2.The PC (return address) is saved to the stack (SP-4).

3.The PSW is updated.

IE is cleared and the accepted interrupt level is set in IM2 to IM0. (IM2 to IM0 is undefined in case of non- maskable interrupts.)

4.The stack pointer is updated. (SP-8 ??? SP)

5.Control is transferred to the address corresponding to the accepted interrupt factor or the address comprised of the interrupt vector address register (IVARn).

When an interrupt other than a reset interrupt is accepted, control is transferred to the address corresponding to the interrupt factor or the address comprised of the interrupt vector address register. The processing listed below is then performed at the branch destination in order to judge the interrupt factor in further detail.

See "2.5.3 Interrupt Types" for processing reset interrupts.

(Note) In General, Branch instructions (JMP instruction, etc.) are placed at the branch destination for reset interrupts, then it branches to the initialization program.

2-19

CPU

(Example of pre-processing by the interrupt handler)

1.The registers are saved.

The saved registers are those used by the interrupt handler.

2.The interrupt group analysis is executed.

2.1The interrupt acknowledge sequence is executed.

Interrupt acknowledge consists of reading out the interrupt accept group register (IAGR) to obtain the group number of the interrupt group with the highest priority among the specified interrupt levels.

2.2The leading address of the interrupt handler for each level is generated.

2.3Control is transferred to the interrupt handler for each level.

3.When there are multiple factors within the same group, the interrupt control register (GnICR) is read out to designate the factor.

*In case of non-maskable interrupts, the factor is specified by accessing the NMICR directly without accessing the IAGR.

4.Control is transferred to the interrupt handler for each factor.

Note that because this microcontroller uses a store buffer when writing data via the bus controller, it is necessary, when releasing the interrupt factor, to read the appropriate register immediately after clearing the interrupt factor in order to wait for the factor in the GnICR to be cleared completely.

(Example of post-processing by the interrupt handler)

5.The registers are restored.

The restored registers are those saved by the pre-processing.

6.The RTI instruction is executed and control returns to the program before the interrupt.

Fig. 2-5-5 shows the interrupt sequence flow. (when not accepting nested interrupts)

The numbers in the figure correspond to the numbers of processing performed by the interrupt handler in the previous section.

Fig. 2-5-5 Interrupt Sequence Flow

2-20

CPU

An even higher interrupt response speed can be realized by assigning only one factor or only a few factors to a single interrupt level.

Fig. 2-5-6 shows the interrupt sequence flow when assigning one factor to each interrupt level.

Interrupt

handler

Fig. 2-5-6 Interrupt Sequence Flow

[Nested Interrupts]

When a level interrupt occurs, nested interrupts can be prohibited by clearing IE of the PSW. However, nested interrupts can be achieved even while processing level interrupts by setting IE to "1" during processing. However, in order for nested interrupts to occur, the interrupts must have a higher priority than interrupt mask level IM2 to IM0 of the PSW at that time. (The GnICR interrupt priority level LV2 to LV0 is smaller than the PSW interrupt mask level IM2 to IM0.)

When non-maskable interrupts occur, nesting of level interrupts and non-maskable interrupts is prohibited until the interrupt handler is finished by execution of the RTI instruction.

[Interrupt Acceptance Timing]

If an interrupt request occurs part-way through the execution of an instruction, even instructions which require multiple execution cycles such as multiply/divide and other instructions are aborted if possible and the interrupt is accepted. The aborted instruction is executed again after returning from interrupt processing. Aborting these instructions sets the interrupt acceptance prohibited interval to 11 cycles or less. (The maximum interrupt prohibited interval of 11 cycles occurs when saving or restoring all registers with the MOVM, CALL or RET instructions. This occurs only for special cases such as task context switching.)

2-21

CPU

[Stack Frame]

When an interrupt is accepted, a stack frame is allocated and the total 6 bytes of information in the PC and PSW are saved in order to return from the interrupt. However, since the transfer of data across the 32-bit boundary is prohibited, the SP value must constantly be set to a multiple of 4. Accordingly, a stack frame is allocated as shown in Fig. 2-5-7 so that the SP value is constantly set to a multiple of 4. Ultimately, an 8-byte area with a total of 6 bytes of information is saved.

Fig. 2-5-7 Stack Frame Configuration

2-22

Extension Instruction Specifications

3.1 Operation Extension Function

The MN1030 series 32-bit microcontrollers are provided with 32 extension instructions which can be defined by users. This allows the desired processing to be performed at high speed for each model expansion by assigning multiply, multiply-accumulate, saturation and other application-oriented operations to extension instructions and connecting extension function unit via the extension operation interface of the CPU core.

Extension instructions include instructions UDF00 to UDF15 which transfer register or immediate values to the extension function unit and load the operation results to the data register, and instructions UDF20 to UDF35 which only transfer register to the extension function unit. Processing which performs user-defined operations is assigned to instructions UDF00 to UDF15, and processing which only transfers data to the extension function unit is assigned to instructions UDF20 to UDF35. Extension operations which require three or more inputs can be realized by transferring the input data to the extension function unit beforehand using instructions UDF20 to UDF35 and then performing the operation using instructions UDF00 to UDF15.

The block diagram showing extension function unit connected to the CPU for this series is as follows.

This microcontroller has a 32 x 16 multiplier, priority encoder, and saturation compensation unit on chip. The extension functions that use the extension function unit are explained in section 3.2, "Extension Instructions."

Fig. 3-1-1 Block Diagram of the Extension Function Unit

3-2

Extension Instruction Specifications

3.2 Extension Instructions

3.2.1Explanation of Notations

The notations used to describe instruction manual are shown below.

Notations used to express flag changes are listed below.

("Flag" is the general term used to refer to the lower 4 bits (V, C, N, Z) in the PSW.)

0:Reset

1:Set

3-3

Extension Instruction Specifications

3.2.2 Extension Block Register Set

The extension block has the following dedicated registers in which it stores the results of high-speed multiplication operations and multiply-and-accumulate operations.

Fig. 3-2-1 Extension Block Register Set

??? Multiply register (32 bits x 1 register)

This register is provided for high-speed multiplication instructions. A multiplication instruction uses this register to store the high-order 32 bits of the 64-bit multiplication result.

??? Multiply-and-accumulate register (higher) (32 bits x 1 register)

This register is provided for multiply-and-accumulate operation instructions. A multiply-and-accumulate operation instruction uses this register to store the high-order 32 bits of the 64-bit multiply-and-accumulate operation result.

??? Multiply-and-accumulate register (lower) (32 bits x 1 register)

This register is provided for multiply-and-accumulate operation instructions. A multiply-and-accumulate operation instruction uses this register to store the low-order 32 bits of the 64-bit multiply-and-accumulate operation result.

??? Multiply-and-accumulate overflow detect flag register (1 bit x 1 register)

This one-bit register is set when an overflow occurs in a multiply-and-accumulate operation. This flag is not cleared until the next CLRMAC instruction or PUTCX instruction is executed.

3-4

Extension Instruction Specifications

3.2.3Extension Instruction Details

PUTX (Register transfer instruction for high-speed multiplication: Load)

[Instruction Format (Macro Name)]

PUTX Dm

[Assembler Mnemonic]

udf20 Dm, Dm

[Operation]

The contents of Dm are transferred to the high-speed multiply register MDRQ.

[Flag Changes]

[Programming Cautions]

When "udf20 Dm, Dn" is operated, Dn is ignored.

3-5

Extension Instruction Specifications

PUTCX (Register transfer instruction for multiply-and-accumulate operation: Load)

[Instruction Format (Macro Name)]

PUTCX Dm, Dn

[Assembler Mnemonic]

udf21 Dm, Dn

[Operation]

This instruction transfers the contents of Dm to the multiply-and-accumulate register MCRH. This instruction also transfers the contents of Dn to the multiply-and-accumulate register MCRL. The contents of the V flag are set in the multiply-and-accumulate overflow detect register MCVF.

[Flag Changes]

3-6

Extension Instruction Specifications

GETX (Register transfer instruction for high-speed multiplication: Store)

[Instruction Format (Macro Name)]

GETX Dn

[Assembler Mnemonic]

udf15 Dn, Dn

[Operation]

The contents of the high-speed multiply register MDRQ are transferred to Dn.

[Flag Changes]

[Programming Cautions]

There is a one-instruction delay in the updating of the PSW to reflect flag changes.

However, the Bcc and Lcc instructions can evaluate the flags without waiting for the flag changes to be reflected in the PSW.

When "udf15 Dm, Dn" is operated, Dm is ignored.

The operations of "udf15 imm8, Dn", "udf15 imm16, Dn" and "udf15 imm32, Dn" are not assured. In addition, a system error interrupt does not occur in these cases.

3-7

Extension Instruction Specifications

GETCHX (Register high-order 32-bit transfer instruction for multiply-and-accumulate operation: Store)

[Instruction Format (Macro Name)]

GETCHX Dn

[Assembler Mnemonic]

udf12 Dn, Dn

[Operation]

This instruction transfers the contents of the multiply-and-accumulate register MCRH to Dn. The content of the multiply-and-accumulate overflow detect register MCVF is set in the V flag.

[Flag Changes]

When multiply-and-accumulate operation overflow was not detected (MCVF = 0)

When multiply-and-accumulate operation overflow was detected (MCVF = 1)

[Programming Cautions]

There is a one-instruction delay in the updating of the PSW to reflect flag changes.

However, the Bcc and Lcc instructions can evaluate the flags without waiting for the flag changes to be reflected in the PSW.

When "udf12 Dm, Dn" is operated, Dm is ignored.

The operations of "udf12 imm8, Dn", "udf12 imm16, Dn" and "udf12 imm32, Dn" are not assured. In addition, a system error interrupt does not occur in these cases.

3-8

Extension Instruction Specifications

GETCLX (Register low-order 32-bit transfer instruction for multiply-and-accumulate operation: Store)

[Instruction Format (Macro Name)]

GETCLX Dn

[Assembler Mnemonic]

udf13 Dn, Dn

[Operation]

This instruction transfers the contents of the multiply-and-accumulate register MCRL to Dn.

The contents of the multiply-and-accumulate overflow detect register MCVF are set in the V flag.

[Flag Changes]

When multiply-and-accumulate operation overflow was not detected (MCVF = 0)

When multiply-and-accumulate operation overflow was detected (MCVF = 1)

[Programming Cautions]

There is a one-instruction delay in the updating of the PSW to reflect flag changes.

However, the Bcc and Lcc instructions can evaluate the flags without waiting for the flag changes to be reflected in the PSW.

When "udf13 Dm, Dn" is operated, Dm is ignored.

The operations of "udf13 imm8, Dn", "udf13 imm16, Dn" and "udf13 imm32, Dn" are not assured. In addition, a system error interrupt does not occur in these cases.

3-9

Extension Instruction Specifications

CLRMAC (Register clear instruction for multiply-and-accumulate operation)

[Instruction Format (Macro Name)]

CLRMAC

[Assembler Mnemonic]

udf22 D0, D0

[Operation]

This instruction clears the contents of the multiply-and-accumulate registers MCRH and MCRL.

This instruction also clears the contents of the multiply-and-accumulate overflow detect register MCVF.

[Flag Changes]

[Programming Cautions]

When "udf22 Dm, Dn" is operated, Dm and Dn are ignored.

3-10

Extension Instruction Specifications

MULQ (Signed high-speed multiplication instruction: between registers)

[Instruction Format (Macro Name)]

MULQ Dm, Dn

[Assembler Mnemonic]

udf00 Dm, Dn

[Operation]

This instruction performs multiplication quickly using the multiplier of the extension function unit.

The contents of Dm (signed 32-bit integer: multiplicand) and Dn (signed 32-bit integer: multiplier) are multiplied, and the upper 32 bits of the results (64 bits) are written into the high-speed multiply register MDRQ and the lower 32 bits into Dn.

The significant value range of the multiplicand stored in Dm before the operation is judged (starting point: LSB,

judgment unit: 2 bytes), and the operation is only performed for the range containing these significant values. In other words, the smaller the absolute value of the contents stored in Dm, the quicker operation results can be obtained.

[Flag Changes]

[Programming Cautions]

PSW updating by flag changes is delayed by one instruction.

However, Bcc and Lcc instructions can evaluate flags without waiting for flag reflection to PSW.

3-11

Extension Instruction Specifications

MULQI (Signed high-speed multiplication instruction: between immediate value and register)

[Instruction Format (Macro Name)]

MULQI imm, Dn

[Assembler Mnemonic]

[Operation]

This instruction performs multiplication quickly using the multiplier of the extension function unit.

The 32-bit data obtained by sign-extending imm (multiplicand) and the contents of Dn (signed 32-bit integer: multiplier) are multiplied, and the upper 32 bits of the results (64 bits) are written into the high-speed multiply register MDRQ and the lower 32 bits into Dn.

The significant value range of the multiplicand stored in imm before the operation is judged (starting point: LSB,

judgment unit: 2 bytes), and the operation is only performed for the range containing these significant values. In other words, if the number of imm bits is ???16??? or less, the operation results will be derived faster.

[Flag Changes]

[Programming Cautions]

PSW updating by flag changes is delayed by one instruction.

However, Bcc and Lcc instructions can evaluate flags without waiting for flag reflection to PSW.

3-12

Extension Instruction Specifications

MULQU (Unsigned high-speed multiplication instruction: between registers)

[Instruction Format (Macro Name)]

MULQU Dm, Dn

[Assembler Mnemonic]

udf01 Dm, Dn

[Operation]

This instruction performs multiplication quickly using the multiplier of the extension function unit.

The contents of Dm (unsigned 32-bit integer: multiplicand) and Dn (unsigned 32-bit integer: multiplier) are multiplied, and the upper 32 bits of the results (64 bits) are written into the high-speed multiply register MDRQ and the lower 32 bits into Dn.

The significant value range of the multiplicand stored in Dm before the operation is judged (starting point: LSB,

judgment unit: 2 bytes), and the operation is only performed for the range containing these significant values. In other words, the smaller the contents stored in Dm, the quicker operation results can be obtained.

[Flag Changes]

[Programming Cautions]

PSW updating by flag changes is delayed by one instruction.

However, Bcc and Lcc instructions can evaluate flags without waiting for flag reflection to PSW.

3-13

Extension Instruction Specifications

MULQIU (Unsigned high-speed multiplication instruction: between immediate value and register)

[Instruction Format (Macro Name)]

MULQIU imm, Dn

[Assembler Mnemonic]

[Operation]

This instruction performs multiplication quickly using the multiplier of the extension function unit.

The 32-bit data obtained by zero-extending imm (multiplicand) and the contents of Dn (unsigned 32-bit integer: multiplier) are multiplied, and the upper 32 bits of the results (64 bits) are written into the high-speed multiply register MDRQ and the lower 32 bits into Dn.

The significant value range of the multiplicand stored in imm before the operation is judged (starting point: LSB,

judgment unit: 2 bytes), and the operation is only performed for the range containing these significant values. In other words, if the number of imm bits is ???16??? or less, the operation results will be derived faster.

[Flag Changes]

[Programming Cautions]

PSW updating by flag changes is delayed by one instruction.

However, Bcc and Lcc instructions can evaluate flags without waiting for flag reflection to PSW.

3-14

Extension Instruction Specifications

MAC (Signed multiply-and-accumulate operation instruction: between registers)

[Instruction Format (Macro Name)]

MAC Dm, Dn

[Assembler Mnemonic]

udf28 Dm, Dn

[Operation]

This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension function unit.

The instruction multiplies the contents of Dm (signed 32-bit integer: multiplicand) by the contents of Dn (signed

32-bit integer: multiplier), it adds the product obtained by this multiplication to the cumulative sum (64 bits) of the upper 32 bits and lower 32 bits stored in the respective multiply-and-accumulate registers MCRH and MCRL, and it then stores the upper 32 bits of the result (64 bits) in the multiply-and-accumulate register MCRH and the lower 32 bits in the multiply-and-accumulate register MCRL.

If an overflow from the 64-bit cumulative sum data is generated when the product is added to the cumulative sum, multiply-and-accumulate overflow detection flag 1 is output to register MCVF.

[Flag Changes]

[Programming Cautions]

A non-extension instruction that consumes at least two cycles must be inserted between this instruction and the next extension instruction.

3-15

Extension Instruction Specifications

MACH (Signed half word data multiply-and-accumulate operation instruction: between registers)

[Instruction Format (Macro Name)]

MACH Dm, Dn

[Assembler Mnemonic]

udf30 Dm, Dn

[Operation]

This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension function unit.

The instruction multiplies the contents of Dm (signed 16-bit integer: multiplicand) by the contents of Dn (signed

16-bit integer: multiplier), it adds the product obtained by this multiplication to the cumulative sum (64 bits) of the upper 32 bits and lower 32 bits stored in the respective multiply-and-accumulate registers MCRH and MCRL, and it then stores the upper 32 bits of the result (64 bits) in the multiply-and-accumulate register MCRH and the lower 32 bits in the multiply-and-accumulate register MCRL.

If an overflow from the 64-bit cumulative sum data is generated when the product is added to the cumulative sum, multiply-and-accumulate overflow detection flag 1 is output to register MCVF.

[Flag Changes]

[Programming Cautions]

A non-extension instruction that consumes at least one cycle must be inserted between this instruction and the next extension instruction.

3-16

Extension Instruction Specifications

MACB (Signed byte data multiply-and-accumulate operation instruction: between registers)

[Instruction Format (Macro Name)]

MACB Dm, Dn

[Assembler Mnemonic]

udf32 Dm, Dn

[Operation]

This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension function unit.

The instruction multiplies the contents of Dm (signed 8-bit integer: multiplicand) by the contents of Dn (signed

8-bit integer: multiplier), adds the resulting product to the 32-bit cumulative sum that is stored in the multiply-and- accumulate register MCRL, and then stores the new resulting 32-bit cumulative sum back in multiply-and-accumulate register MCRL.

If an overflow from the 32-bit cumulative sum data is generated when the product is added to the cumulative sum, multiply-and-accumulate overflow detection flag 1 is output to register MCVF.

[Flag Changes]

[Programming Cautions]

A non-extension instruction that consumes at least one cycle must be inserted between this instruction and the next extension instruction.

3-17

Extension Instruction Specifications

MACU (Unsigned multiply-and-accumulate operation instruction: between registers)

[Instruction Format (Macro Name)]

MACU Dm, Dn

[Assembler Mnemonic]

udf29 Dm, Dn

[Operation]

This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension function unit.

The instruction multiplies the contents of Dm (unsigned 32-bit integer: multiplicand) by the contents of Dn (unsigned

32-bit integer: multiplier), it adds the product obtained by this multiplication to the cumulative sum (64 bits) of the upper 32 bits and lower 32 bits stored in the respective multiply-and-accumulate registers MCRH and MCRL, and it then stores the upper 32 bits of the result (64 bits) in the multiply-and-accumulate register MCRH and the lower 32 bits in the multiply-and-accumulate register MCRL.

If an overflow from the 64-bit cumulative sum data is generated when the product is added to the cumulative sum, multiply-and-accumulate overflow detection flag 1 is output to register MCVF.

[Flag Changes]

[Programming Cautions]

A non-extension instruction that consumes at least two cycles must be inserted between this instruction and the next extension instruction.

3-18

Extension Instruction Specifications

MACHU (Unsigned half word data multiply-and-accumulate operation instruction: between registers)

[Instruction Format (Macro Name)]

MACHU Dm, Dn

[Assembler Mnemonic]

udf31 Dm, Dn

[Operation]

This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension function unit.

The instruction multiplies the contents of Dm (unsigned 16-bit integer: multiplicand) by the contents of Dn (unsigned

16-bit integer: multiplier), it adds the product obtained by this multiplication to the cumulative sum (64 bits) of the upper 32 bits and lower 32 bits stored in the respective multiply-and-accumulate registers MCRH and MCRL, and it then stores the upper 32 bits of the result (64 bits) in the multiply-and-accumulate register MCRH and the lower 32 bits in the multiply-and-accumulate register MCRL.

If an overflow from the 64-bit cumulative sum data is generated when the product is added to the cumulative sum, multiply-and-accumulate overflow detection flag 1 is output to register MCVF.

[Flag Changes]

[Programming Cautions]

A non-extension instruction that consumes at least one cycle must be inserted between this instruction and the next extension instruction.

3-19

Extension Instruction Specifications

MACBU (Unsigned byte data multiply-and-accumulate operation instruction: between registers)

[Instruction Format (Macro Name)]

MACBU Dm, Dn

[Assembler Mnemonic]

udf33 Dm, Dn

[Operation]

This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension function unit.

The instruction multiplies the contents of Dm (unsigned 8-bit integer: multiplicand) by the contents of Dn (unsigned

8-bit integer: multiplier), adds the resulting product to the 32-bit cumulative sum that is stored in the multiply-and- accumulate register MCRL, and then stores the new resulting 32-bit cumulative sum back in multiply-and-accumulate register MCRL.

If an overflow from the 32-bit cumulative sum data is generated when the product is added to the cumulative sum, multiply-and-accumulate overflow detection flag 1 is output to register MCVF.

[Flag Changes]

[Programming Cautions]

A non-extension instruction that consumes at least one cycle must be inserted between this instruction and the next extension instruction.

3-20

Extension Instruction Specifications

SAT16 (16-bit saturation operation instruction)

[Instruction Format (Macro Name)]

SAT16 Dm, Dn

[Assembler Mnemonic]

udf04 Dm, Dn

[Operation]

When Dm is a 16-bit signed number which is the maximum positive value (0x00007fff) or more, the maximum positive value (0x00007fff) is written into Dn. When Dm is a 16-bit signed number which is the maximum negative value (0xffff8000) or less, the maximum negative value (0xffff8000) is stored in Dn. In all other cases, the contents of Dm are written into Dn.

[Flag Changes]

[Programming Cautions]

PSW updating by flag changes is delayed by one instruction.

However, Bcc and Lcc instructions can evaluate flags without waiting for flag reflection to PSW.

The operations of "udf04 imm8, Dn", "udf04 imm16, Dn" and "udf04 imm32, Dn" are not assured. In addition, a system error interrupt does not occur in these cases.

3-21

Extension Instruction Specifications

SAT24 (24-bit saturation operation instruction)

[Instruction Format (Macro Name)]

SAT24 Dm, Dn

[Assembler Mnemonic]

udf05 Dm, Dn

[Operation]

When Dm is a 24-bit signed number which is the maximum positive value (0x007fffff) or more, the maximum positive value (0x007fffff) is written into Dn. When Dm is a 24-bit signed number which is the maximum negative value (0xff800000) or less, the maximum negative value (0xff800000) is written into Dn. In all other cases, the contents of Dm are written into Dn.

[Flag Changes]

[Programming Cautions]

PSW updating by flag changes is delayed by one instruction.

However, Bcc and Lcc instructions can evaluate flags without waiting for flag reflection to PSW.

The operations of "udf05 imm8, Dn", "udf05 imm16, Dn" and "udf05 imm32, Dn" are not assured. In addition, a system error interrupt does not occur in these cases.

3-22

Extension Instruction Specifications

MCST (Multiply-and-accumulate operation results 8-, 16-, 32-bit saturation operation instruction)

[Instruction Format (Macro Name)]

MCST Dm, Dn

MCST imm8, Dn

[Assembler Mnemonic]

[Operation]

This instruction sets the contents of the multiply-and-accumulate operation overflow detect register MCVF in the V flag. In addition, depending on the value of Dm or imm8, the following operations are performed.

(1) When the value of Dm or imm8 is 32 (0x00000020)

When the 64-bit result of the multiply-and-accumulate operation that is stored in the multiply-and-accumulate registers MCRH and MCRL is equal to or greater than the maximum positive value for a 32-bit signed numeric value (0x000000007fffffff), the maximum positive value (0x7fffffff) is stored in Dn. If the value stored in the multiply-and-accumulate registers MCRH and MCRL is equal to or less than the maximum negative value for a 32- bit signed numeric value (0xffffffff80000000), the maximum negative value (0x80000000) is stored in Dn. In all other cases, the contents of MCRL are stored in Dn.

(2) When the value of Dm or imm8 is 16 (0x00000010)

When the 64-bit result of the multiply-and-accumulate operation that is stored in the multiply-and-accumulate registers MCRH and MCRL is equal to or greater than the maximum positive value for a 16-bit signed numeric value (0x0000000000007fff), the maximum positive value (0x00007fff) is stored in Dn. If the value stored in the multiply-and-accumulate registers MCRH and MCRL is equal to or less than the maximum negative value for a 16- bit signed numeric value (0xffffffffffff8000), the maximum negative value (0xffff8000) is stored in Dn. In all other cases, the contents of MCRL are stored in Dn.

(3) When the value of Dm or imm8 is 8 (0x00000008)

When the 32-bit result of the multiply-and-accumulate operation that is stored in the multiply-and-accumulate register MCRL is equal to or greater than the maximum positive value for an 8-bit signed numeric value (0x0000007f), the maximum positive value (0x7f) is stored in Dn. If the value stored in the multiply-and-accumulate register MCRL is equal to or less than the maximum negative value for an 8-bit signed numeric value (0xffffff80), the maximum negative value (0x80) is stored in Dn. In all other cases, the contents of MCRL are stored in Dn.

(4) When the value of Dm or imm8 is any other value The value in Dn is undefined.

3-23

Extension Instruction Specifications

[Flag Changes]

When multiply-and-accumulate operation overflow was not detected (MCVF = 0)

When multiply-and-accumulate operation overflow was detected (MCVF = 1)

[Programming Cautions]

There is a one-instruction delay in the updating of the PSW to reflect flag changes.

However, the Bcc and Lcc instructions can evaluate the flags without waiting for the flag changes to be reflected in the PSW.

The operations of "udf02 imm16, Dn" and "udf02 imm32, Dn" are not assured. In addition, a system error interrupt does not occur in these cases.

3-24

Extension Instruction Specifications

MCST9 (Multiply-and-accumulate operation results 9-bit saturation operation instruction/positive value conversion instruction)

[Instruction Format (Macro Name)]

MCST9 Dn

[Assembler Mnemonic]

udf03 Dn, Dn

[Operation]

When the 32-bit result of the multiply-and-accumulate operation that is stored in the multiply-and-accumulate register MCRL is equal to or greater than the maximum positive value for a 9-bit signed numeric value (0x000000ff), the maximum positive value (0xff) is stored in Dn. If the value stored in the multiply-and-accumulate register MCRL is equal to or less than the negative value for a 32-bit signed numeric value (0x00000000), the 0 (0x00) is stored in Dn. In all other cases, the contents of MCRL are stored in Dn.

This instruction sets the contents of the multiply-and-accumulate operation overflow detect register MCVF in the V flag.

[Flag Changes]

When multiply-and-accumulate operation overflow was not detected (MCVF = 0)

When multiply-and-accumulate operation overflow was detected (MCVF = 1)

[Programming Cautions]

There is a one-instruction delay in the updating of the PSW to reflect flag changes.

However, the Bcc and Lcc instructions can evaluate the flags without waiting for the flag changes to be reflected in the PSW.

When "udf03 Dm, Dn" is operated, Dm is ignored.

The operations of "udf03 imm8, Dn", "udf03 imm16, Dn" and "udf03 imm32, Dn" are not assured. In addition, a system error interrupt does not occur in these cases.

3-25

Extension Instruction Specifications

MCST48 (Multiply-and-accumulate operation results 48-bit saturation operation instruction)

[Instruction Format (Macro Name)]

MCST48 Dn

[Assembler Mnemonic]

udf06 Dn, Dn

[Operation]

When the 64-bit result of the multiply-and-accumulate operation that is stored in the multiply-and-accumulate registers MCRH and MCRL is equal to or greater than the maximum positive value for a 48-bit signed numeric value (0x00007fffffffffff), the maximum positive value (0x00007fffffffffff) is output and bits 47 through bits 16 of that output are stored in Dn. If the value stored in the multiply-and-accumulate registers MCRH and MCRL is equal to or less than the maximum negative value for a 48-bit signed numeric value (0xffff800000000000), the maximum negative value (0xffff800000000000) is output and bits 47 through bits 16 of that output are stored in Dn. In all other cases, the contents of MCRH and MCRL are output and bits 47 through bits 16 of that output are stored in Dn.

This instruction sets the contents of the multiply-and-accumulate operation overflow detect register MCVF in the V flag.

[Flag Changes]

When multiply-and-accumulate operation overflow was not detected (MCVF = 0)

When multiply-and-accumulate operation overflow was detected (MCVF = 1)

[Programming Cautions]

There is a one-instruction delay in the updating of the PSW to reflect flag changes.

However, the Bcc and Lcc instructions can evaluate the flags without waiting for the flag changes to be reflected in the PSW.

When "udf06 Dm, Dn" is operated, Dm is ignored.

The operations of "udf06 imm8, Dn", "udf06 imm16, Dn" and "udf06 imm32, Dn" are not assured. In addition, a system error interrupt does not occur in these cases.

3-26

Extension Instruction Specifications

BSCH (Bit search instruction)

[Instruction Format (Macro Name)]

BSCH Dm, Dn

[Assembler Mnemonic]

udf07 Dm, Dn

[Operation]

Bit search is performed within the bit string of the 32 bits contained in Dm from the bit position of the bit number indicated by the contents of Dn - 1 in the direction that the bit number becomes smaller. The bit number of the first bit position where a "1" is found is written into Dn.

When the contents of the lower 5 bits of Dn are 0, bit search is performed from bit 31 in the direction that the bit number becomes smaller.

If search is performed up to the bit position of bit 0 without finding a "1", the C flag is set, Dn is set to 0x00000000, and instruction execution ends.

When instruction execution starts, the upper 27 bits of Dn are ignored.

[Flag Changes]

When search was successful ("1" was found)

When search failed ("1" was not found)

[Programming Cautions]

PSW updating by flag changes is delayed by one instruction.

However, Bcc and Lcc instructions can evaluate flags without waiting for flag reflection to PSW.

The operations of "udf07 imm8, Dn", "udf07 imm16, Dn" and "udf07 imm32, Dn" are not assured. In addition, a system error interrupt does not occur in these cases.

3-27

Extension Instruction Specifications

SWAP (Data swapping instruction that swaps bytes [high-order to low-order and vice versa] in four-byte data)

[Instruction Format (Macro Name)]

SWAP Dm, Dn

[Assembler Mnemonic]

udf08 Dm, Dn

[Operation]

This instruction swaps the positions of the high-order and low-order 8-bit bytes within the respective high- and low-order 16-bit half-words within the 32-bit data stored in Dm, and then swaps the positions of the high-order and low-order 16-bit half-words, and then stores the result in Dn. As a result, bits 31 through 24 of Dm are stored in bits 7 through 0 in Dn, bits 23 through 16 of Dm are stored in bits 15 through 8 in Dn, bits 15 through 8 of Dm are stored in bits 23 through 16 in Dn, and bits 7 through 0 of Dm are stored in bits 31 through 24 in Dn.

The sample of execution

Before execution: 0x12345678

After execution: 0x78563412

3-28

Extension Instruction Specifications

[Flag Changes]

[Programming Cautions]

PSW updating by flag changes is delayed by one instruction.

However, Bcc and Lcc instructions can evaluate flags without waiting for flag reflection to PSW.

The operations of "udf08 imm8, Dn", "udf08 imm16, Dn" and "udf08 imm32, Dn" are not assured. In addition, a system error interrupt does not occur in these cases.

3-29

Extension Instruction Specifications

SWAPH (Data swapping instruction [high-order to low-order and vice versa] in two-byte data)

[Instruction Format (Macro Name)]

SWAPH Dm, Dn

[Assembler Mnemonic]

udf09 Dm, Dn

[Operation]

This instruction swaps bits 15 through 8 of Dm with bits 7 through 0, and bits 31 through 24 with bits 23 through 16, and then stores the result in Dn.

The sample of execution

Before execution: 0x12345678

After execution: 0x34127856

[Flag Changes]

[Programming Cautions]

PSW updating by flag changes is delayed by one instruction.

However, Bcc and Lcc instructions can evaluate flags without waiting for flag reflection to PSW.

The operations of "udf09 imm8, Dn", "udf09 imm16, Dn" and "udf09 imm32, Dn" are not assured. In addition, a system error interrupt does not occur in these cases.

3-30

Extension Instruction Specifications

3.2.4 Programming Notes

??? Notes on instruction description

These programming notes address instruction descriptions as well as instruction placement and combinations. Failure to heed these notes will result in misoperation. A list of these notes is shown below.

Table 3-2-1 Notes on Instruction Description

*1: The category ???Word/half-word data multiply-and-accumulate instruction??? applies to the following instructions: MAC instruction, MACH instruction, MACU instruction, MACHU instruction

*2: The category ???byte data multiply-and-accumulate instruction??? applies to the following instructions: MACB instruction, MACBU instruction

*3: The category ???multiply-and-accumulate instruction??? applies to the following instructions:

MAC instruction, MACH instruction, MACU instruction, MACHU instruction, MACB instruction, MACBU instruction

*4: The category ???MCRH, MCRL access instruction??? applies to the following instructions: PUTCX instruction, CLRMAC instruction, GETCHX instruction, GETCLX instruction

*5: The category ???High-speed multiplication instruction??? applies to the following instructions: MULQ instruction, MULQU instruction, MULQI instruction, MULQIU instruction

3-31

Extension Instruction Specifications

(a)Note on the description of word/half-word data multiply-and-accumulate instructions and multiply-and- accumulate instructions

When executing a word/half-word data multiply-and-accumulate instruction followed by a multiply-and-accumulate instruction, the result produced by the word/half-word data multiply-and-accumulate instruction is used in the execution of the subsequent multiply-and-accumulate instruction. Therefore, it is essential to not initiate the subsequent multiply-and-accumulate instruction until after the result that is required from the word/half-word data multiply-and-accumulate instruction has been output. As a result, one cycle must be inserted between the word/ half-word data multiply-and-accumulate instruction and the subsequent multiply-and-accumulate instruction.

DEC

EX

OperationOperation

MEM

WB

M u lt ip l y -and -ac c u mu lat e instruction (1) has output the result that is required by

mu lt i p ly -a n d -acc u mu lat e instruction (2)

This note applies to the following instructions:

<Word/half-word data multiply-and-accumulate instructions>

MAC instruction, MACH instruction, MACU instruction, MACHU instruction <Multiply-and-accumulate instructions>

MAC instruction, MACH instruction, MACU instruction, MACHU instruction, MACB instruction, MACBU instruction

3-32

Extension Instruction Specifications

(b)Note on the description of word/half-word data multiply-and-accumulate instructions and MCRH, MCRL access instructions

When executing a word/half-word data multiply-and-accumulate instruction followed by an MCRH, MCRL access instruction, the result produced by the word/half-word data multiply-and-accumulate instruction is used in the execution of the subsequent MCRH, MCRL access instruction. Therefore, it is essential to not initiate the subsequent MCRH, MCRL access instruction until after the result that is required from the word/half-word data multiply-and- accumulate instruction has been output. As a result, two cycles must be inserted between the word/half-word data multiply-and-accumulate instruction and the subsequent MCRH, MCRL access instruction.

MEM

WB

M u l t i p l y - a nd - a c c um u l a t e instruction has output the result that is required by MCRH, MCRL access instruction

This note applies to the following instructions:

<Word/half-word data multiply-and-accumulate instructions>

MAC instruction, MACH instruction, MACU instruction, MACHU instruction <MCRH, MCRL access instructions>

PUTCX instruction, CLRMAC instruction, GETCHX instruction, GETCLX instruction

3-33

Extension Instruction Specifications

(c) Note on the description of byte data multiply-and-accumulate instructions and MCRH, MCRL access instructions

When executing a byte data multiply-and-accumulate instruction followed by an MCRH, MCRL access instruction, the result produced by the byte data multiply-and-accumulate instruction is used in the execution of the subsequent MCRH, MCRL access instruction. Therefore, it is essential to not initiate the subsequent MCRH, MCRL access instruction until after the result that is required from the byte data multiply-and-accumulate instruction has been output. As a result, one cycle must be inserted between the byte data multiply-and-accumulate instruction and the subsequent MCRH, MCRL access instruction.

MEM

WB

M ul t i pl y - a nd - a c c u m ul a t e instruction has output the result that is required by MCRH, MCRL access instruction

This note applies to the following instructions:

<Byte data multiply-and-accumulate instructions> MACB instruction, MACBU instruction

<MCRH, MCRL access instructions>

PUTCX instruction, CLRMAC instruction, GETCHX instruction, GETCLX instruction

3-34

Extension Instruction Specifications

(d)Note on the description of multiply-and-accumulate instructions and multiply-and-accumulate instructions or multiply-and-accumulate instructions and quick multiplication instructions

When executing a multiply-and-accumulate instruction followed by another multiply-and-accumulate instruction or a quick multiplication instruction, at least three cycles must be inserted between the instructions. However, no problems are encountered in the case of the instruction combinations listed in the table, or when the value of the multiply-and-accumulate operation overflow detect register MCVF is not used.

This note applies to the following instructions (except in the case of the instruction combinations listed above): <Multiply-and-accumulate instructions>

MAC instruction, MACH instruction, MACU instruction, MACHU instruction MACB instruction, MACBU instruction,

<High-speed multiplication instructions>

MULQ instruction, MULQU instruction, MULQI instruction, MULQIU instruction

3-35

Extension Instruction Specifications

(e)Note on the description of memory access and multiply-and-accumulate instruction or high-speed multiplication instruction

There is an error occasion - CPU hung-up - as written below, if High-speed multiplication instruction or Multiply- and-accumulate instruction is executed within 2 instructions after a memory access instruction that accesses to internal ROM, internal peripheral I/O space or external memory space (this space is referred to as "the space other than internal RAM" below).

However, this note is not applied in either of the following 4 conditions.

1. The Extension Instruction is not used.

PanaXSeries C compiler outputs High-speed multiplication instruction only if you use compiler option (-mmulq). If you don't use that option, PanaXSeries C compiler never outputs Extension Instruction.

2.Only High-speed multiplication instructions are used in Extension Instructions.

3.Only Multiply-and-accumulate instructions are used in Extension Instructions.

4.Only the other extension instructions are used in Extension Instructions.

???In this note, "Extension Instructions" are classified into Multiply-and-accumulate instructions, High-speed multiplication instructions and the other extension instructions.

There is an error occasion - CPU hung-up -, when "error actualizing condition" occurs after generating "error making potential condition".

"Error making potential condition" and "Error actualizing condition" are described in details below. An "interrupt" on this note is defined as one of level interrupts or non-maskable interrupts*.

* When ICE is used, there is error occasion as in the case of level interrupts and non-maskable interrupts.

<Error making potential condition>

Error making potential condition occurs when an interrupt is requested during instruction decoding of High-speed multiplication instruction or Multiply-and-accumulate instruction executed after a memory access instruction that accesses to the space other than internal RAM. Error making potential conditions are classified into the following 12 cases.

3-36

Extension Instruction Specifications

Case 3:

If a stack area is in the internal RAM, any error making potential condition shown on the following cases 4 to 12 is not generated.

The case where the number of returned register by RET instruction is 0 or 1 is excluded. And also the case where 2 registers are returned by RET instruction and the High-speed multiplication instruction uses 32-bit immediate value is excluded.

Case 5:

The case where the number of returned register by RET instruction is 0, 1 or 2 is excluded. And also the case where the High-speed multiplication instruction uses 32-bit immediate value is excluded.

The case where the number of returned register by RETF instruction is 0 is excluded.

Case 7:

The case where the number of returned register by RETF instruction is 0 is excluded. And also the case where the High-speed multiplication instruction uses 32-bit immediate value is excluded.

The case where the High-speed multiplication instruction uses 32-bit immediate value is excluded.

3-37

Extension Instruction Specifications

The case where the High-speed multiplication instruction uses 32-bit immediate value is excluded.

The case where the High-speed multiplication instruction uses 32-bit immediate value is excluded.

The case where the High-speed multiplication instruction uses 32-bit immediate value is excluded.

<Error actualizing condition>

Error actualizing condition is generated by the first extension instruction executed in the interrupt program, or after switching of the task. Error actualizing condition is shown below.

The error making potential condition is cleared when there is no problem.

When the condition of use corresponds to "Error generation", it is possible to solve the error condition by inserting the 2 NOP instructions as follows.

When the program is compiled and assembled, 2 NOP instructions are inserted on default by using the assembler and linker V3.3R1 or later.

Extension Instruction Specifications

In addition, please obey the following recommended conditions of 3 points when a program is developed by the assembler so that this error would not occur. As for the program developed by the PanaXSeries C compiler, the following recommended conditions are guaranteed.

1.Please use RTI instruction on a return from an interrupt.

2.Please use the value set by SETLB instruction for LIR and LAR which stores branch target of Lcc instruction.

3.Please don't execute RET instruction or RETF instruction operating the stack frame.

This note applies to the following instructions : <Memory access instructions>

Ones of the following instructions which access to a memory.

MOV instruction, MOVBU instruction, MOVHU instruction, MOVM instruction, BSET instruction, BCLR instruction, MOVH instruction (Only store) or MOVB instruction (Only store).

<Multiply-and-accumulate instructions>

MAC instruction, MACH instruction, MACU instruction, MACHU instruction, MACB instruction, MACBU instruction

<High-speed multiplication instructions>

MULQ instruction, MULQU instruction, MULQI instruction, MULQIU instruction <The other extension instructions>

PUTX instruction, PUTCX instruction, GETX instruction, GETCHX instruction, GETCLX instruction, CLRMAC instruction, SAT16 instruction, SAT24 instruction, MCST instruction, MACT9 instruction, MCST48 instruction, BSCH instruction, SWAP instruction, SWAPH instruction

3-39

Extension Instruction Specifications

3-40

Memory Modes

4.1 Memory Mode Types and Selection

This microcontroller has a 32-bit linear address space of up to 4 Gbytes.

The address space is comprised of internal memory space built into the chip and external memory space located outside the chip. The internal memory space can be further divided into internal data space which allows high- speed data access, internal I/O space which contains the I/O ports and control registers built into the chip, and internal instruction space which mainly contains instructions.

Instructions can only be located in the internal instruction space within the internal memory space and in the external memory space. Data can be located in all address spaces, and can be referenced by the MOV instruction. Accordingly, all addressing modes can be used to access data, enabling efficient programming.

The address space differs according to the two memory modes of memory extension mode and processor mode. For details on the address space in each memory mode, refer to Fig. 4-3-1 and Fig. 4-3-2. When using the register indirect with displacement and register indirect with index addressing modes, make sure that the space (either the internal instruction space, the internal data space, the internal I/O space, or the external memory space) containing the address pointed at by the base registers (Am, An and SP) and the space containing the calculated address are the same.

4-2

Memory Modes

4.2 Memory Mode Pin Processing

Fix the input levels for the memory mode pins (MMOD0,1) as shown in Table 4-2-1 and Fig. 4-2-1 with pull-up/ pull-down resistors.

For details on the pull-up/pull-down resistance, refer to ???High-speed Serial Control Card Operation Manual???.

Table 4-2-1 Memory Mode Setting

For details on the memory mode settings for onboard writing of flash memory in the MN1030F01K, refer to chapter 16, ???Internal Flash Memory???.

VDD

R

MMOD0

(SDATA)

R'

R

MMOD1

(SCLOCK)

R'

Fig. 4-2-1 Memory Mode Pin Connection Diagram

Note that the memory mode pins (MMOD0,1) also serve as serial interface pins for debugging and for onboard writing of flash memory in the MN1030F01K. The memory mode pins (MMOD0 and 1) are normally input pins, but when they are connected to the serial interface for debugging and for onboard writing of flash memory in the MN1030F01K, they become N ch (when pulled up) or P ch (when pulled down) open drain input/output pins.

???Direct inquires for details on the serial interface for debugging and for onboard writing of flash memory in the MN1030F01K to the contact indicated at the end of this manual.

4-3

Memory Modes

4.3 Description of Memory Mode

4.3.1Memory Extension Mode

The memory mode which comprises a system from both internal and external memory is called memory extension mode. This mode enables configuration of a system where the program and data make the best use of the high- speed performance of internal memory and the large capacity of external memory. This mode is useful when the program sizes exceed the maximum internal capacity or when locating instructions externally due to facilitate program revisions.

Memory extension mode has memory space of up to 3 GB from addresses x'00000000 to x'BFFFFFFF. Addresses x'00000000 to x'1FFFFFFF are the internal data space (up to 512 MB) which contains data, addresses x'20000000 to x'3FFFFFFF are the internal I/O space (up to 512 MB) which is assigned to the I/O ports and control registers, addresses x'40000000 to x'7FFFFFFF are the internal instruction space which contains instructions and table data, and addresses x'80000000 to x'BFFFFFFF are the external memory space (up to 1 GB).

The MN103001G has 128 Kbytes of internal instruction ROM located at x'40000000 to x'4001FFFF. The MN103001G also has 8 Kbytes of internal data RAM located at x'00000000 to x'00001FFF.

The MN1030F01K has 256 Kbytes of internal flash memory located at x'40000000 to x'4002FFFF. The MN1030F01K also has 8 Kbytes of internal data RAM located at x'00000000 to x'00001FFF.

Note that it is prohibited to access unmounted space of the internal data space, the internal I/O space and the internal instruction space. When accessing the unmounted space, the operation is not assured.

Fig. 4-3-1 Memory Space in Extension Memory Mode

4-4

Memory Modes

4.3.2Processor Mode

The memory mode which executes externally located instructions while using the internal data RAM and I/O ports is called processor mode. The internal instruction ROM and the internal flash memory are not used for this mode. Processor mode has memory space of up to 3 GB from addresses x'00000000 to x'BFFFFFFF. Addresses x'00000000 to x'1FFFFFFF are the internal data space (up to 512 MB) which contains data, addresses x'20000000 to x'3FFFFFFF are the internal I/O space (up to 512 MB) which is assigned to the I/O ports and control registers, and addresses x'40000000 to x'BFFFFFFF are the external memory space (up to 2 GB).

This microcontroller has 8 Kbytes of data RAM located at x'00000000 to x'00001FFF.

Note that it is prohibited to access unmounted space of the internal data space and the internal I/O space. When accessing the unmounted space, the operation is not assured.

Fig. 4-3-2 Memory Space in Processor Mode

4-5

Memory Modes

4-6

Operating Mode

5.1 Overview

The 32-bit microcontroller has the following three operating modes. Oscillator start/stop and CPU and peripheral circuit start/stop switching control functions are provided to support low power consumption.

Operating modes

1.Reset mode (RESET)

2.Normal operation mode (NORMAL)

3.Low power mode

Stop mode (STOP)

Halt mode (HALT)

Sleep mode (SLEEP)

RESET

Release reset

: Both the CPU and peripheral circuits operating.

: Both the CPU and peripheral circuits stopped.

: CPU stopped but peripheral circuits operating.

: Oscillation stabilization wait inserted.

Fig. 5-1-1 Operating Mode Transition Diagram

(Notes)

???All modes are entered to normal operating mode by resetting the system.

???Changing the mode by program is performed by setting the CPUM register.

5-2

Operating Mode

5.2 Reset Mode

???The mode in which the reset (RST) pin is active (???L??? level) is called ???Reset Mode???.

???When the reset pin is low, the chip is reset (initialized) internally. When the reset pin makes the transition to high, the oscillation stabilization wait time is started by an internal 18-bit (when CKSEL pin = ???H???) or 19-bit (when CKSEL pin = ???L???) binary counter based on the oscillation clock.

The oscillation stabilization wait time tOSCW for oscillation frequency fOSC [MHz] is:

tOSCW = 2n / (fOSC x 103) [ms]

n = 18 (when CKSEL pin = ???H???) or 19 (when CKSEL pin = ???L???) In other words, when CKSEL pin = ???H??? and fOSC = 15[MHz]: tOSCW = 17.476 [ms]

??? Table 5-2-1 shows the status of the internal registers immediately after a reset.

Table 5-2-1 Status of Internal Registers Immediately after a Reset

???Internal reset is canceled after completion of oscillation stabilization wait time, and the microcontroller changes to the normal operation mode.

5-3

Operating Mode

5.3 Low Power Mode

Low power consumption is achieved by stopping the oscillation of the oscillators and the clock generator (CG) and stopping the clocks supplied to the CPU and peripheral circuits. Low power mode contains the following three modes and transitions to the three modes are made through software.

Stop mode (STOP)

In this mode, the oscillation of oscillators as well as the CG oscillation are stopped. In the STOP mode, oscillator and CG operation is started by an interrupt and the microcontroller changes to normal operation mode (NORMAL) after waiting for oscillation to be stabilized.

Halt mode (HALT)

In this mode, the oscillators and CG are oscillating but clock supply to the CPU and peripheral circuits is stopped. Thus, CPU and peripheral circuits operation is stopped.

In the HALT mode, the microcontroller changes to normal operation mode (NORMAL) when an interrupt occurs.

Sleep mode (SLEEP)

In this mode, the oscillators and CG are oscillating but clock supply only to the CPU is stopped. Thus, CPU operation is stopped but the peripheral circuits are operating. In SLEEP mode, the microcontroller changes to normal operation mode (NORMAL) when an interrupt occurs.

???Operation of various peripheral functions in the low power consumption modes

The operation of the peripheral functions in SLEEP, HALT, and STOP mode is shown in the table below.

In SLEEP mode, all peripheral functions operate except for the bus controller and the watchdog timer. In HALT and STOP mode, most peripheral functions are stopped.

In SLEEP mode, the interrupt controller accepts interrupt requests from the peripheral blocks and external pin interrupt requests, notifies the CPU core, and then initiates recovery from SLEEP mode. In HALT/STOP mode, the interrupt controller accepts the external pin interrupt request, notifies the CPU core, and then initiates recovery from HALT/STOP mode.

When making a transition to HALT/SLEEP mode, stop the watchdog timer by clearing the WDCNE bit to "0" in watchdog timer control register WDCTR.

5-4

Clock Generator

6.1 Overview

The CG has an internal PLL circuit; in addition to supplying clock pulses to this microcontroller at a frequency that is a multiple of the oscillating frequency of the oscillator, the CG also supplies clock pulses with the same frequency as the oscillating frequency of the oscillator, or that frequency divided by 2, to external devices.

6.2 Features

The features of the CG are described below.

???Flexible clock control

-Supports self-excitation/external excitation (input frequency: 8 MHz to 20 MHz)

Note: The in-circuit emulator (ICE) cannot operate with self-excited oscillators in the microcontroller.

-When PLL is being used, a clock that is a programmable multiple of the input frequency is supplied as the CPU clock (MCLK). A clock that is 1/4 of MCLK is supplied as the peripheral clock (IOCLK). A clock that is 1x the input frequency is output as the external device supply clock (SYSCLK).

-When PLL is not being used, a clock that is 1/2 of the input frequency is supplied as the CPU clock (MCLK) and as the external device supply clock (SYSCLK), and a clock that is 1/8 of the input frequency is supplied as the peripheral clock (IOCLK).

6.3 Block Diagram

6-2

Clock Generator

6.4 Description of Operation

6.4.1Input Frequency Setting

The CG input frequency range is set by the external input pin CKSEL. When CKSEL is set ???H???, use an oscillator or resonator with an input frequency fosci such that 8 MHz ??? fosci ??? 18 MHz. When CKSEL is set ???L???, use an oscillator or resonator with an input frequency fosci such that 8 MHz ??? fosci ??? 20 MHz.

Use of an oscillator or resonator that generates a frequency lower than 8 MHz, or higher than 20 MHz is prohibited. The correspondence between the CKSEL mode and the input frequency range is shown in Table 6-4-1.

Table 6-4-1 CKSEL Mode (PLL used/ PLL not used)

6.4.2Internal Clock Supply

When external input pin CKSEL is ???H???, the frequency of the CPU core/internal RAM/bus controller operation clock (MCLK) is 1x, 2x or 4x the input frequency, depending on the setting of the clock control register, and the frequency of the internal peripheral function operation clock (IOCLK) is 1/4x MCLK. Note that the clock that is supplied to external devices (SYSCLK) has the same frequency as the input frequency.

When external input pin CKSEL is ???L???, the frequency of the CPU core/internal RAM/bus controller operation clock (MCLK) is 1/2x the input frequency, and the frequency of the internal peripheral function operation clock (IOCLK) is 1/8x the input frequency. Note that the clock that is supplied to external devices (SYSCLK) 1/2x the input frequency.

Note: For details on the clock control register settings, refer to section 8.6.8, ???Clock Control Register.???

When the reset state is released, SYSCLK, MCLK, and IOCLK are supplied starting after a certain oscillation stabilization wait time.

Note: For details on the oscillation stabilization wait time, refer to Chapter 12, ???Watchdog Timer.???

Note 1: When a clock is supplied from external, input the clock to the OSCI pin, and leave the OSCO pin open.

Note 2: The in-circuit emulator (ICE) cannot operate with self-excited oscillators in the microcontroller. Use the clock generated in the target system.

When the clock is generated in the target system, supply the clock to the in-circuit emulator main unit through a buffer with adequate drive capability. The in-circuit emulator will not operate correctly if the amplitude of the clock is inadequate, the clock signal is noisy, or the buffer has inadequate drive capability.

6-3

Clock Generator

The relationship between the input frequency (fosci) and the SYSCLK, MCLK, and IOCLK multiples and frequencies is shown in Table 6-4-2, and the relationship between the input frequency (fosci) and the SYSCLK, MCLK, and IOCLK multiples and frequencies when reset is released is shown in Table 6-4-3.

*: In the case of the MN1030F01K, the maximum frequency for MCLK is 40 MHz.

Note: When changing the input frequency during operation, be certain to enter the reset mode and set the CKSEL pin to the prescribed value during reset mode.

The input frequency ranges shown here are preliminary. When using this LSI, contact our sales office for the product specifications.

6-4

Internal Memory

7.1 Overview

The MN103001G has 128 Kbytes of instruction ROM and 8 Kbytes of internal data RAM. The MN1030F01K has 256 Kbytes of flash memory and 8 Kbytes of internal data RAM. The instruction ROM/flash memory and data RAM are connected to the CPU core via a 64-bit bus and a 32-bit bus, respectively.

7.2 Features

The features of the internal memory are listed below.

???Internal instruction ROM (MN103001G)

-Capacity: 128 Kbytes

-Instruction bus width: 64 bits

-Access cycles: Instruction read: 2 MCLK cycles

???Internal flash memory (MN1030F01K)

-Capacity: 256 Kbytes

-Instruction bus width: 64 bits

-Access cycles: Instruction read: 2 MCLK cycles

???Internal data RAM (MN103001G/MN1030F01K)

-Capacity: 8 Kbytes

-Data bus width: 32 bits

-Access cycles (*): Data read: 1 MCLK cycle

Data write: 1 MCLK cycle

(*): The internal data RAM can only be used to store or read data; it is not possible to store or read instructions in the internal data RAM.

7-2

Internal Memory

7.3 Internal Memory Configuration

The internal instruction ROM is located in the internal memory space at address x'40000000 to x'4001FFFF, while the internal flash memory is located at address x'40000000 to x'4003FFFF and the internal data RAM is located at address x'00000000 to x'00001FFF. Each is connected to the CPU core independently by a dedicated bus in the Harvard architecture (in memory extension mode).

Fig. 7-3-1 shows a block diagram of the internal memory in memory extension mode.

CPU core

256 KB

x'4001FFFF

Internal instruction ROM (MN103001G)

x'4003FFFF

Internal flash memory (MN1030F01K)

Fig. 7-3-1 Internal Memory Block Diagram (In Memory Extension Mode)

Note: In processor mode, internal instruction ROM and internal flash memory is not connected to the CPU core, and addresses x???40000000 to x???BFFFFFFF are used for external memory.

7-3

Internal Memory

7-4

Bus Controller (BC)

8.1 Overview

The bus controller (BC) controls interfacing between the CPU core, internal I/O (peripherals), and devices external to the chip. The bus controller also handles arbitration between the internal and external buses. In addition, in an interface with devices external to the chip, it is possible to select whether address pins and data pins are separate or multiplex. The bus controller outputs four chip select signals, RAS/CAS signals, and other signals for an external bus interface, permitting ROM, SRAM, DRAM, and other peripheral LSIs to be connected directly to this microcontroller.

8.2 Features

The features of the bus controller are described below.

???High-speed control of the internal and external buses through the CPU clock (MCLK) is possible.

-Synchronous mode (synchronized with IOCLK) is supported for the internal I/O bus. Synchronousmode (synchronized with SYSCLK) and asynchronous mode (synchronized with MCLK) are supported for the external bus.

???External memory space can be partitioned into four blocks

-Chip select signal output for each block

-The bus width can be set to 8 or 16 bits for blocks 0 to 3

-Blocks 0 to 3 can be switched between synchronous mode and asynchronous mode

-Blocks 0 to 3 permit the read/write timing to be set through the software

-Blocks 1 and 2 can be used as DRAM space

-Blocks 2 and 3 permit use for handshaking

???DRAM interface

-Address multiplexing function

-Permit the read/write timing to be set through the software

-Support for software page mode through software settings

-Support for CAS-before-RAS refresh (Programmable refresh cycle)

???Permits switching between separate/multiplex address and data pins through the external input pin settings

-Blocks 0 to 3 permit switching between separate/multiplex address and data pins through the external input pin settings

-Using multiplex address and data pins permit the allocation of microcontroller I/O and peripheral pins and reducing the number of external device pins

-Permits direct connection with ROM, SRAM, and DRAM without external circuitry

???Avoids time penalty during storage operations through use of store buffer (one word)

-Support for storage in on-chip peripheral circuits and external devices

-When the store buffer is empty, storage operations are completed with no wait states, and the CPU can execute subsequent processing

8-2

Bus Controller (BC)

8.3 Bus Configuration

Fig. 8-3-1 shows the bus configuration. The chip???s internal buses are the ROM bus between the CPU core and internal instruction ROM/internal flash memory, the RAM bus between the CPU core and internal data RAM, the BC bus between the CPU core and the bus controller, and the I/O bus between the bus controller and internal I/O. The EX bus is an external bus.

Table 8-3-1 lists the characteristics of each bus.

Fig. 8-3-1 Bus Configuration Diagram

Table 8-3-1 Characteristics of Each Bus

(*1) For a description of the operation clock, refer to section 8.8, ???Operation Clock.??? (*2) Set by the external input pin or control register.

8.4 Block Diagram

Fig. 8-4-1 shows the block diagram for the bus controller. The bus controller consists of a controller, a store buffer, a CPU interface (BC bus I/F), an interface for internal I/O circuitry (I/O bus I/F) and an external device interface (EX bus I/F).

8-3

Bus Controller (BC)

Fig. 8-4-1 Block Diagram for the Bus Controller

8-4

Bus Controller (BC)

8.5 Pin Functions

The external pin functions relating to the bus controller are shown in Table 8-5-1.

Table 8-5-1 External Pin Functions Relating to the Bus Controller

Note: WE1 corresponds to D15 to 8, and WE0 corresponds to D7 to 0.

CS2 to 1 and RAS2 to 1, CS3 and A23, CAS and A22, AS and D0, RWSEL and D1, and A15 to 0 and ADM15 to 0 are shared pins.

8-5

Bus Controller (BC)

Table 8-5-2 shows the operating status of the external pins concerning BC.

Table 8-5-2 Operating Status of Pins Concerning BC

Hi-Z: High impedance

Maintain: Maintains the status from the previous bus cycle

L:"L" level output

H:"H" level output

Note: Because the pins listed in the table at right are all multipurpose, check the status of the external pins of the LSI in chapter 15, ???I/O Ports.???

For details on the operating status of each pin upon reset, refer to appendix D, ???Pins and Their Operating Statuses upon Reset.???

8-6

Bus Controller (BC)

8.6 Description of Registers

Table 8-6-1 lists the bus controller registers. The settings of these registers are used in timing control, DRAM interface control, etc.

Table 8-6-1 List of Bus Control Registers

8-7

Bus Controller (BC)

8.6.1 Memory Block 0 Control Register

Memory control register 0A/B is used to set the memory block 0 read/write timing and synchronous/asynchronous mode through software.

Memory control register 0A

Register symbol: MEMCTR0A

Note: For the external memory access timing charts, refer to section 8.13, ???External Memory Space Access (Non- DRAM Spaces).???

Note: nfr = MCLK frequency/SYSCLK frequency

8-8

Bus Controller (BC)

The bus width is the bus width (8 bits or 16 bits) that accords with the mode specified by the MMOD1 and 0 pins and the EXMOD1 and 0 pins.

Note: For details on the setting of the MMOD1 and 0 pins and the EXMOD1 and 0 pins, refer to section 8.9, "Mode Settings."

8-9

Bus Controller (BC)

8.6.2 Memory Block 1 Control Register

Memory control register 1A/B is used to set the memory block 1 read/write timing, synchronous/asynchronous mode, DRAM mode, page mode, and bus width through software.

Note: For the external memory access timing charts, refer to section 8.13, ???External Memory Space Access (Non- DRAM Spaces).???

For the timing charts when using DRAM, refer to section 8.14, ???External Memory Space Access (DRAM Spaces).???

When not using DRAM (Memory control register 1B B1DRAM = 0)

Note: nfr = MCLK frequency/SYSCLK frequency

8-10

Bus Controller (BC)

When using DRAM (Memory control register 1B B1DRAM = 1)

Note: When performing ICE trace/emulation in software page mode, set the CAS parameter to a value of ???5??? or higher.

8-11

Bus Controller (BC)

8-12

Bus Controller (BC)

When using DRAM (Memory control register 1B B1DRAM = 1)

The bus width is 16 bits, and synchronous mode is set.

8-13

Bus Controller (BC)

8.6.3 Memory Block 2 Control Register

Memory control register 2A/B is used to set the memory block 2 read/write timing, synchronous/asynchronous mode, fixed wait/handshaking mode, DRAM mode, page mode, and bus width through software.

Note: For the external memory access timing charts, refer to section 8.13, ???External Memory Space Access (Non- DRAM Spaces).???

For the timing charts when using DRAM, refer to section 8.14, ???External Memory Space Access (DRAM Spaces).???

When using fixed wait mode and not using DRAM (Memory control register 2B B2DRAM = 0, B2WM = 0)

Note: nfr = MCLK frequency/SYSCLK frequency

8-14

Bus Controller (BC)

When using handshaking mode (Memory control register 2B B2DRAM = 0, B2WM = 1)

Note: When performing ICE trace/emulation in software page mode, set the CAS parameter to a value of ???5??? or higher.

8-15

Bus Controller (BC)

When using fixed wait mode and not using DRAM (Memory control register 2B B2DRAM = 0, B2WM = 0)

8-16

Bus Controller (BC)

When using handshaking mode (Memory control register 2B B2DRAM = 0, B2WM = 1)

8-17

Bus Controller (BC)

After the reset is released, block 2 is set as follows:

The bus width is 16 bits, and synchronous fixed wait mode is set.

8-18

Bus Controller (BC)

8.6.4 Memory Block 3 Control Register

Memory control register 3A/B is used to set the memory block 3 read/write timing, synchronous/asynchronous mode, fixed wait/handshaking mode, and bus width through software. However, the handshaking mode can only be set when (MCLK frequency/SYSCLK frequency) = 4.

Note: For the external memory access timing charts, refer to section 8.13, ???External Memory Space Access (Non- DRAM Spaces).???

When using fixed wait mode (Memory control register 3B B3WM = 0)

Note: nfr = MCLK frequency/SYSCLK frequency

Note: When fixed wait asynchronous mode (B3WM = 0 and B3BM = 1 in MEMCTR3B) is set, ???00??? must be set for BCS1 to 0.

8-19

Bus Controller (BC)

8-20

Bus Controller (BC)

Note: Handshaking mode can only be set when (MCLK frequency/SYSCLK frequency) = 4. If (MCLK frequency/SYSCLK frequency) = 1 or 2, set B3WM = 0 in MEMCTR3B.

After the reset is released, block 3 is set as follows:

The bus width is 16 bits, and synchronous fixed wait mode is set.

8-21

Bus Controller (BC)

8.6.5 DRAM control register

DRAM control register

Register symbol: DRAMCTR

For details on the RAS hold time, the RAS precharge cycle, the CAS pulse width, the row address setup timing, the column address output timing, and the column address setup timing, refer to memory control registers 1A/B and 2A/B.

For the timing charts when using DRAM, refer to section 8.14, ???External Memory Space Access (DRAM Spaces).???

8-22

Bus Controller (BC)

The refresh interval is the (REFCNT setting +1) multiplied by the SYSCLK cycle.

For the DRAM refresh timing, refer to section 8.14.4, ???DRAM Refresh.???

8-23

Bus Controller (BC)

8.6.7 Page Row Address Register

Page Row Address Register

Register symbol: PRAR

When DRAM software page mode is initiated (i.e., when the PE bit in memory control register 1B/2B is set to ???1???), the contents of the page row address register are output as the row address.

Set the row address in the page row address register before initiating DRAM software page mode. The row address that is set at this point should have already been subjected to the shift operation in accordance with the DRAM size.

8.6.8 Clock Control Register

For details, refer to Chapter 6, ???Clock Generator.???

8-24

Bus Controller (BC)

Notes when switching the internal clock multiplier

Be aware of the following points when setting the clock control register CKCTR and changing the internal clock multiplier.

???If external memory is accessed immediately after setting the clock control register CKCTR, the multiplier for the internal clock MCLK may change in the middle of the access, resulting in a change in the external bus timing.

The internal clock multiplier changes during an external memory access in any of the following cases:

(1)When executing a program in internal instruction memory, the internal clock multiplier changes in the event of an access initiated by an external memory access instruction that came within seven instructions after an instruction that writes to the clock control register CKCTR.

(2)When executing a program in external memory, the internal clock multiplier changes in the event of either an instruction read or an access initiated by an external memory access instruction, when either came within three instructions after an instruction that writes to the clock control register CKCTR.

(3)When interrupt processing is generated immediately after writing CKCTR and the stack pointer is pointing to the external memory space, the internal clock multiplier changes for the first write access to the stack immediately after the interrupt is accepted.

Use either of the following methods in response to the above situations:

Method 1: In situations where it does not matter if the clock multiplier changes during the external memory access

Write CKCTR after setting the bus controller for the external memory access to a value that permits external memory access with any clock multiplier before or after overwriting CKCTR.

Method 2: In situations where the clock multiplier must not change during the external memory access (limited to memory extension mode)

Overwrite CKCTR through a program in internal instruction memory, and then place at least seven instructions that do not access external memory (for example, nop instructions) after the instruction that writes CKCTR. In addition, if there is a possibility that an interrupt request may be generated immediately after the CKCTR write operation, either set the stack pointer in internal data RAM beforehand, or else prohibit the acceptance of interrupts before writing CKCTR.

Note that method 2 cannot be used in processor mode; use method 1.

8-25

Bus Controller (BC)

8.7 Space Partitioning

In extension memory mode (MMOD 1 to 0 = "LH"), the 1 GB memory space from x'80000000 to x'BFFFFFFF becomes external memory space; in processor mode (MMOD 1 to 0 = "HL"), the 2 GB memory space from x'40000000 to x'BFFFFFFF becomes external memory space. External memory space is partitioned into 4 blocks (block 0 to block 3). When any of these blocks are accessed, various signals (such as CSn) corresponding to the block in question are output. Fig. 8-7-1 shows the address format for external memory accesses, and Fig. 8-7-2 shows the memory map.

In addition, if it is necessary to extend the external memory space, extension address A23 (dual-purpose pin that is shared with CS3) can be used to extend the memory space. (There is no portion for address extension for block 3.)

00: Internal memory

01: Internal memory (when MMOD 1 to 0 = ???LH???), External memory (when MMOD 1 to 0 = ???HL???)

10:External memory

11:Access prohibited

Fig. 8-7-1 Address Format When Accessing External Memory

In addition, the features of each block are described in Table 8-7-1. The various settings for each block are made through the memory block 0 to 3 control registers and, when DRAM is connected, through the DRAM control register.

Table 8-7-1 Features of Each Block

For details, refer to the descriptions of memory control registers 0A/B, 1A/B, 2A/B, and 3A/B in section 8.6, ???Description of Registers.???

8-26

Bus Controller (BC)

Extension memory mode

x'FFFFFFFF

Internal memory space

External memory space

External memory space that is actually assigned as external memory

Fig. 8-7-2 Space Partitioning

8-27

Bus Controller (BC)

8.8 Operation Clocks

MCLK, IOCLK, and SYSCLK are used as BC operation clocks. Table 8-8-1 shows the ratio of each clock versus the oscillation input clock (OSCI).

Table 8-8-1 Frequency Ratios of BC Operation Clocks

For details, refer to Chapter 6, ???Clock Generator.???

8.9 Mode Settings

The values of external input pins MMOD1 to 0 and EXMOD1 to 0 set the external memory mode, block 0 bus width, and separate/common mode for the address pins and data pins. The various mode settings that can be made through the external pins are shown in Table 8-9-1.

Table 8-9-1 Mode Settings by the BC External Pins

* Set the bus widths for blocks 1 to 3 through their respective memory control registers.

8-28

Bus Controller (BC)

8.10 Bus Cycle

Depending on the value of the external input pin CKSEL and the internal registers, the MCLK frequency can be either 1/2, 1, 2, or 4 times the input frequency, and the IOCLK frequency can be either 1/8, 1/4, 1/2, or 1 times the input frequency. Note that SYSCLK is output with either 1/2 or 1 times the input frequency.

Table 8-10-1 Relationship between the Clock Frequency and

the Number of Cycles (CPU Cycles) Required for Access

(*1) If the store buffer is operational, the writing to internal I/O and external memory is entirely performed with 0 wait states.

(*2) In the synchronous mode, a synchronization wait of a maximum of 3 cycles or of 1 cycle is generated when the MCLK frequency is four times or two times the SYSCLK frequency, respectively.

(*3) Because the ratio of IOCLK to MCLK is always 1/4, a wait for synchronization is inserted.

8-29

Bus Controller (BC)

8.11 Store Buffer

The bus controller has one store buffer (with a 32-bit data width) built in, and is used to avoid a time penalty when conducting a store operation in internal I/O or external memory. The CPU store operation is completed storing the address, data, and access size in the store buffer, and is executed with no wait states. Writes from the store buffer to internal I/O or external memory are conducted in parallel with subsequent CPU operations. However, if there is a request from the CPU for an access to the internal I/O or external memory before the write from the store buffer is completed, execution of that request is delayed.

8-30

Bus Controller (BC)

8.12 Accessing the Internal I/O Space

Accesses to the internal I/O space (I/O register) are performed through the I/O bus, with the bus controller controlling the interface for read/write requests from the CPU. Accesses between the bus controller and the internal I/O space are executed in synchronization with IOCLK. Fig. 8-12-1 shows the timing chart when accessing the internal I/O space.

MCLK

IOCLK

I/O Bus

Address

RR

WR

DSn

I/O Bus

Data

Fig. 8-12-1 Internal I/O Space Access

During a read, the address and the read request signal (RR) are output in synchronization with the rising edge of IOCLK. After MCLK 1 cycle, the data strobe signals (DSn) are asserted, and the I/O side begins to drive the data on the data bus. During a write, the address and the write request signal (WR) are output in synchronization with the falling edge of IOCLK. After MCLK 1 cycle, the data strobe signals (DSn) are asserted, and are then negated 1/4 of an IOCLK cycle before the end of the I/O access cycle. The write is performed at the rising edge of the DSn signals.

8-31

Bus Controller (BC)

8.13 External Memory Space Access (Non-DRAM Spaces)

During an access to external memory, the BC controls the interface for the read/write request from the CPU. Table 8-13-1 lists the transactions that are supported for the external bus.

Table 8-13-1 External Bus Transaction

8-32

Bus Controller (BC)

8.13.1 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode

Setting of the various parameters for external memory access is performed in memory control registers 0 to 3, corresponding to each block. In synchronous mode, the bus access is initiated in synchronization with SYSCLK. When fixed wait insertion is specified, the bus access ends to the timing set in the memory control register.

Fig. 8-13-1 is the timing chart in the case of a ???16-bit bus with fixed wait states, in synchronous mode, in address/ data separate mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by four.???

Fig. 8-13-2 is the timing chart in the case of a ???16-bit bus with fixed wait states, in synchronous mode, in address/ data separate mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by two.???

Fig. 8-13-3 is the timing chart in the case of a ???16-bit bus with fixed wait states, in synchronous mode, in address/ data separate mode, and with the frequency of MCLK equal to that of SYSCLK.???

BCS indicates the timing during one SYSCLK cycle at which the access should start, and is expressed in terms of the number of MCLK pulses since the rising edge of SYSCLK.

Note that when writing to byte 0, WE0 is asserted and the data is output on D7 to 0, and when writing to byte 1, WE1 is asserted and the data is output on D15 to 8.

In addition, in the case of a word access (32 bits), the external access is performed twice with A[1] = "0" and A[1] = "1".

Fig. 8-13-1 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 4)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-33

Bus Controller (BC)

Fig. 8-13-2 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2)

For details on the various timing settings, refer to the description of the memory control register in section 8.6,

Fig. 8-13-3 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-34

Bus Controller (BC)

8.13.216-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode

When using handshaking, bus access starts once synchronization with SYSCLK is achieved, and after the data acknowledge signal (DK) is asserted, 2 MCLK cycles are consumed by the BC internally and then the access is completed according to the specified parameters.

The various parameters for external memory access are set in memory control registers 2 and 3, corresponding to each block.

Handshaking can only be set in synchronous mode.

Fig. 8-13-4 is the timing chart in the case of a ???16-bit bus with handshaking, in synchronous mode, in address/data separate mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by four.???

Fig. 8-13-5 is the timing chart in the case of a ???16-bit bus with handshaking, in synchronous mode, in address/data separate mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by two.???

Fig. 8-13-6 is the timing chart in the case of a ???16-bit bus with handshaking, in synchronous mode, in address/data separate mode, and with the frequency of MCLK equal to that of SYSCLK.???

The DK signal connected to the microcontroller should be input so as to be asserted from point EA+DW onward, and is negated before the next access.

Note that when writing to byte 0, WE0 is asserted and the data is output on D7 to 0, and when writing to byte 1, WE1 is asserted and the data is output on D15 to 8.

In addition, in the case of a word access (32 bits), the external access is performed twice with A[1] = "0" and A[1] = "1".

Note: Setting handshaking is prohibited if synchronous mode has not been set.

Note: If handshaking mode is set for memory block 3, the only settings that are permitted are those in which MCLK is equal to SYSCLK multiplied by 4. Any setting in which MCLK is only twice SYSCLK, or in which the two frequencies are equal, is prohibited.

Fig. 8-13-4 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 4)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-35

Bus Controller (BC)

Fig. 8-13-5 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

Fig. 8-13-6 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-36

Bus Controller (BC)

8.13.316-bit Bus in Asynchronous Mode and in Address/Data Separate Mode

Asynchronous mode is used for accessing external memory at high speed; the address signals, CSn signals, etc., are output asynchronously with the SYSCLK but in synchronization with the internal MCLK. In asynchronous mode, accesses are all by fixed wait insertion.

Fig. 8-13-7 is the timing chart in the case of a ???16-bit bus in asynchronous mode, in address/data separate mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by four.???

Fig. 8-13-8 is the timing chart in the case of a ???16-bit bus in asynchronous mode, in address/data separate mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by two.???

Fig. 8-13-9 is the timing chart in the case of a ???16-bit bus in asynchronous mode, in address/data separate mode, and with the frequency of MCLK equal to that of SYSCLK.???

During a read, the RE signal is asserted at EA x MCLK after the start of the bus cycle. During a write, the WE signal is asserted at EA x MCLK after the start of the bus cycle.

Note that when writing to byte 0, WE0 is asserted and the data is output on D7 to 0, and when writing to byte 1, WE1 is asserted and the data is output on D15 to 8.

In addition, in the case of a word access (32 bits), the external access is performed twice with A[1] = "0" and A[1] = "1".

Fig. 8-13-7 Access Timing on a 16-bit Bus in Asynchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 4)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-37

Bus Controller (BC)

Fig. 8-13-8 Access Timing on a 16-bit Bus in Asynchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2)

For details on the various timing settings, refer to the description of the memory control register in section 8.6,

Fig. 8-13-9 Access Timing on a 16-bit Bus in Asynchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-38

Bus Controller (BC)

8.13.4 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode

8-bit bus mode is set for block 0 by setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, and for blocks 1 to 3 by setting the BnBW bit to "0" in the corresponding memory control register. In 8-bit bus mode, half-word access (16 bits) is performed by means of two external accesses, with A[0] = "0" for the low-order byte and A[0] = "1" for the high-order byte. Word access (32 bits) is performed by means of four accesses, with A[1:0] = "00", A[1:0] = "01", A[1:0] = "10", and A[1:0] = "11", starting from the low-order side. Note that the low- order 8 bits (D7 to 0) are used for the data bus.

In synchronous mode, the bus access starts in synchronization with SYSCLK, and when fixed wait states are inserted, the access ends according to the timing that was set in the memory control register.

The various parameters for external memory access are set in memory control registers 0 to 3, corresponding to each block.

Fig. 8-13-10 is the timing chart in the case of a half-word access using an ???8-bit bus with fixed wait states, in synchronous mode, in address/data separate mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by four.???

Fig. 8-13-11 is the timing chart in the case of a half-word access using an ???8-bit bus with fixed wait states, in synchronous mode, in address/data separate mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by two.???

Fig. 8-13-12 is the timing chart in the case of a half-word access using an ???8-bit bus with fixed wait states, in synchronous mode, in address/data separate mode, and with the frequency of MCLK equal to that of SYSCLK.??? Note that when writing, WE0 is asserted and the data is output on D7 to 0.

Note: For details on the mode settings, refer to Table 8-9-1, ???Mode Settings by the BC External Pins.???

Fig. 8-13-10 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 4)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-39

Bus Controller (BC)

Fig. 8-13-11 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2)

For details on the various timing settings, refer to the description of the memory control register in section 8.6,

Fig. 8-13-12 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-40

Bus Controller (BC)

8.13.5 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode

8-bit bus mode is set for blocks 2 and 3 by setting the BnBW bit to ???0??? in the corresponding memory control register. In 8-bit bus mode, half-word access (16 bits) is performed by means of two external accesses, with A[0] = "0" for the low-order byte and A[0] = "1" for the high-order byte. Word access (32 bits) is performed by means of four accesses, with A[1:0] = "00", A[1:0] = "01", A[1:0] = "10", and A[1:0] = "11", starting from the low-order side. Note that the low-order 8 bits (D7 to 0) are used for the data bus.

When using handshaking, bus access starts once synchronization with SYSCLK is achieved, and after the data acknowledge signal (DK) is asserted, 2 MCLK cycles are consumed by the BC internally and then the access is completed according to the specified parameters.

The various parameters for external memory access are set in memory control registers 2 and 3, corresponding to each block.

Handshaking can only be set in synchronous mode.

Fig. 8-13-13 is the timing chart in the case of a half-word access using an ???8-bit bus with handshaking, in synchronous mode, in address/data separate mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by four.???

Fig. 8-13-14 is the timing chart in the case of a half-word access using an ???8-bit bus with handshaking, in synchronous mode, in address/data separate mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by two.???

Fig. 8-13-15 is the timing chart in the case of a half-word access using an ???8-bit bus with handshaking, in synchronous mode, in address/data separate mode, and with the frequency of MCLK equal to that of SYSCLK.???

The DK signal connected to the microcontroller should be input so as to be asserted from point EA+DW onward, and is negated before the next access.

Note that when writing, WE0 is asserted and the data is output on D7 to 0.

Note: If handshaking mode is set for memory block 3, the only settings that are permitted are those in which MCLK is equal to SYSCLK multiplied by 4. Any setting in which MCLK is only twice SYSCLK, or in which the two frequencies are equal, is prohibited.

8-41

Bus Controller (BC)

(a) Read Timing

MCLK

SYSCLK

: Undefined

(b)Write Timing

Fig. 8-13-13 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 4)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-42

Bus Controller (BC)

Fig. 8-13-14 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-43

Bus Controller (BC)

Fig. 8-13-15 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-44

Bus Controller (BC)

8.13.68-bit Bus in Asynchronous Mode and in Address/Data Separate Mode

8-bit bus mode is set for block 0 by setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, and for blocks 1 to 3 by setting the BnBW bit to ???0??? in the corresponding memory control register. In 8-bit bus mode, half-word access (16 bits) is performed by means of two external accesses, with A[0] = "0" for the low-order byte and A[0] = "1" for the high-order byte. Word access (32 bits) is performed by means of four accesses, with A[1:0] = "00", A[1:0] = "01", A[1:0] = "10", and A[1:0] = "11", starting from the low-order side. Note that the low- order 8 bits (D7 to 0) are used for the data bus.

Asynchronous mode is used for accessing external memory at high speed; the address signals, CS signals, etc., are output asynchronously with SYSCLK but in synchronization with the internal MCLK. In asynchronous mode, accesses are all by fixed wait insertion.

Fig. 8-13-16 is the timing chart in the case of a half-word access using an ???8-bit bus in asynchronous mode, in address/data separate mode.???

Note that when writing, WE0 is asserted and the data is output on D7 to 0.

Note: For details on the mode settings, refer to Table 8-9-1, ???Mode Settings by the BC External Pins.???

Fig. 8-13-16 Access Timing on a 8-bit Bus, in Asynchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 4)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-45

Bus Controller (BC)

8.13.716-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode

By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 0 to 3 use common pins for the memory address and memory data signals (pins ADM15 to 0). In synchronous mode, the bus access starts in synchronization with SYSCLK, and when fixed wait states are inserted, the access ends according to the timing that was set in the memory control register. The various parameters for external memory access are set in memory control registers 0 to 3, corresponding to each block.

BCS indicates the timing during one SYSCLK cycle at which the access should start, and is expressed in terms of the number of MCLK pulses since the rising edge of SYSCLK.

Fig. 8-13-17 is the timing chart in the case of a ???16-bit bus with fixed wait states, in synchronous mode, in address/ data multiplex mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by four.???

Fig. 8-13-18 is the timing chart in the case of a ???16-bit bus with fixed wait states, in synchronous mode, in address/ data multiplex mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by two.???

Fig. 8-13-19 is the timing chart in the case of a ???16-bit bus with fixed wait states, in synchronous mode, in address/ data multiplex mode, and with the frequency of MCLK equal to that of SYSCLK.???

As shown in each timing chart, the ADM15 to 0 pins go to ???Hi-Z??? or the undefined output state while CSn is negated in address/data multiplex mode. When the bus authority is released, the ADM15 to 0 pins are either pulled up or go to ???Hi-Z???, depending on the setting of the I/O port output mode register.

Note that when writing to byte 0, WE0 is asserted and the data is output on ADM7 to 0, and when writing to byte 1, WE1 is asserted and the data is output on ADM15 to 8.

Note: For details on the mode settings, refer to Table 8-9-1, ???Mode Settings by the BC External Pins.???

Note: ???0??? (low level) is output on pins A23 to 16 (A23 also serves as CS3) while the ADM15 to 0 pins function as data pins. Therefore, refer to 3. in section 8.16, ???Cautions,??? regarding the use of these pins.

Fig. 8-13-17 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 4)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

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Bus Controller (BC)

Fig. 8-13-18 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 2)

For details on the various timing settings, refer to the description of the memory control register in section 8.6,

Fig. 8-13-19 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-47

Bus Controller (BC)

8.13.816-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode

By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 2 and 3 use multiplex pins for the memory address and memory data signals (pins ADM15 to 0).

When using handshaking, bus access starts once synchronization with SYSCLK is achieved, and after the data acknowledge signal (DK) is asserted, 2 MCLK cycles are consumed by the BC internally and then the access is completed according to the specified parameters.

The various parameters for external memory access are set in memory control registers 2 and 3, corresponding to each block.

Fig. 8-13-20 is the timing chart in the case of a ???16-bit bus with handshaking, in address/data multiplex mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by four.???

Fig. 8-13-21 is the timing chart in the case of a ???16-bit bus with handshaking, in address/data multiplex mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by two.???

Fig. 8-13-22 is the timing chart in the case of a ???16-bit bus with handshaking, in address/data multiplex mode, and with the frequency of MCLK equal to that of SYSCLK.???

As shown in each timing chart, the ADM15 to 0 pins go to ???Hi-Z??? or the undefined output state while CSn is negated in address/data multiplex mode. When the bus authority is released, the ADM15 to 0 pins are either pulled up or go to ???Hi-Z???, depending on the setting of the I/O port output mode register.

The DK signal connected to the microcontroller should be input so as to be asserted from point EA+DW onward, and is negated before the next access.

Note that when writing to byte 0, WE0 is asserted and the data is output on ADM7 to 0, and when writing to byte 1, WE1 is asserted and the data is output on ADM15 to 8.

In addition, in the case of a word access (32 bits), the external access is performed twice with A[1] = ???0??? and A[1] = ???1???.

Note: For details on the mode settings, refer to Table 8-9-1, ???Mode Settings by the BC External Pins.???

Note: If handshaking mode is set for memory block 3, the only settings that are permitted are those in which MCLK is equal to SYSCLK multiplied by 4. Any setting in which MCLK is only twice SYSCLK, or in which the two frequencies are equal, is prohibited.

Note: ???0??? (low level) is output on pins A23 to 16 (A23 also serves as CS3) while the ADM15 to 0 pins function as data pins. Therefore, refer to 3. in section 8.16, ???Cautions,??? regarding the use of these pins.

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Bus Controller (BC)

Fig. 8-13-20 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 4)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

Fig. 8-13-21 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 2)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-49

Bus Controller (BC)

Fig. 8-13-22 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-50

Bus Controller (BC)

8.13.9 16-bit Bus in Asynchronous Mode and in Address/Data Multiplex Mode

By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 0 to 3 use multiplex pins for the memory address and memory data signals (pins ADM15 to 0).

Asynchronous mode is used for accessing external memory at high speed; the address signals, CS signals, etc., are output asynchronously with SYSCLK but in synchronization with the internal MCLK. In asynchronous mode, accesses are all by fixed wait insertion.

The various parameters for external memory access are set in memory control registers 0 to 3, corresponding to each block.

Fig. 8-13-23 is the timing chart in the case of a ???16-bit bus in asynchronous mode, in address/data multiplex mode.??? As shown in the timing chart, the ADM15 to 0 pins go to ???Hi-Z??? or the undefined output state while CSn is negated in address/data multiplex mode. When the bus authority is released, the ADM15 to 0 pins are either pulled up or go to ???Hi-Z???, depending on the setting of the I/O port output mode register.

Note that when writing to byte 0, WE0 is asserted and the data is output on ADM7 to 0, and when writing to byte 1, WE1 is asserted and the data is output on ADM15 to 8.

In addition, in the case of a word access (32 bits), the external access is performed twice with A[1] = ???0??? and A[1] = ???1???.

Note: For details on the mode settings, refer to Table 8-9-1, ???Mode Settings by the BC External Pins.???

Note: ???0??? (low level) is output on pins A23 to 16 (A23 also serves as CS3) while the ADM15 to 0 pins function as data pins. Therefore, refer to 3. in section 8.16, ???Cautions,??? regarding the use of these pins.

Fig. 8-13-23 Access Timing on a 16-bit Bus in Asynchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 4)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-51

Bus Controller (BC)

8.13.10 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode

By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 0 to 3 use multiplex pins for the memory address and memory data signals (pins ADM15 to 0).

8-bit bus mode is set for block 0 by setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, and for blocks 1 to 3 by setting the BnBW bit to ???0??? in the corresponding memory control register. In 8-bit bus mode, half-word access (16 bits) is performed by means of two external accesses, with A[0] = ???0??? for the low-order byte and A[0] = ???1??? for the high-order byte. Note that the low-order 8 bits (D7 to 0) are used for the data bus. Word access (32 bits) is performed by means of four accesses, with A[1:0] = ???00???, A[1:0] = ???01???, A[1:0] = ???10???, and A[1:0] = ???11???, starting from the low-order side.

In synchronous mode, the bus access starts in synchronization with SYSCLK, and when fixed wait states are inserted, the access ends according to the timing that was set in the memory control register.

The various parameters for external memory access are set in memory control registers 0 to 3, corresponding to each block.

Fig. 8-13-24 is the timing chart in the case of a half-word access using an ???8-bit bus with fixed wait states, in synchronous mode, in address/data multiplex mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by four.???

Fig. 8-13-25 is the timing chart in the case of a half-word access using an ???8-bit bus with fixed wait states, in synchronous mode, in address/data multiplex mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by two.???

Fig. 8-13-26 is the timing chart in the case of a half-word access using an ???8-bit bus with fixed wait states, in synchronous mode, in address/data multiplex mode, and with the frequency of MCLK equal to that of SYSCLK.??? As shown in each timing chart, the ADM15 to 0 pins go to ???Hi-Z??? or the undefined output state while CSn is negated in address/data multiplex mode. When the bus authority is released, the ADM15 to 0 pins are either pulled up or go to ???Hi-Z???, depending on the setting of the I/O port output mode register.

Note that when writing, WE0 is asserted and the data is output on ADM7 to 0.

Note: For details on the mode settings, refer to Table 8-9-1, Mode Settings by the BC External Pins.???

Note: ???0??? (low level) is output on pins A23 to 16 (A23 also serves as CS3) while the ADM15 to 0 pins function as data pins. Therefore, refer to 3. in section 8.16, ???Cautions,??? regarding the use of these pins.

8-52

Bus Controller (BC)

(b) Write Timing

Fig. 8-13-24 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 4)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-53

Bus Controller (BC)

(a) Read Timing

(b)Write Timing

Fig. 8-13-25 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 2)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

When BCE for the low-order bits is completed at the rising edge of SYSCLK, the bus cycle for the high-order bits begins at the same rising edge of SYSCLK.

8-54

Bus Controller (BC)

(a) Read Timing

(b) Write Timing

Fig. 8-13-26 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-55

Bus Controller (BC)

8.13.118-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode

By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 2 and 3 use multiplex pins for the memory address and memory data signals (pins ADM15 to 0).

8-bit bus mode is set for blocks 2 and 3 by setting the BnBW bit to ???0??? in the corresponding memory control register.

In 8-bit bus mode, half-word access (16 bits) is performed by means of two external accesses, with A[0] = "0" for the low-order byte and A[0] = ???1??? for the high-order byte. Note that the low-order 8 bits (D7 to 0) are used for the data bus. Word access (32 bits) is performed by means of four accesses, with A[1:0] = ???00???, A[1:0] = ???01???, A[1:0] = ???10???, and A[1:0] = ???11???, starting from the low-order side.

With handshaking, bus access commences in synchronization with SYSCLK, and after the data acknowledge signal (DK) is asserted, two MCLK cycles are consumed by the BC internally, and then access is completed as per the designated parameters.

The various parameters for external memory access are set in memory control registers 2 and 3, corresponding to each block.

Fig. 8-13-27 is the timing chart in the case of a half-word access using an ???8-bit bus with handshaking, in address/ data multiplex mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by four.???

Fig. 8-13-28 is the timing chart in the case of a half-word access using an ???8-bit bus with handshaking, in address/ data multiplex mode, and with the frequency of MCLK equal to that of SYSCLK multiplied by two.???

Fig. 8-13-29 is the timing chart in the case of a half-word access using an ???8-bit bus with handshaking, in address/ data multiplex mode, and with the frequency of MCLK equal to that of SYSCLK.???

As shown in each timing chart, the ADM15 to 0 pins go to ???Hi-Z??? or the undefined output state while CSn is negated in address/data multiplex mode. When the bus authority is released, the ADM15 to 0 pins are either pulled up or go to ???Hi-Z???, depending on the setting of the I/O port output mode register.

The DK signal connected to the microcontroller should be input so as to be asserted from point EA+DW onward, and is negated before the next access.

Note that when writing, WE0 is asserted and the data is output on ADM7 to 0.

Note: For details on the mode settings, refer to Table 8-9-1, ???Mode Settings by the BC External Pins.???

Note: If handshaking mode is set for memory block 3, the only settings that are permitted are those in which MCLK is equal to SYSCLK multiplied by 4. Any setting in which MCLK is only twice SYSCLK, or in which the two frequencies are equal, is prohibited.

Note: ???0??? (low level) is output on pins A23 to 16 (A23 also serves as CS3) while the ADM15 to 0 pins function as data pins. Therefore, refer to 3. in section 8.16, ???Cautions,??? regarding the use of these pins.

8-56

Bus Controller (BC)

(b) Write Timing

Fig. 8-13-27 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and in Address/ Data Multiplex Mode (MCLK = SYSCLK multiplied by 4)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-57

Bus Controller (BC)

(a) Read Timing

(b)Write Timing

Fig. 8-13-28 Access Timing on a 8-bit Bus with Handshaking in Synchronous Mode and in Address/ Data Multiplex Mode (MCLK = SYSCLK multiplied by 2)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-58

Bus Controller (BC)

(a)Read Timing

(b)Write Timing

Fig. 8-13-29 Access Timing on a 8-bit Bus with Handshaking in Synchronous Mode and in Address/ Data Multiplex Mode (MCLK = SYSCLK)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-59

Bus Controller (BC)

8.13.128-bit Bus in Asynchronous Mode and in Address/Data Multiplex Mode

By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 0 to 3 use multiplex pins for the memory address and memory data signals (pins ADM15 to 0).

8-bit bus mode is set for block 0 by setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, and for blocks 1 to 3 by setting the BnBW bit to ???0??? in the corresponding memory control register. In 8-bit bus mode, half-word access (16 bits) is performed by means of two external accesses, with A[0] = ???0??? for the low-order byte and A[0] = ???1??? for the high-order byte. Word access (32 bits) is performed by means of four accesses, with A[1:0] = ???00???, A[1:0] = ???01???, A[1:0] = ???10???, and A[1:0] = ???11???, starting from the low-order side. Note that the low-order 8 bits (D7 to 0) are used for the data bus.

Asynchronous mode is used for accessing external memory at high speed; the address signals, CSn signals, etc., are output asynchronously with SYSCLK but in synchronization with the internal MCLK. In asynchronous mode, accesses are all by fixed wait insertion.

The various parameters for external memory access are set in memory control registers 0 to 3, corresponding to each block.

Fig. 8-13-30 is the timing chart in the case of a half-word access using an ???8-bit bus in asynchronous mode, in address/data multiplex mode.???

As shown in each timing chart, the ADM15 to 0 pins go to ???Hi-Z??? or the undefined output state while CSn is negated in address/data multiplex mode. When the bus authority is released, the ADM15 to 0 pins are either pulled up or go to ???Hi-Z???, depending on the setting of the I/O port output mode register.

Note that when writing, WE0 is asserted and the data is output on ADM7 to 0.

Note: For details on the mode settings, refer to Table 8-9-1, ???Mode Settings by the BC External Pins.???

Note: ???0??? (low level) is output on pins A23 to 16 (A23 also serves as CS3) while the ADM15 to 0 pins function as data pins. Therefore, refer to 3. in section 8.16, ???Cautions,??? regarding the use of these pins.

8-60

Bus Controller (BC)

(a) Read Timing

(b) Write Timing

Fig. 8-13-30 Access Timing on a 8-bit Bus in Asynchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 4)

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-61

Bus Controller (BC)

8.14 External Memory Space Access (DRAM Space)

8.14.1 DRAM Space

Blocks 1 and 2 can be used as DRAM space by setting the BnDRAM bits in memory control registers 1B/2B and setting the DRAME bit in DRAM control register. The DRAM bus cycle is always not synchronized the external clock (but is synchronized with MCLK), and performs address multiplexed output, RAS/CAS signal output, etc.

Note: When common pins are used for addresses and data, DRAM cannot be supported.

The RAS/CAS signal output timing can be set through software in the DRAM control register and memory control registers 1A/B and 2A/B.

Fig. 8-14-1 shows the DRAM access timing chart.

Note: For details on the timing settings, refer to section 8.6, ???Description of Registers.???

Fig. 8-14-1 DRAM Access Timing Chart

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-62

Bus Controller (BC)

??? Minimum value for the RAS Precharge interval

When consecutive DRAM accesses are performed, the RAS precharge interval is shortest when performing an access of type (1) or (2) below while the PAGE bit is set to ???0??? in the DRAM control register:

(1)Word/half-word access while the bus width is set to 8 bits

(2)Word access while the bus width is set to 16 bits

Because the minimum value for the RAS precharge interval is:

RP + ASR

as shown in Fig. 8-14-2, set the parameters RP and ASR to values that will satisfy the DRAM requirements. Note that the minimum value that can be set for both RP and ASR is 1.

Fig. 8-14-2 Case Where the RAS Precharge Interval is at Its Minimum (Example Where RP = 1 and ASR = 1)

8-63

Bus Controller (BC)

??? 2 WE control/2 CAS control

DRAM that permits byte/word control can be supported by selecting either one of the following two methods:

???2 WE control: The two pins WE1 and WE0 are used for byte/word control.

???2 CAS control: The two pins DCAS1 and DCAS0 are used for byte/word control.

Fig. 8-14-3 illustrates an example of a write using 2 WE control, and Fig. 8-14-4 illustrates an example of a write using 2 CAS control.

MCLK

RASn

CAS

WE1

WE0

Dn

Fig. 8-14-3 Example of an 8-bit Data Write Using 2 WE Control (16-bit Bus Width)

MCLK

An Row Column Row Column

RASn

DCAS1

DCAS0

DWE

Dn

Fig. 8-14-4 Example of an 8-bit Data Write Using 2 CAS Control (16-bit Bus Width)

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Bus Controller (BC)

8.14.2DRAM page mode

If the PAGE bit in the DRAM control register is set to ???1???, page mode access is enabled, making high-speed access in page mode possible for following accesses to DRAM.

(1)Word/half-word access when the bus width is set to 8 bits

(2)Word access when the bus width is set to 16 bits

Fig. 8-14-5 shows the page mode read timing and write timing.

(b) Write Timing

Fig. 8-14-5 DRAM Page Mode Read/Write Timing

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

8-65

Bus Controller (BC)

8.14.3Software Page Mode

Software page mode is a mode that forcibly initiates page mode by setting the control register. Operation within software page mode is as described below. Refer to Fig. 8-14-6.

???When the mode is initiated, the contents of PRAR are output as the row address.

???While the mode is in effect, RASn for the block corresponding to the memory control register that initiated the mode is maintained in the asserted state.

???After the mode is initiated, external accesses are all processed as column address accesses. In this case, the ASC and CAS parameters of the block in question are guaranteed. In addition, the RE/WE signal has the same waveform as in a normal DRAM access.

???The CAS precharge interval depends on the timing of the external access. Note that the shortest CAS precharge interval is ASC + 3 for a read, or ASC + 1 for a write. As an example, Fig. 8-14-6 illustrates the case where the CAS precharge interval is at its shortest.

???(CAO + 1) MCLK pulses are guaranteed for the row address output interval. (???CAO??? is a parameter.)

???The parameter ASR for the block in question is guaranteed for the assertion of RASn.

The procedure for executing this mode is described below:

???Preparation for mode initiation

(1)Set the row address in the row address register PRAR.

Set a row address that has already been shifted according to the DRAM size.

(2)Set DRAMCTR.

Be certain to set the PAGE bit to ???1??? and the DRAME bit to ???1???.

???Mode initiation

Once the PE bit of the memory control register for the block in question (block 1 or 2) is set to ???1???, software page mode access begins after the register writing operation has been completed.

???Mode termination

Once the PE bit of the memory control register for the block in question (block 1 or 2) is set to ???0???, software page mode is terminated after the register writing operation has been completed.

Note: When performing ICE trace/emulation in software page mode, set the CAS parameter to ???5??? or higher.

8-66

Bus Controller (BC)

(a) Read Timing

(b) Write Timing

Fig. 8-14-6 Software Page Mode Read/Write Timing

For details on the various timing settings, refer to the description of the memory control register in section 8.6, ???Description of Registers.???

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Bus Controller (BC)

[Restrictions on Use]

(1)While software page mode is in effect, external access outside of the block in question is prohibited.

Cancel software page mode before accessing an external memory space other than the block for which software page mode is set.

(2)While software page mode is in effect, the bus will not be released, regardless of any accesses to DRAM, even if the bus request signal BR is asserted.

If it is necessary to accept the bus request signal BR while data is being transferred in software page mode, partition the volume of data that is to be transferred in software page mode. Then, the program should temporarily release software page mode once after the transfer of each block of data is completed. If the bus request signal BR is being asserted when the software page mode is released, the bus grant signal BG is asserted, and the bus is released.

(3)The DRAM refresh cycle is not performed while software page mode is in effect.

If DRAM refresh is necessary, temporarily release DRAM software page mode once within each refresh cycle.

(4)While software page mode is in effect, any access that writes a ???1??? to the PE bit of the memory control register that initiated the mode is prohibited. (RASn remains asserted, and software page mode starts over again from the output of the row address.)

8.14.4DRAM refresh

If the REFE bit in the DRAM control register is set, CAS-before-RAS refresh is performed at the interval set by the refresh count register. Fig. 8-14-7 illustrates the refresh operation concept. The refresh interval is the product of the value of the REFCNT in the refresh count register. If the REFE bit in the DRAM control register is set, the refresh count register operates as a down-counter, and the refresh count value is counted from REFC, the value of REFCNT, to 0. The refresh operation is executed once in an idle external bus cycle during the period while the refresh count value is counted down from REFC to 0. If, due to a serial interface access or other such operation, there is no idle external bus cycle before the refresh count value reaches 0, then a refresh cycle is inserted right after the bus cycle that is being executed at the moment the refresh count value reaches 0 is completed.

Fig. 8-14-8 shows the timing of a CAS-before-RAS refresh operation.

For details on the DRAM refresh interval setting, refer to section 8.6.6, "Refresh Count Register."

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Bus Controller (BC)

Refresh count value

REFE bit is set

For details on the ASR and RP settings, refer to the explanations in section 8.6.2, ???Memory Block 1 Control Register,??? and section 8.6.3, ???Memory Block 2 Control Register.???

For details on the RERS setting, refer to the explanation in section 8.6.5, ???DRAM Control Register.???

Note: When using blocks 1 and 2 as DRAM space simultaneously, the timing (ASR, RP) set in memory control register 1A/B is used as the refresh timing for both block 1 and block 2.

8-69

Bus Controller (BC)

8.15 Bus Arbitration

In this microcontroller, bus arbitration is implemented through the bus authority request signal (BR) and the bus authority release signal (BG).

If an external device asserts the BR signal, then once the current bus access that is being executed is completed, the BG signal is asserted and the bus authority is released to the external device. Once the BR signal is negated, this LSI negates the BG signal in order to re-acquire the bus authority. However, if a refresh request is generated by the DRAM control circuit within this microcontroller while the bus authority has been released to an external device, this LSI negates the BG signal and requests the bus authority back form the external device. The external device then negates the BR signal in response, and the refresh is executed.

Note that bus arbitration is performed in synchronization with SYSCLK.

Fig. 8-15-1 to 3 show the timing for releasing the bus authority to an external device, and Fig. 8-15-4 shows the timing when a refresh request is generated while the bus authority has been released. An, CSn, RE, WEn, RASn, and CAS (and, if there is output on other pins related to the BC, those signals as well) are always output by this microcontroller which has the bus authority (BG = ???H???)* 1, and go to ???Hi-Z??? (high impedance) when the bus authority is released (BG = ???L???).

Note that the execution of internal I/O space access requests and external memory space access requests by the CPU while the bus authority is being released are delayed until the bus authority release is completed.

Accesses which can be executed while the bus authority is being released and accesses which are delayed until bus authority release is completed are listed below.

(1)Accesses which can be executed while the bus authority is being released

-Internal data RAM space accesses by the CPU

-Internal ROM/internal flash memory space accesses by the CPU

(2)Accesses which are delayed until bus authority release is completed

-Internal I/O space accesses by the CPU

-External memory space accesses by the CPU

Note: For details on pins related to the BC and their statuses, refer to Table 8-5-2, ???Operating Status of Pins Concerning BC.???

*1) However, if a bus access is executed immediately before the bus authority is released to an external device, the An signal, etc., may go to high impedance, even if BG = ???H???, depending on the timing of the completion of that bus access. Specifically, the An and other signals are placed in the high impedance state at the following timing relative to the timing at which the BG signal is asserted:

When nfr = 4: Simultaneously, or 1, 2, or 3 MCLK cycles before

When nfr = 2: Simultaneously, or 1 MCLK cycle before

Here, nfr = MCLK frequency/SYSCLK frequency

8-70

Bus Controller (BC)

Fig. 8-15-1 Bus Arbitration Timing 1

(Bus Authority Release/Bus Authority Acquisition, nfr = 4)

8-71

Bus Controller (BC)

Fig. 8-15-3 Bus Arbitration Timing 3

(Bus Authority Release/Bus Authority Acquisition, nfr = 1)

Fig. 8-15-4 Bus Arbitration Timing 4

(Refresh Request Generated While Bus Authority Has Been Released)

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Bus Controller (BC)

8.16 Cautions

These cautions concern the BC. These cautions must be heeded, since failure to do so may result in misoperation.

1.Do not change the contents of the relevant memory control register and the DRAM control register while accessing external memory space, except when software page mode is not in effect.

2.Do not overwrite the refresh counter register while the REFE bit is ???1??? in the DRAM control register.

3.???0??? is output on pins A23* to 16 when pins ADM15 to 0 are operating as data pins in address/data multiplex mode, as shown in the diagram below; as a result, in order to use pins A23* to 16 while pins ADM15 to 0 are operating as data pins, it is necessary to latch the output on pins A23* to 16 with the address strobe AS.

*: A23 also serves as CS3.

: Undefined

: Undefined or Hi-Z

* : A23 also serves as CS3

Fig. 8-16-1 Example of Address Pin Usage in Address/Data Multiplex Mode

4.When entering the stop mode, the output mode of pins ADM15 to 0 is undefined. Therefore, when pins ADM15 to 0 are being pulled up according to the I/O port output mode register setting, the pull-up setting for pins ADM15 to 0 should be released before entering the stop mode in order to avoid power consumption in the stop mode due to the pull-up resistance.

Note: For details on the output mode register settings, refer to Chapter 15, ???I/O Ports.???

5.Interrupts are prohibited and the bus is locked (occupied by the CPU) when executing BSET or BCLR, however, if a BSET or BCLR instruction is executed during program execution in external memory, a bus authority release due to an external bus request may be interposed between the data read and data write by the BSET or BCLR instruction.

If the atomic bus cycles (i.e. bus lock) of the BSET or BCLR instruction need to be guaranteed in a system that uses multiple processors, either of the following measures should be taken.

1. A program in which a BSET or BCLR instruction is executed should be placed in internal memory.

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Bus Controller (BC)

_____

2. Designate the bus authority request pin (BR) as a general-purpose input port, and the bus authority release

_____

pin (BG) as a general-purpose output port, for instance, so that bus requests cannot be accepted during execution of a BSET or BCLR instruction.

8-74

Interrupt Controller

9.1 Overview

The interrupt controller processes non-maskable interrupts and level interrupts (internal interrupts and external interrupts).

For external pins, the microcontroller has eight external interrupt pins and one non-maskable interrupt pin.

9.2 Features

??? Up to four interrupt requests can be accepted by each group.

??? External pin interrupt conditions: Positive edge, negative edge, "H" level, "L" level

Recovery from STOP, HALT or SLEEP mode is possible by means of an external pin interrupt

9.3 System Diagram

Fig. 9-3-1 System Diagram

9-2

Interrupt Controller

9.4 Block Diagram

Interrupt control register address

The interrupt level can be set separately for each group. (However, GROUP 0 and GROUP 1 are non-maskable.)

Fig. 9-4-1 Block Diagram 1

9-3

Interrupt Controller

Interrupt control register address

Fig. 9-4-2 Block Diagram 2

9-4

Interrupt Controller

Interrupt control register address

Fig. 9-4-3 Block Diagram 3

9-5

Interrupt Controller

9.5 Description of Registers

This interrupt controller includes an interrupt control registers, an interrupt accepted group register, and an external interrupt condition specification register.

Table 9-5-1 lists the interrupt controller registers.

9-6

Interrupt Controller

The method of clearing flag differs according to the interrupt request flags.

1. External non-maskable interrupt request flag (NMIF) and Watchdog timer overflow interrupt request flag (WDIF) After a non-maskable interrupt is accepted, these flags can be cleared by writing to the non-maskable interrupt control register (NMICR).

When a flag is set to ???1???, write a ???1??? to the flag to clear it.

The relationship between the flag status, the data written to the flag, and the new flag status after the data is written is shown in the table below.

Note: A non-maskable interrupt cannot be generated through software. 2. System error interrupt request flag (SYSEF)

This flag cannot be cleared by writing to the non-maskable interrupt control register (NMICR).

_______

This flag can be cleared by generating a reset interrupt by setting the RST pin to "L" level or by the self-reset, which is generated by writing to the reset control register (RSTCTR) of the watchdog timer.

Note*:

Normally, the serial debugger uses non-maskable interrupts. The following points should be observed when performing user application processing using non-maskable interrupts, and when using the serial debugger:

???The non-maskable interrupt processing program should be written so that interrupt factors are checked within the non-maskable interrupt processing program, and control branches to the debugger program for all factors other than those that should be processed.

???The program should be written so that if the stack pointer (SP) is changed before branching to the debugger program, control should branch after the stack pointer is set to the value when the interrupt was accepted.

*For details, refer to the??? MN1030 Series C Source Code Debugger User's Manual???.

9-7

Interrupt Controller

Group n interrupt control register GnICR (n = 2 to 19)

Registers G2ICR to G19ICR control level interrupts for groups 2 to 19, respectively.

Each register confirms the group interrupt level as well as the enabling, request, and detection of interrupts within the respective group.

The explanation on this page applies to registers G2ICR to G19ICR.

The interrupt control registers for group 2 to 19 are described starting on page 9-10.

???This register stores the logical product of the IEn(n=3 to 0) and IRn(n=3 to 0) bits.

???If an interrupt that is enabled in the IEn bits is generated, the bit corresponding to the interrupt is "1".

9-8

Interrupt Controller

For details on the interrupt factor assigned to each group, refer section 9.4, "Block

Diagram."

??? When simultaneous interrupt requests are generated from more than one interrupt group, the interrupt with the highest interrupt priority level is accepted. In addition, if multiple interrupt priority levels are set in the same level, the interrupt from the group with the smallest group number is accepted.

Perform operations concerning the interrupt priority level bits (LV2 to 0) and the interrupt enable bits (IE3 to 0) in the group n interrupt control register (GnICR) while interrupts are disabled, as shown below.

...................

However, while the interrupt handler is running, IE in the PSW is "0," unless IE has been set. Therefore, it is not necessary to explicitly clear the IE bit and disable interrupts.

The nop instructions indicated above can be any instructions, as long as they do not change the IE bit in the PSW, or change LV2 to 0 or IE3 to 0 in GnICR.

In addition, the reason for inserting two nop instructions is to ensure that the minimum number of cycles needed to change the IE bit in the PSW are provided; therefore, any instruction that consumes at least the same number of cycles as two nop instructions may be inserted.

9-9

Interrupt Controller

9-10

Interrupt Controller

9-11

Interrupt Controller

9-12

Interrupt Controller

9-13

Interrupt Controller

9-14

Interrupt Controller

9-15

Interrupt Controller

9-16

Interrupt Controller

9-17

Interrupt Controller

12G10LV0 Group 10 interrupt priority level register (LSB)

13G10LV1 Group 10 interrupt priority level register

14G10LV2 Group 10 interrupt priority level register (MSB)

9-18

Interrupt Controller

12G11LV0 Group 11 interrupt priority level register (LSB)

13G11LV1 Group 11 interrupt priority level register

14G11LV2 Group 11 interrupt priority level register (MSB)

9-19

Interrupt Controller

12G12LV0 Group 12 interrupt priority level register (LSB)

13G12LV1 Group 12 interrupt priority level register

14G12LV2 Group 12 interrupt priority level register (MSB)

9-20

Interrupt Controller

12G13LV0 Group 13 interrupt priority level register (LSB)

13G13LV1 Group 13 interrupt priority level register

14G13LV2 Group 13 interrupt priority level register (MSB)

9-21

Interrupt Controller

12G14LV0 Group 14 interrupt priority level register (LSB)

13G14LV1 Group 14 interrupt priority level register

14G14LV2 Group 14 interrupt priority level register (MSB)

9-22

Interrupt Controller

12G15LV0 Group 15 interrupt priority level register (LSB)

13G15LV1 Group 15 interrupt priority level register

14G15LV2 Group 15 interrupt priority level register (MSB)

9-23

Interrupt Controller

12G16LV0 Group 16 interrupt priority level register (LSB)

13G16LV1 Group 16 interrupt priority level register

14G16LV2 Group 16 interrupt priority level register (MSB)

9-24

Interrupt Controller

12G17LV0 Group 17 interrupt priority level register (LSB)

13G17LV1 Group 17 interrupt priority level register

14G17LV2 Group 17 interrupt priority level register (MSB)

9-25

Interrupt Controller

12G18LV0 Group 18 interrupt priority level register (LSB)

13G18LV1 Group 18 interrupt priority level register

14G18LV2 Group 18 interrupt priority level register (MSB)

9-26

Interrupt Controller

12G19LV0 Group 19 interrupt priority level register (LSB)

13G19LV1 Group 19 interrupt priority level register

14G19LV2 Group 19 interrupt priority level register (MSB)

9-27

Interrupt Controller

During a register read, this register returns the smallest group number of the groups that are generating an interrupt of the interrupt levels indicated by IM2 to 0 the PSW.

Because when an interrupt generated, the interrupt levels accepted by the CPU are set in IM2 to 0, this register returns a group number that is generating an interrupt level accepted by the CPU. However, if IM2 to 0 are changed, if the interrupt control register is manipulated, or if a new interrupt factor is generated, the value that this register returns may change even while interrupt processing is in progress.

The interrupt accepted group register IAGR is a read-only register; it cannot be written.

9-28

Interrupt Controller

Note : Change the conditions under which the external interrupt is triggered while the IE bit of the interrupt control register GnICR (n=11 to 18) for each of the groups 11 to 18 is not set to "1" (interrupt enable).

9-29

Interrupt Controller

9.6 Description of Operation

The following interrupt processing is performed.

In the event of a level interrupt, an interrupt group determination is made, and an interrupt request is sent to the CPU.

Once the interrupt signal is received, it is determined to be either a non-maskable interrupt or a level interrupt.

If it is a level interrupt, the interrupt group is determined by deciding to which group the interrupt factor belongs. Once the interrupt group is determined, the interrupt request is sent by manipulating the interrupt control register (GnICR) for that group in order to notify the CPU of the interrupt group level. The interrupt group number is also set in the interrupt acceptance group register (IAGR).

The interrupt level of a group can be determined by reading the interrupt priority level register LV2 to 0 in the interrupt control register (GnICR).

If multiple level interrupt signals are received, the groups to which each belongs is determined and then the interrupt group with the highest priority level is selected. If the group levels are the same, the group with the smallest group number is selected.

The processing described above is not performed in the case of a non-maskable interrupt; instead, the non-maskable interrupt request is simply sent to the CPU.

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Interrupt Controller

[Cautions]

1.Maintain external pin interrupt signals for at least 10, 5, or 2.5 SYSCLK cycles when nfr = (MCLK frequency/ SYSCLK frequency) = 1, 2, or 4, respectively. The interrupt cannot be detected if the signal is not maintained for at least that long.

However, when recovering from HALT mode in response to an external pin interrupt signal, maintain the signal for at least 22, 11, or 5.5 SYSCLK cycles when nfr = 1, 2, or 4, respectively. Furthermore, when recovering from STOP mode in response to an external pin interrupt signal, maintain the signal for at least 10, 5, 2.5 SYSCLK cycles when nfr = 1, 2, or 4, respectively, if there is just one interrupt factor; if there are multiple interrupt factors, continue the external pin interrupt request until the interrupt factors are confirmed by

the interrupt processing program.

2Although it is possible to recover from STOP, HALT, or SLEEP mode in response to an external pin (IRQ7 to 0) interrupt, the trigger conditions for recovery differ for each mode, as indicated in the table below.

3When writing a GnICR register in an interrupt program in order to clear IR and ID and then returning from the interrupt program, in order to gain synchronization with the bus controller store buffer be certain to perform an I/O bus access between the execution of the instruction (movbu, etc.) that is used to write the clear data to the GnICR register and the execution of the instruction to return from the interrupt program.

Example: After clearing a GnICR register, read it again.

If there is no I/O bus access between the instruction that is used to write the clear data to the GnICR register and the instruction to return from the interrupt program, the return from the interrupt program is not guaranteed.

Misoperation will occur when executing the interrupt program again after returning, especially when the RETURN instruction is described after a clear data write.

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Interrupt Controller

9-32

8-bit Timers

10.1 Overview

This device has 12 reload timers built in.

All are down counters that can be used as interval timers and event counters.

Eight of the timers are also capable of PWM output.

10.2 Features

The features of the 8-bit timers are described below.

??? Clock source: An internal clock or external clock can be selected as the clock source. (Timers 0 to B)

???Serial interface reference clock generation

Timers 2, 3, 8, and 9 generate reference clocks for serial interfaces 0 to 3.

???A/D conversion start trigger generation

Timer 2 generates the A/D conversion start trigger.

10-2

8-bit Timers

10.3 Block Diagram

Fig. 10-3-1 shows a block diagram for timers 0 to 3.

Fig. 10-3-2 shows a block diagram for timers 4 to B.

Figures 10-3-3 to 10-3-6 show connection diagrams for the 8-bit timers.

Fig. 10-3-1 8-bit Timer Block Diagram (Timers 0 to 3)

10-3

8-bit Timers

Fig. 10-3-2 8-bit Timer Block Diagram (Timers 4 to B)

10-4

8-bit Timers

Prescaler control register

detection

TM2IO

Edge

detection

Fig. 10-3-3 8-bit Timer Connection Diagram (Overall)

10-5

8-bit Timers

Fig. 10-3-4 8-bit Timer Connection Diagram (Timer 0 to 3 block)

10-6

8-bit Timers

Fig. 10-3-5 8-bit Timer Connection Diagram (Timer 4 to 7 block)

10-7

8-bit Timers

Fig. 10-3-6 8-bit Timer Connection Diagram (Timer 8 to B block)

10-8

8-bit Timers

10.4 Functions

Table 10-4-1 lists the functions of each 8-bit timer.

Table 10-4-1 List of 8-bit Timer Functions

Note: Because timers 0 and 8, 1 and 9, 2 and A, and 3 and B share multipurpose output pins, only one of either "timer output" or "PWM output" can be selected.

10-9

8-bit Timers

10.5 Description of Registers

Table 10-5-1 lists the 8-bit timer registers.

Table 10-5-1 List of 8-bit Timer Registers (1/2)

10-10

8-bit Timers

Table 10-5-1 List of 8-bit Timer Registers (2/2)

10-11

8-bit Timers

0: Operation disabled

1: Operation enabled

[Note]

When setting TMnCNE to "1", do so while TMnLDE is set to "0". When setting TMnLDE to "1", do so while TMnCNE is set to "0".

Operation is not guaranteed if TMnCNE and TMnLDE are both set to "1" at the same time.

10-12

8-bit Timers

Timer n mode register (n = 4, 5, 6, 7, 8, 9, A, B)

10-13

8-bit Timers

[Note]

When setting TMnCNE to "1", do so while TMnLDE is set to "0". When setting TMnLDE to "1", do so while TMnCNE is set to "0".

Operation is not guaranteed if TMnCNE and TMnLDE are both set to "1" at the same time.

Table 10-5-2 PWM Output Waves

10-14

8-bit Timers

Table 10-5-3 8-bit Timer Clock Sources

When using 1/8 IOCLK or 1/32 IOCLK, the prescaler control register (TMPSCNT) must be set. When TMnIO pin input was selected, the rising edge of the pin input signal is counted.

10-15

8-bit Timers

Timer n base register (n = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B)

The value that is set in TMnBR is loaded into TMnBC under the following conditions:

(1)When TMnLDE = 1

(2)When an underflow has occurred

TMnBC generates an underflow interrupt every (value set in TMnBR + 1) counts.

When PWM output has been selected for timers 4 to B, the PWM output cycle is set.

Timer n binary counter (n = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B)

This is a down counter.

The initial value for this register is the value that is set in TMnBR, and this register generates an underflow and an interrupt request every (value set in TMnBR + 1) counts.

10-16

8-bit Timers

Timer n compare register (n = 4, 5, 6, 7, 8, 9, A, B)

This register sets the PWM output duty ratio.

The duty ratio is (value set in TMnCMP)/(value set in TMnBR + 1).

When data is written to this register, it is written in the compare register buffer.

The set value is loaded from the compare register buffer into the compare register under the following conditions:

(1)When TMnLDE = 1

(2)When an underflow was generated

When this register is read, the value that is actually in the compare register is read.

10-17

8-bit Timers

10-18

8-bit Timers

0:Operation disabled

1:Operation enabled

The prescaler that is controlled by this register is also used with the 16-bit timers.

10-19

8-bit Timers

10.6 Description of Operation

This section describes the operation of the 8-bit timers.

10.6.1Interval Timers and Timer Output

When using an 8-bit timer as an interval timer, make the appropriate settings according to the procedure described below.

The timer in question then operates as an interval timer that generates interrupts on the set cycle. (Refer to Figs. 10-6-1 to 10-6-3.)

When using the timers as a 16-, 24- or 32-bit timer by means of a cascaded connection, refer to section 10.6.3, "Cascaded Connection."

The procedure for generating the reference clock for the serial interfaces and for generating the A/D conversion start trigger is the same.

??? Procedure for initiating operation

(1)Set the timer division ratio.

Set the division ratio in TMnBR. The interrupt request cycle is then:

(value set in TMnBR + 1) x Clock source cycle

(2)Select the clock source.

Select the clock source through TMnCK[2:0] in the TMnMD register. When using either 1/8 IOCLK or 1/32 IOCLK as the clock source, set TMPSCNE to "1" in the TMPSCNT register to enable prescaler operation.

(3)Output mode setting (Applies to timers 4 to B only.)

Set TMnOM[1:0] in the TMnMD register to underflow 1/2 cycle output, and select the polarity after initialization.

(4)Initialize the timer.

Set TMnLDE to "1" in the TMnMD register to initialize timer n. The value set in TMnBR is loaded into TMnBC as the initial value, and the timer output is reset.

After initialization, be certain to set TMnLDE to "0" to return to normal operation mode.

(5)Set the I/O port. (Applies when using timer output.) Select the output signal in the TMOSL register.

Set the I/O port to the timer output pin.

Select the timer output for the output signal in the I/O port register, and then set it to the output pin. Note : For details on the I/O port register settings, refer to chapter 15, "I/O Ports."

10-20

8-bit Timers

(6)Enable the timer counting operation.

Once TMnCNE is set to "1" in the TMnMD register, the counting operation starts.

Once the counting operation is enabled, an underflow interrupt request is generated at fixed intervals.

In addition, the pin output is inverted each time that this interrupt is generated, and the value that is set in TMnBR is loaded into TMnBC.

If the value in the TMnBR register is changed while the counting operation is in progress, that value is loaded as the initial value the next time that an underflow is generated, and then the interrupt cycle changes.

??? Procedure for ending operation

(1)Stop the timer counting operation.

Set TMnCNE to "0" in the TMnMD register, stopping the counting operation.

(2)Initialize the timer, if necessary.

If TMnLDE is set to "1" in the TMnBR register, the value that is set in TMnMD is loaded into TMnBC as the initial value, and the timer output is reset. If only the timer is stopped and "1" is not written to TMnLDE, the status of the binary counter and the pin output are maintained as they were before the counting operation was stopped. If TMnCNE is set to "1", the count resumes from the state that was in effect immediately before the counting operation was stopped.

10-21

8-bit Timers

TMnBC value

Interrupt request

Timer output

Fig 10-6-1 Interval Timer Operation

IOCLK

Interrupt request signal (TMnIRQ)

Timer output (TMnOUT)

(value in TMnBR + 1) x IOCLK

Fig 10-6-2 Interval Timer Operation (When Clock Source = IOCLK)

10-22

8-bit Timers

Fig. 10-6-3 Interval Timer Operation (Using Prescaler)

10-23

8-bit Timers

10.6.2 Event Counting

When using an 8-bit timer for event counting, make the settings according to the procedure described below. When using the timers as a 16-, 24- or 32-bit timer by means of a cascaded connection, refer to section 10.6.3, "Cascaded Connection."

??? Procedure for initiating operation

(1)Set the timer division ratio.

Set the division ratio in TMnBR.

An interrupt request is then generated when the rising edge on the pin input is counted (value set in TMnBR + 1) times.

(2)Select the clock source.

Through TMnCK[2:0] in the TMnMD register, set the clock source to the TMnIO pin input.

(3)Initialize the timer.

Set TMnLDE to "1" in the TMnMD register to initialize timer n. The value set in TMnBR is loaded into TMnBC as the initial value.

After initialization, be certain to set TMnLDE to "0" to return to normal operation mode.

(4)Set the I/O port.

Set the I/O port to the general-purpose input pin.

For details on the I/O port register settings, refer to chapter 15, "I/O Ports."

(5)Enable the timer counting operation.

Once TMnCNE is set to "1" in the TMnMD register, the counting operation is enabled.

Once the counting operation is enabled, the rising edge on the pin input is counted, and an interrupt request is generated when there is an underflow in the binary counter. (Refer to Fig. 10-6-4.)

If the value in the TMnBR register is changed while the counting operation is in progress, that value is loaded as the initial value the next time that an underflow is generated.

??? Procedure for ending operation

(1)Stop the timer counting operation.

Set TMnCNE to "0" in the TMnMD register, stopping the counting operation.

(2)Initialize the timer, if necessary.

If TMnLDE is set to "1" in the TMnMD register, the value that is set in TMnBR is loaded into TMnBC as the initial value.

If only the timer is stopped and "1" is not written to TMnLDE, the status of the binary counter is maintained as it was before the counting operation was stopped. If TMnCNE is set to "1", the count resumes from the state that was in effect immediately before the counting operation was stopped.

10-24

8-bit Timers

[Note]

Pin input is sampled according to IOCLK. Input a signal with a pulse width of at least 6, 3, or 1.5 SYSCLK cycles when (MCLK frequency/SYSCLK frequency) = 1, 2, or 4, respectively.

Event counting is not possible when IOCLK is stopped (in HALT or STOP mode).

10-25

8-bit Timers

10.6.3Cascaded Connection

The 8-bit timers can be cascaded together in the combinations shown in Fig. 10-6-5.

When using cascaded 8-bit timers as a 16-bit timer:

When using cascaded 8-bit timers as a 24-bit timer:

When using cascaded 8-bit timers as a 32-bit timer:

Fig. 10-6-5 Cascaded Connection

10-26

8-bit Timers

Make the settings described below when cascading 8-bit timers.

(1)Set the timer division ratio.

Set the timer division ratio in TMnBR.

(Example 1) When using timers 0 and 1 as 16-bit timers and setting the interrupt cycle to x'1234:

In order to set the interrupt cycle to x'1234, x'1234 - 1 = x'1233

must be set in TMnBR.

Set x'33 in the low-order byte, TM0BR, and x'12 in the high-order byte, TM1BR.

Because TMnBR can be accessed via 16-bit or 32-bit access, values can be set in multiple registers simultaneously. (When cascading timers 1 and 2, 5 and 6, and 9 and A, or when using them as 24-bit timers, it is not possible to simultaneously access only the registers for the cascaded timers.)

When changing the values that are set in TMnBR while the counter is in operation, change TMnBR for the cascaded timers simultaneously.

(2)Select the clock source.

Select any desired clock source for the lowest-order timer.

Set the clock source for the higher timers (all except for the lowest timer) to "cascaded connection."

(Example 1) When using timer 0 and timer 1 as a 16-bit timer Set the desired clock source for timer 0.

Set the clock source for timer 1 to "cascaded connection."

(Example 2) When using timers 0, 1, 2 and 3 as a 32-bit timer Set the desired clock source for timer 0.

Set the clock source for timers 1, 2 and 3 to "cascaded connection."

(3)Initialize the timers

Set the TMnLDE flag to "1" for all cascaded timers in order to initialize the timers. (It is not necessary to set the bit simultaneously in all of the registers.)

10-27

8-bit Timers

(4)Enable counting operation

Enable the counting operation by either one of the following two methods:

1)Enable the counting operation for each of the cascaded timers one at a time, in order, starting from the highest timer.

2)Enable the counting operation for all of the cascaded timers simultaneously.

(5)Stop the counting operation

Stop the counting operation by either one of the following two methods:

1)Stop the counting operation for each of the cascaded timers one at a time, in order, starting from the lowest timer.

2)Stop the counting operation for all of the cascaded timers simultaneously.

(6)Timer output and interrupts

Only the timer output and interrupt requests from the highest of the cascaded timers can be used. Operation of the timer output and interrupt requests from the lower cascaded timers is not guaranteed.

10-28

8-bit Timers

Differences between using a timer as a prescaler and when cascaded

The following explanation of these differences uses the cases where the clock source for timer 1 is set to "timer 0 underflow" and to "cascaded with timer 0" as examples.

When "timer 0 underflow" is set, operation is as shown in Fig. 10-6-6. (IOCLK is selected as the clock source for timer 0.)

When TM0BC underflows, the value that is set in TM0BR is loaded into TM0BC, and the value in TM1BC is decremented by one.

When TM1BC underflows, the value that is set in TM1BR is loaded into TM1BC.

10-29

8-bit Timers

When "cascaded with timer 0" is set, operation is as shown in Fig. 10-6-7. (IOCLK is selected as the clock source for timer 0.)

If TM1BC does not equal x'00, then when TM0BC underflows, the value in TM0BC is x'FF and the value in TM1BC is decremented by one.

If TM1BC does equal x'00, then when TM0BC underflows, the values that are set in TM0BR and TM1BR are loaded into TM0BC and TM1BC, respectively, and a timer 1 interrupt request is generated.

10-30

8-bit Timers

10.6.4PWM Output

Make the settings as described below when using an 8-bit timer to output a PWM waveform. (Timers 4 to B) The timers cannot be cascaded when outputting a PWM waveform.

??? Procedure for initiating operation

(1)Set the PWM output cycle. Set the cycle in TMnBR. The PWM output cycle is:

(value set in TMnBR + 1) x clock source cycle

(2)Set the PWM output duty ratio. Set the duty ratio in TMnCMP. The PWM output duty ratio is:

(value set in TMnCMP) / (value set in TMnBR + 1) The set value is written to the compare register buffer.

(3)Select the clock source.

Select the clock source through TMnCK[2:0] in the TMnMD register. When using 1/8 IOCLK or 1/32 IOCLK as the clock source, set TMPSCNE to "1" in the TMPSCNT register to enable prescaler operation.

(4)Set the output mode (timers 4 to B only).

Set TMnOM[1:0] in the TMnMD register to PWM output, and select the polarity upon initialization.

(5)Initialize the timer.

Set TMnLDE in the TMnMD register to "1" to initialize timer n.

The value set in TMnBR is loaded into TMnBC as the initial value.

The value in the compare register buffer is loaded into the TMnCMP register. PWM output is initialized.

After initialization, be certain to set TMnLDE to "0" and to return to normal operation.

(6)Set the I/O port.

Select the output signal through the TMOSL register. (Select the output for timers 8 to B.) Set the I/O port to the timer output pin .

Select timer output for the output signal in the I/O port register, and set it to the output pin For details on the I/O port register settings, refer to chapter 15, "I/O Ports.".

(7)Enable the timer count operation.

Set TMnCNE to "1" in the TMnMD register to start the counting operation.

10-31

8-bit Timers

Once the counting operation is enabled, the PWM waveform is output and an underflow interrupt request is generated. (Refer to Fig. 10-6-8 and 10-6-9.)

If the value in the TMnBR register is changed while the counting operation is in progress, that value is loaded as the initial value when the next underflow is generated, and the cycle of the PWM waveform changes.

If the value in the TMnCMP register is changed while the counting operation is in progress, that value is loaded into the compare register when the next underflow is generated, and the duty ratio of the PWM waveform changes.

??? Procedure for ending operation

(1)Stop the timer counting operation.

Set TMnCNE to "0" in the TMnMD register, stopping the counting operation.

(2)Initialize the timer, if necessary.

If TMnLDE is set to "1" in the TMnMD register, the timer is initialized.

The value set in TMnBR is loaded into TMnBC as the initial value.

The value in the compare register buffer is loaded into the TMnCMP register. PWM output is initialized.

If only the timer is stopped and "1" is not written to TMnLDE, the status of the binary counter is maintained as it was before the counting operation was stopped. If TMnCNE is set to "1", the count resumes from the state that was in effect immediately before the counting operation was stopped.

10-32

8-bit Timers

IOCLK

TMnBC value

Interrupt request signal (TMnIRQ)

Timer output (TMnOUT)

TMnCMP value x IOCLK

(TMnBR value +1) x IOCLK

Fig. 10-6-8 PWM Output (When Clock Source = IOCLK, and "L" Level Is Output Upon Initialization)

IOCLK

Counter clock

TMnBC value

Interrupt request signal (TMnIRQ)

Timer output (TMnOUT)

TMnCMP value x counter clock

(TMnBR value + 1) x counter clock

Fig. 10-6-9 PWM Output (When Using Prescaler, and "H" Level Is Output Upon Initialization)

10-33

8-bit Timers

10-34

16-bit Timers

11.1 Overview

This microcontroller has four 16-bit timers built in.

Three are reload timers (down-counters) that can be used as interval timers or event counters. The other is an up-counter that has two compare/capture registers built in.

11.2 Features

The features of the 16-bit timers are described below.

Timer 10

???Up-counter

???Clock sources

An internal clock or an external clock can be selected as the clock source.

???Internal clock: IOCLK, 1/8 IOCLK, 1/32 IOCLK, or underflow in timers 0 to 2

???External clock: Counts the rising edge or falling edge of the input signal on the TM10IOB pin.

???Compare/capture register

Has two compare/capture registers built in.

??? Pin output

Capable of PWM output with variable cycle and duty ratio. (One output) Capable of PWM output with added bits. (Two outputs)

(Resolution: 8 + 2 bits, 8 + 3 bits, 8 + 4 bits, and 8 + 6 bits) Capable of one-shot output. (Two outputs)

Polarity of pin output can be set.

??? Input capture

Each pin can be set individually to rising edge, falling edge, or both edges. (Two inputs) An interrupt request is generated upon capture.

When "both edges" is set, an interrupt request is generated at both the rising edge and the falling edge.

??? Interrupts

An interrupt request is generated when the binary counter overflows.

An interrupt request is generated when the compare register and the binary counter match, or when capture occurs. (Two outputs)

??? Counting start by external trigger

Counting can be started by input on the TM10IOB pin. (Edge specification possible)

Timers 11, 12, and 13

???Reload timers (down-counters)

???Clock sources

An internal clock or an external clock can be selected as the clock source.

???Internal clock: IOCLK, 1/8 IOCLK, 1/32 IOCLK, or underflow in timers 0 to 2

???External clock: Counts the rising edge of the signal on the pin input.

???Interrupts

An interrupt request is generated when the binary counter underflows.

??? Timer output

Output at 1/2 of the timer underflow is possible.

11-2

16-bit Timers

11.3 Block Diagram

Fig. 11-3-1 shows the block diagram for timer 10, and Fig. 11-3-2 shows the block diagram for timers 11 to 13.

Timer 10

Fig. 11-3-1 16-bit Timer Block Diagram (Timer 10)

11-3

16-bit Timers

Timer n

(n = 11, 12, 13)

Fig. 11-3-2 16-bit Timer Block Diagram (Timers 11, 12, and 13)

11-4

16-bit Timers

11-5

16-bit Timers

Fig. 11-3-4 shows the block diagram for the timer 10 compare/capture registers.

Fig. 11-3-4 Timer 10 Compare/Capture Register Block Diagram

Fig. 11-3-5 shows the block diagram for the PWM output section when timer 10 is set to PWM mode with additional bits.

Underflow

Additional bit control

Compare register buffer

Fig. 11-3-5 PWM Output Section Block Diagram

11-6

16-bit Timers

11.4 Functions

Table 11-4-1 lists the functions of each 16-bit timer.

Table 11-4-1 List of 16-bit Timer Functions

11-7

16-bit Timers

11.5 Description of Registers

Table 11-5-1 lists the 16-bit timer registers.

Table 11-5-1 List of 16-bit Timer Registers

The prescaler control register (TMPSCNT) is also used by the 8-bit timers.

11-8

16-bit Timers

1: Enables one-shot operation.

If TM10BC and TM10CA match, the TM10CNE flag is reset and the timer stops.

11-9

16-bit Timers

[Note]

When setting TM10CNE to "1", do so while TM10LDE is set to "0". When setting TM10LDE to "1", do so while TM10CNE is set to "0".

Operation is not guaranteed if TM10CNE and TM10LDE are both set to "1" at the same time.

11-10

16-bit Timers

Timer n mode register (n = 11, 12, 13)

[Note]

When setting TMnCNE to "1", do so while TMnLDE is set to "0". When setting TMnLDE to "1", do so while TMnCNE is set to "0".

Operation is not guaranteed if TMnCNE and TMnLDE are both set to "1" at the same time.

Table 11-5-2 16-bit Timer Clock Sources

11-11

16-bit Timers

Timer n base register (n = 11, 12, 13)

Register symbol: TMnBR

The value set in TMnBR is loaded into TMnBC under the following conditions:

(1)When TMnLDE = 1

(2)When an underflow has occurred.

TMnBC generates an underflow interrupt request every (value set in TMnBR + 1) counts.

Timer n binary counter (n = 10, 11, 12, 13)

Timer 10 is an up-counter that counts up from an initial value of x'0000, and generates an interrupt request when an overflow occurs. In PWM output mode with additional bits, timer 10 operates as a binary counter with the resolution that was set, and generates an interrupt request when an overflow occurs.

Timers 11, 12 and 13 are down-counters. With the value set in TMnBR as the initial value, these registers underflow after (value set in TMnBR + 1) counts, and generate an interrupt request.

11-12

16-bit Timers

00: Compare register (single-buffer)

01: Compare register (double-buffer)

10: Capture register (single-edge operation)

11: Capture register (dual-edge operation)

When dual-edge capture is set, the setting of TM10AEG is ignored.

11-13

16-bit Timers

00: Compare register (single-buffer)

01: Compare register (double-buffer)

10: Capture register (single-edge operation)

11: Capture register (dual-edge operation)

When dual-edge capture is set, the setting of TM10BEG is ignored.

11-14

16-bit Timers

When this register is set as a compare register, an interrupt request is generated when TM10BC and TM10CA match.

The timer 10 cycle can be set by clearing TM10BC when TM10BC matches TM10CA. The cycle is the set value + 1.

When this register is set as a double-buffer compare register, data that is written to TM10CA is stored temporarily in a buffer, so it is possible that after writing TM10CA, a read of TM10CA will still return the value that was previously stored there.

The value set in the buffer is loaded into the compare register under the conditions described below. In any of these cases, the value in TM10BC becomes x'0000.

(1)When timer 10 is initialized

(2)When an overflow occurs (while TM10CAE is set to "0")

(3)When TM10BC matches TM10CA (while TM10CAE is set to "1")

When this register is set as a capture register, the value in TM10BC is captured in TM10CA and an interrupt request is generated when the edge that was selected by the TM10AEG flag is input to the TM10IOA pin.

When this register is set as a dual-edge capture register, the value in TM10BC is captured in TM10CA and an interrupt request is generated at either a rising edge or a falling edge.

11-15

16-bit Timers

When this register is set as a compare register, an interrupt request is generated when TM10BC and TM10CB match.

The timer 10 cycle can be set by clearing TM10BC when TM10BC matches TM10CB. The cycle is the set value + 1.

When this register is set as a double-buffer compare register, data that is written to TM10CB is stored temporarily in a buffer, so it is possible that after writing TM10CB, a read of TM10CB will still return the value that was previously stored there.

The value set in the buffer is loaded into the compare register under the conditions described below. In any of these cases, the value in TM10BC becomes x'0000.

(1)When timer 10 is initialized

(2)When an overflow occurs (while TM10CAE is set to "0")

(3)When TM10BC matches TM10CA (while TM10CA is set as a compare register, and TM10CAE is set to "1".)

(4)When capturing a value in TM10CA (while TM10CA is set as a capture register, and TM10CAE is set to "1".)

When this register is set as a capture register, the value in TM10BC is captured in TM10CB and an interrupt request is generated when the edge that was selected by the TM10BEG flag is input to the TM10IOB pin.

When this register is set as a dual-edge capture register, the value in TM10BC is captured in TM10CB and an interrupt request is generated at either a rising edge or a falling edge.

11-16

16-bit Timers

0:Prescaler operation disable

1:Prescaler operation enabled.

This prescaler also serves as the 1/8 IOCLK or 1/32 IOCLK prescaler that is used by 8-bit timers.

11-17

16-bit Timers

11.6 Description of Operation of Timer 10

This section describes the operation of timer 10.

Timer 10 includes an up-counter and two compare/capture registers. The compare/capture registers are independent of each other, and can each be used as either a compare register or a capture register.

11.6.1Compare Register Settings

In order to use either the timer 10 compare/capture A register or B register as a compare register, the following settings must be made according to the procedure described below before timer 10 is initialized.

The explanation below refers only to the compare/capture A register, but similar settings would also need to be made for the compare/capture B register.

(1) Set the compare/capture A register mode. Set the TM10MDA register as follows:

(2)Set the comparison value in the compare/capture A register. Set the comparison value in TM10CA.

If the double-buffer is set, the value that is set is not loaded into the compare register at this point. Even if TM10CA is read at this point, the previous value that was set is read. The set value is loaded when timer 10 is initialized.

Once the timer 10 counting operation is enabled, a compare/capture A interrupt request is generated according to the timing shown in Fig. 11-6-1.

If the double-buffer is set, the value that is set in the buffer is loaded into the compare register at the same time that TM10BC is cleared.

11-18

16-bit Timers

IOCLK

(when TM10CAE = 0)

Compare/capture A interrupt request

Fig. 11-6-1 Compare Register Operation (When Clock Source = IOCLK)

11.6.2Capture Register Settings

In order to use either the timer 10 compare/capture A register or B register as a capture register, the following settings must be made according to the procedure described below before timer 10 is initialized.

The explanation below refers only to the compare/capture A register, but similar settings would also need to be made for the compare/capture B register.

(1)Set the compare/capture A register mode. Set the TM10MDA register as follows:

Once the timer 10 counting operation is enabled, the value in TM10BC is captured in TM10CA, and a compare/ capture A interrupt request is generated according to the timing shown in Fig. 11-6-2. (If the counting operation is currently halted, the capture operation does not occur even if the selected edge is input to the pin.)

11-19

16-bit Timers

If dual-edge was selected, the capture operation is performed when either a rising or falling edge is input. It is not possible to determine which edge was input. (The pin input level cannot be read.)

The capture operation can be disabled even while counting is in progress by setting TM10ACE to "0".

When TM10CAE is set to "1" in the TM10MD register and TM10CA is set as a capture register, TM10BC is cleared when the value is captured in TM10CA. If TM10CB is set as a double-buffer compare register, the value that is set in the buffer is loaded into the compare register at this time.

IOCLK

Pin input (TM10IOA)

Capture timing

TM10BC

TM10CA

Compare/capture A interrupt request

Fig. 11-6-2 Input Capture Operation (When "Rising Edge" Is Selected)

11-20

16-bit Timers

11.6.3Pin Output Settings

Timer 10 can be used to output a variety of waveforms to the TM10IOA and TM10IOB pins.

(1)Setting the output level upon initialization

If the TM10LDE flag in the TM10MD register is set to "1", thus initializing timer 10, the output level on the TM10IOA pin is the value that is set for the TM10AEG flag in the TM10MDA register.

The output level on the TM10IOB pin is the value that is set for the TM10BEG flag in the TM10MDB register. Once the TM10LDE flag in the TM10MD register is returned to "0" in order to resume normal operation, manipulating the TM10AEG or TM10BEG flags does not change the output level on the corresponding pins.

(2)Setting the output waveform for the counting operation

If the TM10CNE flag in the TM10MD register is set to "1", thus enabling the timer 10 counting operation, the waveform selected by the TM10AO0, 1, and 2 flags in the TM10MDA register is output to the TM10IOA pin. Similarly, the waveform selected by the TM10BO0, 1, and 2 flags in the TM10MDB register is output to the TM10IOB pin.

Because the values of the TM10AEG and TM10BEG flags are referenced only when the output level is changed, changing the settings of these flags does not change the output level until the next time that the output is changed.

11-21

16-bit Timers

Examples of TM10IOA pin output waveforms are shown below. Output for the TM10IOB pin is similar.

Fig. 11-6-3 shows the output waveform for the TM10IOA pin when "Set when TM10BC matches TM10CA, and reset when TM10BC matches TM10CB" is set. If the set and reset conditions occur simultaneously, the reset takes precedence.

TM10CNE

Match between TM10BC and TM10CA

Match between TM10BC and TM10CB

TM10IOA pin output (when TM10AEG = 0)

TM10IOA pin output (when TM10AEG = 1)

Fig. 11-6-3 Pin Output Waveform (1)

Fig. 11-6-4 shows the output waveform for the TM10IOA pin when "Set when TM10BC matches TM10CA, and reset when TM10BC overflows" is set. If the set and reset conditions occur simultaneously, the reset takes precedence.

TM10CNE

TM10BC overflow

Match between TM10BC and TM10CA

TM10IOA pin output (when TM10AEG = 0)

TM10IOA pin output (when TM10AEG = 1)

Fig. 11-6-4 Pin Output Waveform (2)

11-22

16-bit Timers

Fig. 11-6-5 shows the output waveform for the TM10IOA pin when "Set when TM10BC matches TM10CA" is set.

Fig. 11-6-5 Pin Output Waveform (3)

Fig. 11-6-6 shows the output waveform for the TM10IOA pin when "Reset when TM10BC matches TM10CA" is set.

Fig. 11-6-6 Pin Output Waveform (4)

Fig. 11-6-7 shows the output waveform for the TM10IOA pin when "Toggled output" is set.

TM10CNE

Match between TM10BC and TM10CA

TM10IOA pin output (when TM10AEG = 0)

TM10IOA pin output (when TM10AEG = 1)

Fig. 11-6-7 Pin Output Waveform (5)

11-23

16-bit Timers

11.6.4Starting by an External Trigger

Timer 10 can be started up by input on the TM10IOB pin. Fig. 11-6-8 illustrates the startup operation. The compare/capture A and B registers can be used as compare registers or as capture registers.

???Procedure for initiating operation

(1)Select the input edge on which timer 10 is to start.

Select the input edge through TM10BEG in the TM10MDB register. The starting edge is the opposite of the normal setting.

TM10BEG = 0 Start when falling edge is input TM10BEG = 1 Start when rising edge is input

(2)Set the operating mode.

Set the TM10MD register as described below:

When using 1/8IOCLK or 1/32IOCLK as the clock source, set TMPSCNE in the TMPSCNT register to "1" to enable prescaler operation before enabling the counting operation for timer 10.

(3)Initialize the timer.

Set TM10LDE in the TM10MD register to "1" in order to initialize timer 10. TM10BC is cleared, and the pin output is reset.

In addition, if the compare/capture register is set as a double-buffer compare register, the value in the buffer is loaded into the compare register.

After initialization is completed, be certain to reset TM10LDE back to "0" in order to restore normal operation mode.

(4)Set the I/O port.

Set TM10IOB pin to "input pin." Set the TM10IOA pin as desired.

Note: For details on the I/O port register settings, refer to chapter 15, "I/O Ports."

(5)Enable timer startup by an external trigger.

Set TM10TGE in the TM10MD register to "1".

Once the specified edge is input to the TM10IOB pin, timer 10 starts up. (The TM10CNE flag in the TM10MD register is set by the hardware.)

11-24

16-bit Timers

???Procedure for ending operation

(1)Disable timer startup by an external trigger. Set TM10TGE in the TM10MD register to "0".

(2)Stop the counting operation.

Set TM10CNE in the TM10MD register to "0".

If TM10TGE and TM10CNE are both set to "0" simultaneously, there is a possibility that TM10CNE will be set again, depending on the pin input timing. Therefore, always be sure to set TM10TGE to "0" first, and then set TM10CNE to "0".

IOCLK

Pin input (TM10IOB)

Edge detection

TM10CNE

Fig. 11-6-8 Timer 10 Startup by an External Trigger (When ???Rising Edge??? is Selected)

11-25

16-bit Timers

11.6.5 One-shot Operation

It is possible to stop timer 10 when TM10BC and TM10CA match. Figs. 11-6-9 and 11-6-10 illustrate the operation that stops timer 10.

The compare/capture B register can be used as a compare register or as a capture register.

??? Procedure for initiating operation

(1) Set the compare/capture A register mode. Set the TM10MDA register as follows:

(2)Set the value at which the timer is to stop. Set the comparison value in TM10CA.

The timer will stop when it reaches the count of (value set in the TM10CA register + 1).

(3)Set the operating mode.

Set the TM10MD register as described below:

When using 1/8 IOCLK or 1/32 IOCLK as the clock source, set TMPSCNE in the TMPSCNT register to "1" to enable prescaler operation before enabling the counting operation for timer 10.

(4)Initialize the timer.

Set TM10LDE in the TM10MD register to "1" in order to initialize timer 10. TM10BC is cleared, and the pin output is reset.

In addition, if TM10CA is set as a double-buffer compare register, the value in the buffer is loaded into the compare register.

After initialization is completed, be certain to reset TM10LDE back to "0" in order to restore normal operation mode.

(5)Set the I/O port (when using pin output). Set the I/O port to "timer output pin."

In the I/O port register, select "timer output" for the output signal and then set the output pin. When the timer is to be started up by an external trigger, set the TM10IOB pin to "input pin".

(6)Enable the timer counting operation.

The counting operation starts when the TM10CNE in the TM10MD register is set to "1".

If the timer is to be started by an external trigger, leave TM10CNE set to "0" and set TM10TGE to "1".

When starting to count up again after TM10BC and TM10CA have matched, the hardware clears the TM10CNE flag to stop the counting operation. TM10BC is also cleared.

Note: For details on the I/O port register settings, refer to chapter 15, "I/O Ports."

11-26

16-bit Timers

???Procedure for ending operation

???When the timer was started by a program (TM10TGE = 0)

(1)Stop the counting operation.

Set TM10CNE in the TM10MD register to "0".

???When the timer was started by an external trigger (TM10TGE = 1)

(1)Disable timer startup by an external trigger. Set TM10TGE in the TM10MD register to "0".

(2)Stop the counting operation.

Set TM10CNE in the TM10MD register to "0".

If TM10TGE and TM10CNE are both set to "0" simultaneously, there is a possibility that TM10CNE will be set again, depending on the pin input timing. Therefore, always be sure to set TM10TGE to "0" first, and then set TM10CNE to "0".

IOCLK

Compare/capture A interrupt request

TM10CNE flag

Fig. 11-6-9 One-shot Operation (When Clock Source = IOCLK)

IOCLK

Count clock

Compare/capture

A interrupt request

TM10CNE flag

Fig. 11-6-10 One-shot Operation (When Using Prescaler)

11-27

16-bit Timers

11.6.6 Interval Timer

When using timer 10 as an interval timer, make the settings according to the procedure described below.

This interval timer generates a compare/capture A interrupt request on the cycle that is set. (Refer to Figs. 11-6-11 to 11-6-14.)

The compare/capture B register can be used as a compare register or as a capture register.

Note: For details on the settings, refer to section 11.6.1, "Compare Register Settings," or section 11.6.2, "Capture Register Settings."

???Procedure for initiating operation

(1)Set the compare/capture A register mode.

Set the TM10MDA register as follows:

(2)Set the timer division ratio.

Set the division ratio in TM10CA.

The compare/capture A interrupt cycle then becomes: (value set in TM10CA + 1) x clock source cycle

(3)Set the operating mode.

Set the TM10MD register as described below:

When using 1/8IOCLK or 1/32IOCLK as the clock source, set TMPSCNE in the TMPSCNT register to "1" to enable prescaler operation before enabling the counting operation for timer 10.

(4)Initialize the timer.

Set TM10LDE in the TM10MD register to "1" in order to initialize timer 10. TM10BC is cleared, and the pin output is reset.

In addition, if TM10CA is set as a double-buffer compare register, the value in the buffer is loaded into the compare register.

After initialization is completed, be certain to reset TM10LDE back to "0" in order to restore normal operation mode.

(5)Set the I/O port (when using pin output). Set the I/O port to "timer output pin."

In the I/O port register, select "timer output" for the output signal and then set the output pin.

For details on the I/O port register settings, refer to chapter 15, "I/O Ports."

(6)Enable the timer counting operation.

The counting operation starts when the TM10CNE in the TM10MD register is set to "1".

Once the counting operation is enabled, a compare/capture A interrupt request is generated on a regular cycle.

11-28

16-bit Timers

If the value in the TM10CA register is changed while the counting operation is in progress, the value in the buffer is loaded into the compare register the next time that TM10BC is cleared, and the interrupt cycle is then changed. If the interrupt cycle will be changed while the counting operation is in progress, set TM10CA as a double-buffer compare register.

???Procedure for ending operation

(1)Stop the timer counting operation.

Set TM10CNE to "0" in the TM10MD register, stopping the counting operation.

(2)Initialize the timer, if necessary.

If TM10LDE is set to "1" in the TM10MD register, TM10BC is cleared and the timer output is reset. If the TM10CA register is set as a double-buffer, the value in the compare register buffer is loaded into the compare register.

If TM10LDE is not set to "1" after the timer is stopped, the binary counter, the compare register and the pin output are maintained as they were before the timer was stopped. If TM10CNE is set to "1" again, the count resumes from the state that was in effect immediately before the timer was stopped.

TM10BC value

Value set in

TM10CA

x'0000

TM10CNE

Compare/capture A interrupt request

Fig. 11-6-11 Timer 10 Interval Timer Operation (1)

Value set in

TM10CA

x'0000

TM10CNE

Compare/capture A interrupt request

Fig. 11-6-12 Timer 10 Interval Timer Operation (2)

11-29

16-bit Timers

IOCLK

If ???double-buffer??? is set, the set value is loaded from the buffer at the same time that TM10BC is cleared.

Fig. 11-6-13 Timer 10 Interval Timer Operation (When Clock Source = IOCLK)

IOCLK

Count clock

is loaded from the buffer at the same time that TM10BC is cleared.

Fig. 11-6-14 Timer 10 Interval Timer Operation (When Using Prescaler)

11-30

16-bit Timers

11.6.7 Event Counting

When using timer 10 as an event counter, make the settings according to the procedure described below.

This event counter generates a compare/capture A interrupt when it has counted the specified number of edges. (Refer to Fig. 11-6-15.)

The compare/capture B register can be used as a compare register or as a capture register.

Note: For details on the settings, refer to section 11.6.1, "Compare Register Settings."

???Procedure for initiating operation

(1)Set the compare/capture A register mode. Set the TM10MDA register as follows:

(2)Set the input edge for the TM10IOB pin.

Select either the rising edge or the falling edge at the TM10BEG of the TM10MDB register.

(3)Set the timer division ratio.

Set the division ratio in TM10CA.

A compare/capture A interrupt request is then generated when the specified edge is counted (value set in TM10CA + 1) times on the TM10IOB pin.

(4)Set the operating mode.

Set the TM10MD register as described below:

(5)Initialize the timer.

Set TM10LDE in the TM10MD register to "1" in order to initialize timer 10. TM10BC is cleared, and the pin output is reset.

In addition, if TM10CA is set as a double-buffer compare register, the value in the buffer is loaded into the compare register.

After initialization is completed, be certain to reset TM10LDE back to "0" in order to restore normal operation mode.

(6)Set the I/O port.

Set the I/O port to "input pin."

Note:For details on the I/O port register settings, refer to chapter 15, "I/O Ports."

(7)Enable the timer counting operation.

The counting operation starts when the TM10CNE in the TM10MD register is set to "1".

11-31

16-bit Timers

Once the counting operation is enabled, TM10BC is incremented each time that the specified edge is input to the TM10IOB pin. Once (value in compare/capture A register + 1) edges are counted, TM10BC is cleared and a compare/capture A register interrupt request is generated.

If the value in the TM10CA register is changed while the counting operation is in progress, the value in the buffer is loaded into the compare register the next time that TM10BC is cleared, and the interrupt cycle is then changed. If the interrupt cycle will be changed while the counting operation is in progress, set TM10CA as a double-buffer compare register.

???Procedure for ending operation

(1)Stop the timer counting operation.

Set TM10CNE to "0" in the TM10MD register, stopping the counting operation.

(2)Initialize the timer, if necessary.

If TM10LDE is set to "1" in the TM10MD register, TM10BC is cleared and the timer output is reset. If the TM10CA register is set as a double-buffer, the value in the compare register buffer is loaded into the compare register.

If TM10LDE is not set to "1" after the timer is stopped, the binary counter, the compare register and the pin output are maintained as they were before the timer was stopped. If TM10CNE is set to "1" again, the count resumes from the state that was in effect immediately before the timer was stopped.

[Note]

The pin input is sampled according to IOCLK. Input a signal with a pulse width of at least 6, 3, or 1.5 SYSCLK cycles when (MCLK frequency/SYSCLK frequency) = 1, 2, or 4, respectively.

Also note that event counting is not possible when IOCLK is stopped (in HALT or STOP mode).

Fig. 11-6-15 Event Count Operation (When ???Rising Edge??? is Selected)

11-32

16-bit Timers

11.7 Description of Operation of Timers 11, 12, and 13

This section describes the operation of timers 11, 12, and 13.

Timers 11, 12, and 13 have built-in registers for setting the initial values, and down-counters. These timers can be used as interval timers and as event counters.

11.7.1Interval Timer and Timer Output

When using timers 11, 12, or 13 as an interval timer, make the settings according to the procedure described below. These interval timers generate interrupts on the cycle that is set. (Refer to Figs. 11-7-1 to 11-7-3.)

???Procedure for initiating operation

(1)Set the timer division ratio.

Set the division ratio in TMnBR. The interrupt cycle is then

(value set in TMnBR + 1) x clock source cycle.

(2)Select the clock source.

Select the clock source through TMnCK[2:0] in the TMnMD register. When using 1/8IOCLK or 1/32IOCLK as the clock source, set TMPSCNE in the TMPSCNT register to "1" to enable prescaler operation before enabling the counting operation for timers 11, 12, or 13.

(3)Initialize the timer.

Set TMnLDE to "1" in the TMnMD register to initialize timer n.

The value set in TMnBR is loaded into TMnBC as the initial value, and the timer output is reset. After initialization, be certain to set TMnLDE to "0" to return to normal operation mode.

(4)Set the I/O port (when using timer output). Set the I/O port to "timer output pin."

In the I/O port register, select "timer output" for the output signal and then set the output pin. For details on the I/O port register settings, refer to chapter 15, "I/O Ports."

(5)Enable the timer counting operation.

The counting operation starts when the TMnCNE in the TMnMD register is set to "1".

11-33

16-bit Timers

Once the counting operation is enabled, an underflow interrupt request is generated on a regular cycle. In addition, with each interrupt the pin output is inverted and the value in TMnBR is loaded into TMnBC.

If the value in the TMnBR register is changed while the counting operation is in progress, this changed value is loaded as the initial value the next time that an underflow is generated, and the interrupt cycle is then changed.

???Procedure for ending operation

(1)Stop the timer counting operation.

Set TMnCNE to "0" in the TMnMD register, stopping the counting operation.

(2)Initialize the timer, if necessary.

If TMnLDE is set to "1" in the TMnMD register, the value that is set in TMnBR is loaded into TMnBC as the initial value, and the timer output is reset. If TMnLDE is not set to "1" after the timer is stopped, the binary counter and the pin output are maintained as they were before the timer was stopped. If TMnCNE is set to "1" again, the count resumes from the state that was in effect immediately before the timer was stopped.

TMnBC value

Interrupt request

Timer output

Fig. 11-7-1 Interval Timer Operation

11-34

16-bit Timers

IOCLK

TMnBC value x'0001 x'0000 TMnBR value TMnBR value -1 x'0000 TMnBR value TMnBR value -1

Interrupt request signal (TMnIRQ)

Timer output (TMnOUT)

(TMnBR value +1) x IOCLK

Fig. 11-7-2 Interval Timer Operation (When Clock Source = IOCLK)

IOCLK

Count clock

TMnBC value x'0001 x'0000 TMnBR value TMnBR value -1 TMnBR value -2

Interrupt request signal (TMnIRQ)

Timer output (TMnOUT)

Fig. 11-7-3 Interval Timer Operation (When Using the Prescaler)

11-35

16-bit Timers

11.7.2Event Counting

When using timer 11, 12, or 13 as an event counter, make the settings according to the procedure described below.

???Procedure for initiating operation

(1)Set the timer division ratio.

Set the division ratio in TMnBR.

An interrupt request is then generated when the rising edge is counted (value set in TMnBR + 1) times in the pin input.

(2)Select the clock source.

Select the clock source through TMnCK[2:0] in the TMnMD register to "TMnIO pin input."

(3)Initialize the timer.

Set TMnLDE to "1" in the TMnMD register to initialize timer n.

The value set in TMnBR is loaded into TMnBC as the initial value.

After initialization, be certain to set TMnLDE to "0" to return to normal operation mode.

(4)Set the I/O port.

Set the I/O port to "input pin."

For details on the I/O port register settings, refer to chapter 15, "I/O Ports."

(5)Enable the timer counting operation.

The counting operation is enabled when the TMnCNE in the TMnMD register is set to "1".

Once the counting operation is enabled, the counter counts rising edges on the pin input. When an underflow occurs in the binary counter, an interrupt is generated and the value set in TMnBR is loaded into TMnBC. (Refer to Fig. 11-7-4.)

If the value in the TMnBR register is changed while the counting operation is in progress, this changed value is loaded as the initial value the next time that an underflow is generated.

???Procedure for ending operation

(1)Stop the timer counting operation.

Set TMnCNE to "0" in the TMnMD register, stopping the counting operation.

(2)Initialize the timer, if necessary.

If TMnLDE is set to "1" in the TMnMD register, the value that is set in TMnBR is loaded into TMnBC as the initial value.

If TMnLDE is not set to "1" after the timer is stopped, the binary counter is maintained as it was before the timer was stopped.

If TMnCNE is set to "1" again, the count resumes from the state that was in effect immediately before the timer was stopped.

11-36

16-bit Timers

[Note]

The pin input is sampled according to IOCLK. Input a signal with a pulse width of at least 6, 3, or 1.5 SYSCLK cycles when (MCLK frequency/SYSCLK frequency) = 1, 2, or 4, respectively.

Also note that event counting is not possible when IOCLK is stopped (in HALT or STOP mode).

11-37

16-bit Timers

11-38

Watchdog Timer

12.1 Overview

This microcontroller has a 25-bit binary counter built in that can be used as a 16- to 25-bit watchdog timer.

A watchdog timer overflow generates a nonmaskable interrupt, enabling the watchdog timer overflow to be identified. The watchdog timer is also used as an oscillation stabilization wait timer.

12.2Features

???The number of bits in the binary counter is selectable.

When the CKSEL pin input is "H" (oscillating frequency: 8 MHz to 18 MHz): 16, 18, 20, 22, or 24 bits can be selected.

When the CKSEL pin input is "L" (oscillating frequency: 8 MHz to 20 MHz): 17, 19, 21, 23, or 25 bits can be selected.

Overflow cycle: 4.369 ms to 1118.481 ms

(when the CKSEL pin input is "H" and the oscillating frequency is 15 MHz)

???A non-maskable interrupt is generated when a watchdog timer overflow occurs.

???Watchdog timer overflow output

A flag can be set to "1" when a watchdog timer overflow occurs.

The watchdog timer overflow output can be selected as either pulse output or level output.

???Oscillation stabilization wait time (when the CKSEL pin input is "H" and the oscillating frequency is 15 MHz)

When recovering from STOP mode: 4.369 ms to 1118.481 ms <Recommended value is 14 ms or longer.>

??? The chip can self-reset internally by writing the RSTCTR register.

12-2

Watchdog Timer

12.3 Block Diagram

12-3

Watchdog Timer

12.4 Description of Registers

Table 12-4-1 lists the watchdog timer registers.

Table 12-4-1 List of Watchdog Timer Registers

12-4

Watchdog Timer

Overflow cycle = 2(n + WDCK x 2)/(f x 103) [ms]

Where, n = 16 (CKSEL pin is ???H???) or n = 17 (CKSEL pin is ???L???);

WDCK = WDCK[2:0]; f: Oscillation input frequency [unit: MHz]

Example

12-5

Watchdog Timer

1: Count operation enabled

[Notes]

1.When resetting the value of watchdog overflow by writing the WDRST flag, do not simultaneously overwrite the WDOVT flag.

If this flag is overwritten, the value of watchdog overflow reset is not guaranteed.

2.When changing the values of WDCK2 to 0, first stop the watchdog timer and reset the counter.

a "1".

The value stored in this flag is retained even after the reset.

The CHIPRST flag is cleared either by an external reset signal (RST) or by writing a "0" to this flag through the software.

12-6

Watchdog Timer

12.5 Description of Operation

Oscillation stabilization wait operation

The watchdog timer operates as an oscillation stabilization wait timer after the reset state is released or when the microcontroller recovers from STOP mode (Fig. 12-5-1).

The watchdog timer operates in this capacity even if the WDCNE flag is "0".

When recovering from STOP mode, the watchdog timer operates as a counter of the number of bits specified by WDCK2 to 0 (Fig. 12-5-2). The oscillation stabilization wait time can be selected from among times that are calculated as follows:

Overflow cycle = 2(n + WDCK x 2)/(f x 103) [ms]

Where, n = 16 (CKSEL pin is ???H???) or n = 17 (CKSEL pin is ???L???); WDCK = WDCK[2:0]; f: Oscillation

input frequency [unit: MHz]

An oscillation stabilization wait time of at least 14 ms is recommended.

If the WDCNE flag is "1", a non-maskable interrupt is not generated even when recovering from STOP mode.

OSCI input

Internal reset

SYSCLK

Internal clock, SYSCLK supply

enabled

Overflow

Watchdog timer count value

Oscillation stabilization wait time

17.476 ms

(when CKSEL = ???H??? and the oscillating input frequency is 15 MHz)

Fig. 12-5-1 Operation Diagram 1: When Reset Is Released

12-7

Watchdog Timer

Interrupt

Stop mode release request (external pin interrupt)

OSCI input

SYSCLK

Watchdog timer count value

Oscillation stabilization wait time

4.369 ms to 1118.481 ms <Recommended value is 14 ms or longer.> (when CKSEL = ???H??? and the oscillating input frequency is 15 MHz)

Fig. 12-5-2 Operation Diagram 2: When Recovering from STOP Mode

12-8

Watchdog Timer

Watchdog operation

If the WDCNE flag is set to "1" and the watchdog operation is enabled, a non-maskable interrupt is generated if a watchdog timer overflow occurs.

When an overflow occurs, the watchdog timer overflow output is output to the WDOVF flag. Pulse output or level output can be selected through the WDOVT flag. When level output is selected, the watchdog timer overflow output (WDOVF flag) is cleared by writing a "1" to the WDRST flag or by reset (RST) pin "L" level input.

Overflow

Watchdog timer count value

Counter reset by writing ???1??? to the WDRST flag

Non-maskable interrupt

WDOVF flag output (when pulse output is selected)

SYSCLK 255-cycle width

WDOVF flag output (when level output is selected)

Fig. 12-5-3 Operation Diagram 3: Watchdog Operation

Before setting the WDCNE flag to "1", write a "1" to the WDRST flag to reset the counter.

When switching to HALT or SLEEP mode, set the WDCNE flag to "0" to turn off the watchdog timer.

Self-reset operation

The chip resets internally when a "1" is written to the CHIPRST bit in the RSTCTR register. The oscillation stabilization wait operation is not performed.

The reset generated by writing the CHIPRST flag is an internal reset signal within the chip and does not manifest itself on the external reset pin (RST pin).

12-9

Watchdog Timer

12-10

Serial Interface

13.1 Overview

This microcontroller has three types of internal serial interfaces. One is a general-purpose serial interface for which clock synchronous mode, UART mode, or I2C mode can be specified; this interface supports one channel. The second interface is a clock synchronous serial interface that supports two channels. The third interface is UART serial interface that supports one channel.

General-purpose serial interface

Fig. 13-1-1 Structure Diagram

13-2

Serial Interface

13.2 General-purpose serial interface

13.2.1 Features

Serial interface 0 is a general-purpose serial interface for which clock sync mode, UART mode, or I2C mode can be specified. The features of each mode are described below.

<Clock synchronous mode>

???Character length 7 bits, 8 bits

???Transmission and reception bit sequence

LSB or MSB selectable

??? Clock source 1/2, 1/8, or 1/32 of IOCLK

1/8 of timer 3 or timer 9 underflow, 1/2 of timer 9 underflow External clock

???Maximum bit rate

7.5Mbit/s (when IOCLK is 15 MHz)

???Error detection during reception

13-3

Serial Interface

<UART mode>

???Character length 7 bits, 8 bits

???Transmission and reception bit sequence

LSB or MSB selectable

??? Clock source 1/8 or 1/32 of IOCLK

1/8 of timer 3 or timer 9 underflow 1/8 of external clock

???Maximum bit rate

19.2kbit/s (when IOCLK is 15 MHz)

???Error detection during reception

<I2C mode>

??? Master transmission, master reception possible (No start sequence conflict detection function)

13-4

Serial Interface

13.2.2Block Diagram of General-Purpose Serial Interface

Fig 13-2-1 shows the block diagram for the general-purpose serial interface section.

Reception buffer read

Fig. 13-2-1 Block Diagram

13-5

Serial Interface

13.2.3Description of Registers for the General-Purpose Serial Interface

The general-purpose serial interface includes the registers listed in Table 13-2-1. These registers are used for settings such as clock source selection, parity bit selection, and protocol selection.

Table 13-2-1 List of General-Purpose Serial Interface Registers

13-6

Serial Interface

6 SC0PB2 Parity bit selection (MSB) 000: None

001, 010, 011: Setting prohibited

13-7

Serial Interface

0:Set data pin "H" at end of transmission

1:Maintain data pin at end of transmission

Data is transmitted by writing it to this buffer.

13-8

Serial Interface

13-9

Serial Interface

13.2.4 Description of Operation

<Clock synchronous mode>

??? Clock synchronous mode connection

Two different connection methods are possible, one for unidirectional transfer, and the other for bi-directional transfer.

When SBT pin is an output only during transmission (SC0TOE = "0"), it is necessary to pull up SBT pin. In addition, when using SBO pin as a data input/output (SC0MD1 and 0 = "11"), it is necessary to pull up SBO pin. Connect a pull-up resistor externally.

When using SBO pin as a data output and SBI pin as a data input (SC0MD1 and 0 = "01"), the SBO pin is always an output and the SBI pin is always an input.

When using SBO pin as a data input/output (SC0MD1 and 0 = "11"), the SBO pin is an output only during transmission, and is normally an input.

When SC0TOE is "0", the SBT pin is an output only during transmission with the internal clock, and is normally an input. Furthermore, when SC0TOE is "1", the SBT pin is always an output when the internal clock is selected.

Bi-directional transfer (SC0MD1 and 0 = ???11???)

Fig. 13-2-2 Connections

13-10

Serial Interface

??? Clock synchronous mode timing

<Transmission>

??? One-byte transfer with 8-bit data length and parity on

SBT pin

Data write

SC0TXF flag

SC0TBF flag

Interrupt request

(when set to ???transmission end???)

Interrupt request

(when set to ???transmission buffer empty???)

Fig. 13-2-3 Timing Chart (1)

??? Two-byte transfer with 8-bit data length and parity off

SBT pin

Data write

SC0TXF flag

SC0TBF flag

Interrupt request

(when set to ???transmission end???)

Interrupt request

(when set to ???transmission buffer empty???)

Fig. 13-2-4 Timing Chart (2)

When transmission is enabled, transmission starts when data is written to SC0TXB.

Continuous transmission is possible by writing data to SC0TXB again while transmission is in progress. During a 7-bit transfer, the MSB (bit 7) is ignored.

The SC0TXF flag is set to "1" when data is written to SC0TXB, and is set to "0" at the end of transmission. The SC0TBF flag is set to "1" when data is written to SC0TXB, and is set to "0" at the start of transmission.

13-11

Serial Interface

<Reception>

??? One-byte transfer with 8-bit data length and parity on

SBT pin

SC0RXF flag

SC0RBF flag

Interrupt request

Data read

Fig. 13-2-5 Timing Chart (3)

??? Two-byte transfer with 8-bit data length and parity off

SBT pin

SC0RXF flag

SC0RBF flag

Interrupt request

Data read

Fig. 13-2-6 Timing Chart (4)

After reception end (when the SC0RBF flag is "1"), the received data is fetched by reading the SC0RXB. In the case of a 7-bit transfer, the MSB (bit 7) is "0".

The SC0RXF flag is set to "1" at the start of reception (at the falling edge of SBT pin ), and is set to "0" at the end of reception.

The SC0RBF flag is set to "1" at the end of reception, and is set to "0" when SC0RXB is read.

Sending dummy data makes it possible to receive data while supplying the clock from the microcomputer side. In this case, interrupt requests are also generated by the transmission source. Receive data according to the following procedure:

(1)Select the internal clock as the reference clock, and set the parity, character length, etc.

(2)Enable both the transmission operation and the receiving operation.

(3)When dummy data is written to the transmission buffer, the clock is sent and reception begins.

When using clock synchronous mode (2), set the SBO pin as a general-purpose input port before writing the dummy data to the transmission buffer, and then reset the pin as the SBO pin after transmission is complete.

13-12

Serial Interface

??? When a reception error is generated

??? Transfer in clock synchronous mode with 8-bit data length, parity on.

SBT pin

SC0RXF flag

SC0RBF flag ???H???

SC0OEF flag

SC0PEF flag

Interrupt request

Fig. 13-2-7 Timing Chart (5)

When "reception end" is set as the reception interrupt source, an interrupt request is generated when reception ends, regardless of whether or not an error occurred.

When "reception end with error" is set as the reception interrupt source, an interrupt request is generated when reception ends with an error having occurred. (An interrupt request is not generated at the moment that the error occurred.)

An overrun error is generated when reception of the next data is completed before previously received data is read from the SC0RXB . In this event, the previously received data is lost. The overrun error indicator flag (SC0OEF) is updated at the moment the final data bit is received.

A parity error is generated when 0-fixed parity is set and a "1" is received, when 1-fixed parity is set and a "0" is received, when even parity is set and an odd number of ones is received, or when odd parity is set and an even number of ones is received. The parity error indicator flag (SC0PEF) is updated at the moment the parity bit is received.

13-13

Serial Interface

<UART mode>

??? UART mode connection

Two different connection methods are possible, one for unidirectional transfer, and the other for bi-directional transfer.

The SBO pin is always an output, and the SBI pin is always an input.

Fig. 13-2-8 Connections

??? UART mode bit rates

In UART mode, it is necessary to select an appropriate bit rate and serial interface input clock.

For example, when IOCLK = 15 MHz and the bit rate is 19.2 kbit/s, the timer function is used to divide the clock signal. The division ratio is determined as follows:

Timer division ratio = INT (IOCLK frequency/bit rate/8 + 0.5) In the example described above, the timer division ratio is 98.

In the timer 3 base register, set TM3BR = 97 and set SC0CK2 to 0 = "100". IOCLK divided by 98 will then be supplied to the serial interface as the input clock. The bit rate error is calculated as follows:

Bit rate error = ABS (division ratio x 8 x bit rate/IOCLK frequency - 1) In this example, the bit rate error is 0.35 %.

Typical examples are shown in Tables 13-2-2 through 13-2-4.

Note: When 1/8 of an external clock signal is used as the clock source, the high and low widths of the external clock must be at least 10, 5, or 2.5 SYSCLK cycles when (MCLK frequency/SYSCLK frequency) = 1, 2, or 4, respectively.

If the division ratio is large, use either a prescaler or a cascaded connection for the timer.

13-14

Serial Interface

Table 13-2-2 Bit rates (1) (When IOCLK = 15 MHz)

13-15

Serial Interface

??? UART mode timing

<Transmission>

??? Transfer with 8-bit data length, parity on, and 1 stop bit

??? Two-byte transfer with 7-bit data length, parity on, and 1 stop bit

When transmission is enabled, transmission starts when data is written to SC0TXB.

Continuous transmission is possible by writing data to SC0TXB again while transmission is in progress. During a 7-bit transfer, the MSB (bit 7) is ignored.

The SC0TXF flag is set to "1" when data is written to SC0TXB, and is set to "0" at the end of transmission. The SC0TBF flag is set to "1" when data is written to SC0TXB, and is set to "0" at the start of transmission.

13-16

Serial Interface

<Reception>

??? Transfer with 8-bit data length, parity on, and 1 stop bit

??? Two-byte transfer with 7-bit data length, parity on, and 1 stop bit

After reception end (when the SC0RBF flag is "1"), the received data is fetched by reading the SC0RXB. In the case of a 7-bit transfer, the MSB (bit 7) is "0".

The SC0RXF flag is set to "1" at the start of reception (when the start bit is detected), and is set to "0" at the end of reception.

The SC0RBF flag is set to "1" at the end of reception, and is set to "0" when SC0RXB is read.

13-17

Serial Interface

??? When a reception error is generated

??? Transfer in UART mode with 8-bit data length, parity on, and 1 stop bit

When "reception end" is set as the reception interrupt source, an interrupt request is generated when reception ends, regardless of whether or not an error occurred.

When "reception end with error" is set as the reception interrupt source, an interrupt request is generated when reception ends with an error having occurred. (An interrupt request is not generated at the moment that the error occurred.)

An overrun error is generated when reception of the next data is completed before previously received data is read from the SC0RXB. In this event, the previously received data is lost. The overrun error indicator flag (SC0OEF) is updated at the moment the final data bit is received.

A parity error is generated when 0-fixed parity is set and a "1" is received, when 1-fixed parity is set and a "0" is received, when even parity is set and an odd number of ones is received, or when odd parity is set and an even number of ones is received. The parity error indicator flag (SC0PEF) is updated at the moment the parity bit are received.

A framing error is generated when "0" was received for the stop bit. The framing error indicator flag (SC0FEF) is updated at the moment the stop bit is received.

13-18

Serial Interface

<I2C mode>

??? I2C mode connection

It is possible to connect a device that is capable of slave transmission and slave reception. SDA and SCL require pull-up resistors. Connect pull-up resistors externally.

The SBO pin is an open-drain input/output, and the SBT pin is an open drain output.

Fig.13-2-14 Connections

13-19

Serial Interface

??? I2C mode transmission/reception

The transmission/reception procedure in I2C mode is described below. (Refer to Fig. 13-2-15.)

??? Make the initial settings as described below.

(1)I/O port setting

Set the SBT and SBO pins as general-purpose input ports. For details on the settings, refer to the chapter on I/O ports.

(2)Transmission/reception mode setting (SC0CTR register)

Be certain to set the flags listed below to the specified values.

Transmission operation enable flag (SC0TXE): 0

Flags other than those listed above may be set as desired.

However, the clock source must be selected from among the following four: 1/8 IOCLK

1/32 IOCLK

1/8 timer 3 underflow 1/8 timer 9 underflow

Set the parity bits each transmission/reception.

(3)I/O port setting

Set the I/O ports to SBT and SBO .

Leave the I/O port input/output control registers set to "input".

(4)Interrupt mode register setting (SC0ICR register) Set the interrupt sources as "transmission end".

(5)Transmission/reception enable

Enable both transmission and reception operations.

??? Send the start sequence (A) according to the procedure described below:

(1)Sending start sequence

When the I2C mode selection flag (SC0IIC) is changed from "0" to "1", a low signal is output on the SBO pin as the start sequence.

(2)Confirmation of sending start sequence

If the start sequence was generated normally, the I2C start sequence detection flag (SC0STF) changes to "1". In this case, even if there are simultaneous starts, "arbitration lost" is not detected.

13-20

Serial Interface

??? Perform data transmission/reception (B) according to the procedure described below:

(1)Ack setting

"Ack" is represented by the parity bits.

Set the parity bit selection flags (SC0PB2 to 0) to "1 fixed" or "0 fixed" in accordance with the communications protocol for the device that is connected. (When sending "Ack", set "0 fixed"; when sending NO-Ack, set "1 fixed ".)

(2)Transmission/reception

When transmitting, write the data that is to be transmitted in the transmission buffer (SC0TXB). When receiving, write "x'FF" in the transmission buffer (SC0TXB).

After the buffers are written, the clock signal is output and the transmission/reception operation is performed. After transmission/reception are completed, the low signal output is maintained on the SBT and SBO pins.

(3)Reading the reception buffer

Always be certain to read the reception buffer after the transmission/reception operation is completed. (It is necessary to read the reception buffer after a transmission operation.)

(4)Ack confirmation

Ack can be read as a parity error. Read the parity error indication flag (SC0PEF). When parity is set to "0 fixed", the value of SC0PEF is the value of Ack.

When parity is set to "1 fixed", the inverted value of SC0PEF is the value of Ack.

When performing consecutive transmission/reception operations, repeat steps (1) to (4).

??? Wait function under SCL control

The transmission/reception operation waits until SCL is released if SCL is driven low by a device performing slave transmission/reception. In this case, SCL goes high for 1/2 the normal interval (1/4 the one-bit width specified by the clock source selection flags (SC0CK2 to 0)).

??? Send the stop sequence (C) according to the procedure described below:

(1)Sending stop sequence

When the I2C mode selection flag (SC0IIC) is changed from "1" to "0", the SBT pin goes high. One IOCLK cycle after the SBT pin goes high, the SBO pin goes high and the stop sequence is sent.

(2)Confirmation of sending stop sequence

If the stop sequence was generated normally, the I2C stop sequence detection flag (SC0SPF) changes to "1".

(3)Transmission/reception disable

Disable the transmission operation and the reception operation.

(Set SC0TXE and SC0RXE to "0". Be sure to always perform this step every time after the stop sequence is sent.)

13-21

Serial Interface

If the above procedures do not satisfy the AC timing of the device that is connected, send the stop sequence according to the procedure described below.

(1)' SBT pin setting

Set the SBT pin as a general-purpose input port.

When the pin switches to a general-purpose input port, SCL goes high. (2)' SBO pin setting

Set the SBO pin as a general-purpose input port.

When the pin switches to a general-purpose input port, SDA goes high and the stop sequence is generated. (3)' Transmission/reception disable

Disable the transmission operation and the reception operation.

(Set SC0TXE and SC0RXE to "0". Be sure to always perform this step every time after the stop sequence is sent.)

(4)' I/O port setting

To perform further transmission/reception operations, set the I/O ports to SBT and SBO.

13-22

Serial Interface

??? Resend the start sequence (D) according to the procedure described below. (Refer to Fig. 13-2-16.)

(1)SBO pin setting

Set the SBO pin as a general-purpose input port.

When the pin switches to a general-purpose input port, SDA goes high.

(2)SBT pin setting

Set the SBT pin as a general-purpose input port.

When the pin switches to a general-purpose input port, SCL goes high.

(3)Control register setting

Disable the transmission operation and the reception operation. (Set SC0TXE and SC0RXE to "0".)

Set the I2C mode selection flag to "0".

(4)I/O port setting

Set the I/O ports to SBT and SBO.

(5)Transmission/reception enable

Enable the transmission operation and the reception operation. (Set SC0TXE and SC0RXE to "1".)

(6)Start sequence resend

Set the I2C mode selection flag to "1".

A low signal is output on the SBO pin, and the start sequence is sent.

At this point, normal transmission/reception is now possible.

(1)

SBT pin (SCL)

(2)

SC0IIC flag

Data write

SC0TXF flag

Interrupt request (set to ???transmission end???)

(D)

Start sequence resend

Fig. 13-2-16 Timing Chart (12)

13-23

Serial Interface

13.3 Clock Synchronous Serial Interface

13.3.1Features

Serial interfaces 1 and 2 are clock synchronous serial interfaces. Their features are described below.

??? ParityNone, 0 fixed, 1 fixed, even, odd

???Character length 7 bits, 8 bits

???Transmission and reception bit sequence

LSB or MSB selectable

??? Clock source 1/2, 1/8, or 1/32 of IOCLK (for either serial interface 1 or 2) 1/8 of timer 2 or timer 8 underflow, 1/2 of timer 8 underflow (for either serial interface 1)

1/8 of timer 3 or timer 9 underflow, 1/2 of timer 9 underflow (for either serial interface 2)

External clock (for either serial interface 1 or 2)

???Maximum bit rate

7.5Mbit/s (when IOCLK is 15 MHz)

???Error detection during reception