Safety Summary

The following general safety precautions must be observed during all phases of operation, service, and repair of this equipment. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment.

The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.

Ground the Instrument.

To minimize shock hazard, the equipment chassis and enclosure must be connected to an electrical ground. If the equipment is supplied with a three-conductor AC power cable, the power cable must be plugged into an approved three-contact electrical outlet, with the grounding wire (green/yellow) reliably connected to an electrical ground (safety ground) at the power outlet. The power jack and mating plug of the power cable meet International Electrotechnical Commission (IEC) safety standards and local electrical regulatory codes.

Do Not Operate in an Explosive Atmosphere.

Do not operate the equipment in any explosive atmosphere such as in the presence of flammable gases or fumes. Operation of any electrical equipment in such an environment could result in an explosion and cause injury or damage.

Keep Away From Live Circuits Inside the Equipment.

Operating personnel must not remove equipment covers. Only Factory Authorized Service Personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment. Service personnel should not replace components with power cable connected. Under certain conditions, dangerous voltages may exist even with the power cable removed. To avoid injuries, such personnel should always disconnect power and discharge circuits before touching components.

Use Caution When Exposing or Handling a CRT.

Breakage of a Cathode-Ray Tube (CRT) causes a high-velocity scattering of glass fragments (implosion). To prevent CRT implosion, do not handle the CRT and avoid rough handling or jarring of the equipment. Handling of a CRT should be done only by qualified service personnel using approved safety mask and gloves.

Do Not Substitute Parts or Modify Equipment.

Do not install substitute parts or perform any unauthorized modification of the equipment. Contact your local Motorola representative for service and repair to ensure that all safety features are maintained.

Observe Warnings in Manual.

Warnings, such as the example below, precede potentially dangerous procedures throughout this manual. Instructions contained in the warnings must be followed. You should also employ all other safety precautions which you deem necessary for the operation of the equipment in your operating environment.

To prevent serious injury or death from dangerous voltages, use extreme caution when handling, testing, and adjusting this equipment and its

Warning components.

Contents

vii

viii

ix

x

xi

List of Figures

xiii

List of Tables

xv

xvi

About This Manual

This manual provides general information, hardware preparation and installation instructions, operating instructions, and a functional description of the MVME2603/2604 family of single board computers.

As of the publication date, the information presented in this manual applies to the following MVME2603 and MVME2604 models:

xvii

Summary of Changes

This is the third edition of the Installation and Use manual. It supersedes the May 1998 edition and incorporates the following updates.

Overview of Contents

Chapter 1, Hardware Preparation and Installation, provides general information, hardware preparation and installation instructions, operating instructions, and a functional description of the MVME2603/2604 family of single board computers.

Chapter 2, Operating Instructions, supplies information for use of the MVME2603/2604 family of single board computers in a system configuration.

Chapter 3, Functional Description, describes the MVME2603/2604 single board computer on a block diagram level.

Chapter 4, Connector Pin Assignments, provides pin assignments for the interconnect signals for the MVME2603/2604 family of single board computers.

Chapter 5, PPCBug, describes the basics of PPCBug and its architecture, describes the monitor (interactive command portion of the firmware) in detail, and gives information on actually using the PPCBug debugger and the special commands.

Chapter 6, CNFG and ENV Commands, contains information about the CNFG and ENV commands. These two commands are used to change configuration information and command parameters interactively.

xviii

Appendix A, Specifications, lists the general specifications for

MVME2603/2604 base boards.

Appendix B, Serial Interconnections, describes the MVME2603/2604 serial communications interfaces.

Appendix C, Troubleshooting CPU Boards: Solving Startup Problems, supplies the user with troubleshooting tips before having to call for help.

Appendix D, Related Documentation, lists all documentation related to the MVME2603/2604 single board computer.

Comments and Suggestions

Motorola welcomes and appreciates your comments on its documentation. We want to know what you think about our manuals and how we can make them better. Mail comments to:

Motorola Computer Group

Reader Comments DW164

2900 S. Diablo Way

Tempe, Arizona 85282

You can also submit comments to the following e-mail address: reader-comments@mcg.mot.com

In all your correspondence, please list your name, position, and company. Be sure to include the title and part number of the manual and tell how you used it. Then tell us your feelings about its strengths and weaknesses and any recommendations for improvements.

xix

Conventions Used in This Manual

The following typographical conventions are used in this document:

bold

is used for user input that you type just as it appears; it is also used for commands, options and arguments to commands, and names of programs, directories and files.

italic

is used for names of variables to which you assign values. Italic is also used for comments in screen displays and examples, and to introduce new terms.

courier

is used for system output (for example, screen displays, reports), examples, and system prompts.

<Enter>, <Return> or <CR>

<CR> represents the carriage return or Enter key.

Ctrl

represents the Control key. Execute control characters by pressing the Ctrl key and the letter simultaneously, for example, Ctrl-d.

xx

Hardware Preparation and

Installation 1

Introduction

The MVME2603/2604 is a single-slot VME module equipped with a PowerPC?? Series microprocessor. The MVME2603 is equipped with a PowerPC 603??? microprocessor; the MVME2604 has a PowerPC 604??? microprocessor. 256KB L2 cache (level 2 secondary cache memory) is available as an option on all versions.

The complete MVME2603/2604 consists of the base board plus:

???An ECC DRAM module (RAM200) for memory

???An optional PCI mezzanine card (PMC) for additional versatility

???An optional carrier board for additional PCI expansion

The block diagram in Figure 1-1 illustrates the architecture of the

MVME2603/2604 base board.

1-1

Equipment Required

The following equipment is required to complete an MVME2603/2604 system:

???VME system enclosure

???System console terminal

???Operating system (and/or application software)

???Disk drives (and/or other I/O) and controllers

???Transition module (MVME712M or MVME761) and connecting cables

MVME2603/2604 VME modules are factory-configured for I/O handling via either MVME712M or MVME761 transition modules.

Overview of Startup Procedure

The following table lists the things you will need to do before you can use this board and tells where to find the information you need to perform each step. Be sure to read this entire chapter, including all Caution and Warning notes, before you begin.

Table 1-1. Startup Overview

Unpacking Instructions

Note If the shipping carton is damaged upon receipt, request that the carrier???s agent be present during the unpacking and inspection of the equipment.

Hardware Configuration

To produce the desired configuration and ensure proper operation of the MVME2603/2604, you may need to carry out certain hardware modifications before installing the module.

The MVME2603/2604 provides software control over most options: by setting bits in control registers after installing the module in a system, you can modify its configuration. (The MVME2603/2604 control registers are described in Chapter 3, Functional Description, and/or in the MVME2600 Series Single Board Computer Programmer???s Reference Guide, as listed in Appendix D, Related Documentation.)

Some options, however, are not software-programmable. Such options are controlled through manual installation or removal of header jumpers or interface modules on the base board or the associated transition module.

MVME2603/2604 Base Board Preparation

Figure 1-2 on page 1-9 illustrates the placement of the switches, jumper headers, connectors, and LED indicators on the MVME2603/2604. Manually configurable items on the base board include:

???Cache mode control (J3)

???Flash bank selection (J10)

???Serial Port 4 receive clock configuration (J16)

???Serial Port 4 transmit clock configuration (J17)

???Serial Port 4 transmit clock receiver buffer control (J20)

???Serial Port 3 transmit clock configuration (J18)

???System controller selection (J22)

In conjunction with the serial port settings on the base board, serial ports on the associated MVME712M or MVME761 transition module are also manually configurable. For a discussion of the configurable items on the transition module, refer to MVME712M Transition Module Preparation on page 1-14, MVME761 Transition Module Preparation on page 1-25, or to the respective user???s manuals for the transition modules (listed in Appendix D, Related Documentation) as necessary.

The MVME2603/2604 is factory tested and shipped with the configurations described in the following sections. The MVME2603/2604???s required and factory-installed debug monitor, PPCBug, operates with those factory settings.

Cache Mode Control (J3)

256KB of L2 cache memory is available on the MVME2603/2604. L2 cache operation is transparent to users, but its write-through mode is configurable via header J3 on older boards. On newer MVME2603/2604 boards, header J3 is not provided. With a jumper installed on J3, cache write-through is under CPU control. With the jumper removed, cache write-through occurs in all cases.

Flash Bank Selection (J10)

The MVME2603/2604 base board has provision for 1MB of 16-bit Flash memory. The RAM200 memory mezzanine accommodates 4MB or 8MB of additional 64-bit Flash memory.

The Flash memory is organized in either one or two banks, each bank either 16- or 64-bits wide. Both banks contain the onboard debugger, PPCBug.

To enable Flash bank A (4MB or 8MB of firmware resident on soldered- in devices on the RAM200 mezzanine), place a jumper across header J10 pins 1 and 2. To enable Flash bank B (1MB of firmware located in sockets on the base board), place a jumper across header J10 pins 2 and 3.

Serial Port 4 Receive Clock Configuration (J16)

In synchronous serial communications, you can configure Serial Port 4 on the MVME2603/2604 to use the clock signals provided by the RxC signal line. On MVME712M-compatible versions of the base board, header J16 configures port 4 to either drive or receive RxC. The factory configuration has port 4 set to receive RxC. J16 remains open on MVME761-compatible versions.

To complete the configuration of Serial Port 4, you must set the following configuration headers as well:

???J17 (Serial Port 4 transmit clock configuration)

???J20 (Serial Port 4 transmit clock receiver buffer control)

???J15 on the MVME712M transition module or J3 on the MVME761 transition module (Serial Port 4 clock configuration)

Figure 1-9 and Figure 1-10 (for the MVME712M) and Figure 1-14 and Figure 1-15 (for the MVME761) diagram the overall jumper settings required on the MVME2603/2604 and transition module for a Serial Port 4 DCE or DTE configuration.

For additional details on the configuration of those headers, refer to

MVME712M Transition Module Preparation on page 1-14, MVME761 Transition Module Preparation on page 1-25, or to the respective user???s manuals for the transition modules (listed in Appendix D, Related Documentation) as necessary.

(factory configuration)

Figure 1-2. MVME2603/2604 Switches, Headers, Connectors, Fuses, LEDs

Serial Port 4 Transmit Clock Configuration (J17)

In synchronous serial communications, you can configure Serial Port 4 on the MVME2603/2604 to use the clock signals provided by the TxC signal line. Header J17 configures port 4 to either drive or receive TxC. The factory configuration has port 4 set to receive TxC.

To complete the configuration of Serial Port 4, you must set the following configuration headers as well:

???J16 (Serial Port 4 receive clock configuration)

???J20 (Serial Port 4 transmit clock receiver buffer control)

???J15 on the MVME712M transition module or J3 on the MVME761 transition module (Serial Port 4 clock configuration)

Figure 1-9 and Figure 1-10 (for the MVME712M) and Figure 1-14 and Figure 1-15 (for the MVME761) diagram the overall jumper settings required on the MVME2603/2604 and transition module for a Serial Port 4 DCE or DTE configuration.

For additional details on the configuration of those headers, refer to

MVME712M Transition Module Preparation on page 1-14, MVME761 Transition Module Preparation on page 1-25, or to the respective user???s manuals for the transition modules (listed in Appendix D, Related Documentation) as necessary.

(factory configuration)

Serial Port 4 Transmit Clock Receiver Buffer Control (J20)

As described in other sections, a complete configuration of Serial Port 4 requires that you set the following jumper headers on the MVME2603/2604 or the transition module:

???J16 (Serial Port 4 receive clock configuration) on MVME712M- compatible versions of the base board

???J17 (Serial Port 4 transmit clock configuration)

???J20 (Serial Port 4 transmit clock receiver buffer control) on MVME712M-compatible versions of the base board

???J15 on the MVME712M transition module or J3 on the MVME761 (Serial Port 4 clock configuration)

A transmit clock receiver buffer (controlled by header J20) is associated with Serial Port 4. Installing a jumper on J20 enables the buffer. Removing the jumper disables the buffer. The factory configuration has the Serial Port 4 buffer enabled.

J20 remains open on MVME761-compatible versions. On MVME712M- compatible versions, J20 is set in tandem with J17 to configure the Serial Port 4 transmit clock. If one deviates from the factory configuration, so must the other.

Figure 1-9 and Figure 1-10 (for the MVME712M) and Figure 1-14 and Figure 1-15 (for the MVME761) diagram the overall jumper settings required on the MVME2603/2604 and transition module for a Serial Port 4 DCE or DTE configuration.

Serial Port 3 Transmit Clock Configuration (J18)

In synchronous serial communications using the MVME761 transition module, you can configure Serial Port 3 on the MVME2603/2604 to use the clock signals provided by the TxC signal line. On MVME761- compatible versions of the base board, header J18 configures port 3 to either drive or receive TxC. The factory configuration has port 3 set to receive TxC. J18 remains open on MVME712M-compatible versions.

To complete the configuration of Serial Port 3, you must set J2 on the MVME761 transition module (Serial Port 3 clock configuration) as well.

Figure 1-7 and Figure 1-8 (for the MVME712M) and Figure 1-14 and Figure 1-15 (for the MVME761) diagram the overall jumper settings required on the MVME2603/2604 and transition module for a Serial Port 3 DCE or DTE configuration.

System Controller Selection (J22)

The MVME2603/2604 is factory-configured as a VMEbus system controller by jumper header J22. If you select the ???automatic??? system controller function by placing a jumper on J22 pins 2 and 3, the MVME2603/2604 determines whether it is the system controller by its position on the bus. If the board is in the first slot from the left, it configures itself as the system controller. If the MVME2603/2604 is not to be system controller under any circumstances, place the jumper on J22 pins 1 and 2. When the board is functioning as system controller, the SCON LED is turned on.

Remote Status and Control

The MVME2603/2604 front panel LEDs and switches are mounted on a removable mezzanine board. Removing the LED mezzanine makes the mezzanine connector (J1, a keyed double-row 14-pin connector) available for service as a remote status and control connector. In this application, J1 can be connected to a user-supplied external cable to carry the Reset and Abort signals and the LED lines to a control panel located apart from the MVME2603/2604. Maximum cable length is 15 feet.

Table 4-1 in Chapter 4, Connector Pin Assignments lists the pin numbers and signal mnemonics for J1.

MVME712M Transition Module Preparation

The MVME712M transition module (Figure 1-3) and P2 adapter board are used in conjunction with the MVME2603/2604 base board.

The features of the MVME712M include:

???A parallel printer port

???An Ethernet interface supporting AUI connections

???One synchronous/asynchronous, and three asynchronous only, EIA-232-D multiprotocol serial ports

???An SCSI interface (via P2 adapter) for connection to both internal and external devices

???Socket-mounted SCSI terminating resistors for end-of-cable or middle-of-cable configurations

???Provision for modem connection

???Green LED for SCSI terminator power; yellow LED for Ethernet transceiver power

The features of the P2 adapter board include:

???A 50-pin connector for SCSI cabling to the MVME712M and/or to other SCSI devices

Serial Ports 1-4 DCE/DTE Configuration

Serial ports 1 through 4 are configurable as modems (DCE) for connection to terminals, or as terminals (DTE) for connection to modems. The MVME712M is shipped with the serial ports configured for DTE operation. Serial port DCE/DTE configuration is accomplished by positioning jumpers on one of two headers per port. The following table lists the serial ports with their corresponding jumper headers.

Table 1-2. MVME712M Port/Jumper Correspondence

The next six figures illustrate the MVME2603/2604 base board and MVME712M transition module with the interconnections and jumper settings for DCE/DTE configuration on each serial port.

Serial Port 4 Clock Configuration

Port 4 can be configured via J15 (Figure 1-4)to use the TrxC4 and RtxC4 signal lines. Part of the configuration is done with headers J16, J17, and J20 on the MVME2603/2604 (Figure 1-9 and Figure 1-10).

J15

Figure 1-4. J15 Clock Line Configuration

NOTE: J18 OPEN

11551.00 9609 (5-8)

Figure 1-7. MVME712M Serial Port 3 DCE Configuration

NOTE: J18 OPEN

11551.00 9609 (6-8)

Figure 1-8. MVME712M Serial Port 3 DTE Configuration

P2 Adapter Preparation

Preparation of the P2 adapter for the MVME712M consists of removing or installing the SCSI terminating resistors. Figure 1-11 illustrates the location of the resistors, fuse, and connectors.

For further information on the preparation of the transition module and the

P2 adapter, refer to the user???s manual for the MVME712M (listed in

Appendix D, Related Documentation) as necessary.

cb211 9212

Figure 1-11. MVME712M P2 Adapter Component Placement

MVME761 Transition Module Preparation

The MVME761 transition module (Figure 1-12) and P2 adapter board are used in conjunction with the MVME2603/2604 base board.

The features of the MVME761 include:

???A parallel printer port (IEEE 1284-I compliant)

???An Ethernet interface supporting 10BaseT/100BaseTX connections

???Two EIA-232-D asynchronous serial ports (identified as COM1 and COM2 on the front panel)

???Two synchronous serial ports (SERIAL 3 and SERIAL 4 on the front panel), configurable for EIA-232-D, EIA-530, V.35, or X.21 protocols

???Two 60-pin Serial Interface Module (SIM) connectors, used on configuring serial ports 3 and 4

The features of the P2 adapter board for the MVME761 include:

???A 50-pin connector for SCSI cabling to SCSI devices

???Jumper-selectable SCSI terminating resistors

???Fused SCSI terminator power developed from the +5V DC present at connector P2

???A 64-pin 3M connector to the MVME761

Serial Ports 1 and 2

On MVME761-compatible models of the MVME2603/2604 base board, the asynchronous serial ports (Serial Ports 1 and 2) are configured permanently as data circuit-terminating equipment (DCE). The port configuration is illustrated in Figure 1-13 on page 1-29.

Configuration of Serial Ports 3 and 4

The synchronous serial ports, Serial Port 3 and Serial Port 4, are configurable through a combination of serial interface module (SIM) selection and jumper settings. The following table lists the SIM connectors and jumper headers corresponding to each of the synchronous serial ports.

Port 3 is routed to board connector J7. Port 4 is available at board connector J8. Eight serial interface modules are available:

???EIA-232-D (DCE and DTE)

???EIA-530 (DCE and DTE)

???V.35 (DCE and DTE)

???X.21 (DCE and DTE)

You can configure Serial Ports 3 and 4 for any of the above serial protocols by installing the appropriate serial interface module and setting the corresponding jumper. SIMs can be ordered separately as required.

Figure 1-14. MVME761 Serial Ports 3 and 4 DCE Configuration

Figure 1-15. MVME761 Serial Ports 3 and 4 DTE Configuration

P2 Adapter Preparation (Three-Row)

The P2 adapter for the MVME761 transition module routes the synchronous and asynchronous serial, parallel, and Ethernet signals to the MVME761. The P2 adapter also has a 50-pin female connector (J2) that carries 8-bit SCSI signals from the MVME2603/2604. To run SCSI devices, you may install an additional transition module that is equipped with a SCSI port, such as the MVME712B.

Preparation of the P2 adapter for the MVME761 consists of installing a jumper on header J1 to enable the SCSI terminating resistors if necessary. Figure 1-16 illustrates the location of the jumper header, resistors, fuse, and connectors.

P2 Adapter Preparation (Five-Row)

The MVME761 transition module uses a five-row P2 adapter to transfer the synchronous and asynchronous serial, parallel, and Ethernet signals to and from the MVME2600 series VME module. The P2 adapter has a 68-pin female connector (J1) that carries 16-bit SCSI signals from the MVME2600. (To run SCSI devices, you may install an optional front panel extension, MVME761EXT, next to the MVME761. The panel extension supplies both 8- and 16-bit SCSI.) The P2 adapter for the MVME761 also supports PMC I/O via connectors J3 and J4.

Preparation of the P2 adapter for the MVME761 consists of installing a jumper on header J5 to enable the SCSI terminating resistors if necessary. Figure 1-17 illustrates the location of the jumper header and connectors.

Hardware Installation

RAM200 Memory Mezzanine Installation

The RAM200 DRAM mezzanine mounts on top of the MVME2603/2604 base board. To upgrade or install a RAM200 mezzanine, refer to

Figure 1-18 and proceed as follows:

1.Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure.

2.Perform an operating system shutdown. Turn the AC or DC power off and remove the AC cord or DC power lines from the system. Remove chassis or system cover(s) as necessary for access to the VME modules.

3.Carefully remove the MVME2603/2604 from its VMEbus card slot and lay it flat, with connectors P1 and P2 facing you.

4.Place the RAM200 mezzanine module on top of the base board. Connector J9 on the underside of the RAM200 should connect smoothly with the corresponding connector J7 on the MVME2603/2604.

11661.00 9611 (2-3)

Figure 1-18. RAM200 Placement on MVME2603/2604

5.Insert the four short Phillips screws through the holes at the corners of the RAM200, into the standoffs on the MVME2603/2604. Tighten the screws.

6.Reinstall the MVME2603/2604 assembly in its proper card slot. Be sure the module is well seated in the backplane connectors. Do not damage or bend connector pins.

7.Replace the chassis or system cover(s), reconnect the system to the AC or DC power source, and turn the equipment power on.

PMC Module Installation

PCI mezzanine card (PMC) modules mount beside the RAM200 mezzanine on top of the MVME2603/2604 base board. To install a PMC module, refer to Figure 1-19 and proceed as follows:

1.Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure.

2.Perform an operating system shutdown. Turn the AC or DC power off and remove the AC cord or DC power lines from the system. Remove chassis or system cover(s) as necessary for access to the VME modules.

3.Carefully remove the MVME2603/2604 from its VMEbus card slot and lay it flat, with connectors P1 and P2 facing you.

11661.00 9611 (3-3)

Figure 1-19. PMC Module Placement on MVME2603/2604

5.Slide the edge connector of the PMC module into the front panel opening from behind and place the PMC module on top of the base board. The four connectors on the underside of the PMC module should then connect smoothly with the corresponding connectors (J11/12/13/14) on the MVME2603/2604.

6.Insert the two short Phillips screws through the holes at the forward corners of the PMC module, into the standoffs on the MVME2603/2604. Tighten the screws.

7.Reinstall the MVME2603/2604 assembly in its proper card slot. Be sure the module is well seated in the backplane connectors. Do not damage or bend connector pins.

8.Replace the chassis or system cover(s), reconnect the system to the AC or DC power source, and turn the equipment power on.

PMC Carrier Board Installation

PCI mezzanine card (PMC) carrier boards mount above the RAM200 mezzanine and (if installed) PMC module on the MVME2603/2604 base board. To install a PMC carrier board for additional PCI expansion, refer to Figure 1-20 and proceed as follows:

1.Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure.

2.Perform an operating system shutdown. Turn the AC or DC power off and remove the AC cord or DC power lines from the system. Remove chassis or system cover(s) as necessary for access to the VME modules.

3.Carefully remove the MVME2603/2604 from its VMEbus card slot and lay it flat, with connectors P1 and P2 facing you.

4.If PMC modules are to be installed on the carrier board, install the modules at this point.

11661.00 9611 (1-3)

Figure 1-20. PMC Carrier Board Placement on MVME2603/2604

5.Remove the LED module screw located at the upper front corner of the base board. Install a short (0.394 inch) standoff in its place.

MVME2603/2604 VME Module Installation

Note Some VME backplanes (for example, those used in Motorola "Modular Chassis" systems) have an auto-jumpering feature for automatic propagation of the IACK and BG signals. Step 6 does not apply to such backplane designs.

MVME712M Transition Module Installation

This section applies to MVME712M-compatible models of the MVME2603/2604 VME module. With the MVME2603/2604 installed, refer to Figure 1-21 and proceed as follows to install an MVME712M transition module:

1.Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure.

2.Perform an operating system shutdown. Turn the AC or DC power off and remove the AC cord or DC power lines from the system. Remove chassis or system cover(s) as necessary for access to the VME modules.

The MVME2600, MVME712-compatible models will be damaged if

!mistakenly connected to the MVME761 transition modules instead of the

Caution correct MVME712 family of boards.

Note In models of the MVME2603/2604 that are configured for MVME712M I/O mode, the pin assignments of VMEbus connector P2 are fully compatible with other transition modules of the MVME712 series.

6.Secure the MVME712M in the chassis with the screws provided, making good contact with the transverse mounting rails to minimize RF emissions.

7.Referring to the user???s manual for the MVME712M (listed in Appendix D, Related Documentation), route the 50-conductor cable to the internal or external SCSI devices as appropriate to your system configuration. Be sure to orient cable pin 1 with connector pin 1.

Note The SCSI cabling can be configured in a number of ways to accommodate various device and system configurations. Figure 1-21 shows a possible configuration for use with internal SCSI devices. For more detailed information on installing the P2 adapter board and the MVME712M transition module, refer to the user???s manual (listed in Appendix D, Related Documentation).

MVME761 Transition Module Installation

This section applies to MVME761-compatible models of the MVME2603/2604 VME module. With the MVME2603/2604 installed, refer to Figure 1-22 and proceed as follows to install an MVME761 transition module:

1.Attach an ESD strap to your wrist. Attach the other end of the ESD strap to the chassis as a ground. The ESD strap must be secured to your wrist and to ground throughout the procedure.

2.Perform an operating system shutdown. Turn the AC or DC power off and remove the AC cord or DC power lines from the system. Remove chassis or system cover(s) as necessary for access to the VME modules.

The MVME2600, MVME761-compatible models will be damaged if

!mistakenly connected to the MVME712 family of boards instead of the

Caution correct MVME761 transition modules.

Note In MVME761-compatible models, certain signals are multiplexed through P2 for additional I/O capacity. Refer to P2 Signal Multiplexing on page 3-15 for details.

3.Remove the filler panel(s) from the appropriate card slot(s) at the front or rear of the chassis. (You may need to shift other modules in the chassis to allow space for the cabling to the MVME761.)

System Considerations

The MVME2603/2604 draws power from VMEbus backplane connectors P1 and P2. P2 is also used for the upper 16 bits of data in 32-bit transfers, and for the upper eight address lines in extended addressing mode. The MVME2603/2604 may not function properly without its main board connected to VMEbus backplane connectors P1 and P2.

Whether the MVME2603/2604 operates as a VMEbus master or as a VMEbus slave, it is configured for 32 bits of address and 32 bits of data (A32/D32). However, it handles A16 or A24 devices in the address ranges indicated in Chapter 2, Operating Instructions. D8 and/or D16 devices in the system must be handled by the PowerPC processor software. Refer to the memory maps in Chapter 2, Operating Instructions.

MVME2603/2604 VME Module

The MVME2603/2604 VME module furnishes +12V DC and (in MVME761 I/O mode) ???12V DC power to the transition module through polyswitches (resettable fuses) R34 and R28 respectively. These voltage sources power the serial port drivers and any LAN transceivers connected to the transition module. Fused +5V DC power is supplied to the base board???s keyboard and mouse connectors through polyswitch R30 and to

Operating Instructions 2

Introduction

This chapter supplies information for use of the MVME2603/2604 family of Single Board Computers in a system configuration. Here you will find the power-up procedure and descriptions of the switches and LEDs, memory maps, and software initialization.

Applying Power

After you have verified that all necessary hardware preparation has been done, that all connections have been made correctly, and that the installation is complete, you can power up the system. The MPU, hardware, and firmware initialization process is performed by the PowerPC PPCBug power-up or system reset. The firmware initializes the devices on the SBC module in preparation for booting the operating system.

The firmware is shipped from the factory with an appropriate set of defaults. In most cases there is no need to modify the firmware configuration before you boot the operating system.

The following flowchart shows the basic initialization process that takes place during PowerPC system startup.

For further information on PPCBug, refer to Chapter 5, PPCBug; to Appendix C, Troubleshooting CPU Boards: Solving Startup Problems; or to the PPCBug Firmware Package User???s Manual, listed in Appendix D, Related Documentation.

2-1

Operating Instructions

STARTUP

SYSTEM

INITIALIZATION

CONSOLE

DETECTION

RUN SELFTESTS

(IF ENABLED)

AUTOBOOT

(IF ENABLED)

OPERATING

SYSTEM

11734.00 9702

Figure 2-1. PPCBug System Startup

The MVME2603/2604 front panel has ABORT and RESET switches and six LED (light-emitting diode) status indicators (CHS, BFL, CPU, PCI, FUS, SYS). The switches and LEDs are mounted on an LED mezzanine board that plugs into the base board.

When activated by software, the ABORT switch can generate an interrupt signal from the base board to the processor at a user-programmable level. The interrupt is normally used to abort program execution and return control to the debugger firmware located in the MVME2603/2604 ROM and Flash memory. The interrupt signal reaches the processor module via ISA bus interrupt line IRQ8???. The signal is also available at pin PB7 of the Z8536 CIO device, which handles various status signals, serial I/O lines, and counters.

The interrupter connected to the ABORT switch is an edge-sensitive circuit, filtered to remove switch bounce.

RESET Switch (S2)

The RESET switch resets all onboard devices; it also drives a SYSRESET??? signal if the MVME2603/2604 is the system controller.

The Universe ASIC includes both a global and a local reset driver. When the Universe operates as the VMEbus system controller, the reset driver provides a global system reset by asserting the VMEbus signal SYSRESET???. A SYSRESET??? signal may be generated by the RESET switch, a power-up reset, a watchdog timeout, or by a control bit in the Miscellaneous Control Register (MISC_CTL) in the Universe ASIC. SYSRESET??? remains asserted for at least 200 ms, as required by the VMEbus specification.

Similarly, the Universe ASIC supplies an input signal and a control bit to initiate a local reset operation. By setting a control bit, software can maintain a board in a reset state, disabling a faulty board from participating in normal system operation. The local reset driver is enabled even when the Universe ASIC is not system controller. Local resets may be generated by the RESET switch, a power-up reset, a watchdog timeout, a VMEbus SYSRESET???, or a control bit in the MISC_CTL register.

There are six LEDs on the MVME2603/2604 front panel: CHS, BFL, CPU,

PCI, FUS, and SYS.

??? CHS (DS1, yellow). Checkstop; driven by the MPC603/604 status lines on the MVME2603/2604. Lights when a halt condition from the processor is detected.

??? BFL (DS2, yellow). Board Failure; lights when the BRDFAIL??? signal line is active.

??? CPU (DS3, green). CPU activity; lights when the DBB??? (Data Bus Busy) signal line on the processor bus is active.

??? PCI (DS4, green). PCI activity; lights when the IRDY??? (Initiator Ready) signal line on the PCI bus is active. This indicates that the PCI mezzanine (if installed) is active.

??? FUS (DS5, green). Fuse OK; lights when +5V DC, +12V DC, and ???12V DC power is available from the base board to the transition module and remote devices.

Note Because the FUS LED monitors the status of several voltages on the MVME2603/2604, it does not directly indicate the condition of any single fuse. If the LED flickers or goes out, check all the fuses (polyswitches).

??? SYS (DS6, green). System Controller; lights when the Universe ASIC in the MVME2603/2604 is the VMEbus system controller.

Memory Maps

There are three points of view for memory maps:

???The mapping of all resources as viewed by the processor (MPU bus memory map)

???The mapping of onboard resources as viewed by PCI local bus masters (PCI bus memory map)

???The mapping of onboard resources as viewed by VMEbus masters (VMEbus memory map)

The following sections give a general description of the MVME2603/2604 memory organization from the above three points of view. Detailed memory maps can be found in the MVME2600 Series Single Board Computer Programmer???s Reference Guide, listed in Appendix D, Related Documentation.

Processor Memory Map

The processor memory map configuration is under the control of the Raven bridge controller ASIC and the Falcon memory controller chip set. The Raven and Falcon devices adjust system mapping to suit a given application via programmable map decoder registers. At system power-up or reset, a default processor memory map takes over.

PCI Local Bus Memory Map

The PCI memory map is controlled by the Raven MPU/PCI bus bridge controller ASIC and by the Universe PCI/VME bus bridge ASIC. The Raven and Universe devices adjust system mapping to suit a given application via programmable map decoder registers.

No default PCI memory map exists. Resetting the system turns the PCI map decoders off, and they must be reprogrammed in software for the intended application.

For detailed PCI memory maps, including suggested CHRP- and PREP- compatible memory maps, refer to the MVME2600 Series Single Board Computer Programmer???s Reference Guide, listed in Appendix D, Related Documentation.

VMEbus Memory Map

The VMEbus is programmable. Like other parts of the MVME2603/2604 memory map, the mapping of local resources as viewed by VMEbus masters varies among applications.

The Universe PCI/VME bus bridge ASIC includes a user-programmable map decoder for the VMEbus-to-local-bus interface. The address translation capabilities of the Universe enable the processor to access any range of addresses on the VMEbus.

Recommendations for VMEbus mapping, including suggested CHRP- and PREP-compatible memory maps, can be found in the MVME2600 Series Single Board Computer Programmer???s Reference Guide, listed in Appendix D, Related Documentation. Figure 2-2 on page 2-9 shows the overall mapping approach from the standpoint of a VMEbus master.

Good programming practice dictates that only one MPU at a time have control of the MVME2603/2604 control registers. Of particular note are:

???Registers that modify the address map

???Registers that require two cycles to access

???VMEbus interrupt request registers

NOTES: 1. Programmable mapping done by Raven ASIC.

11553.00 9609

2.Programmable mapping performed via PCI Slave images in Universe ASIC.

3.Programmable mapping performed via Special Slave image (SLSI) in Universe ASIC.

Figure 2-2. VMEbus Master Mapping

There are seven potential PCI bus masters on the MVME2603/2604 single board computer:

???Raven ASIC (MPU/PCI bus bridge controller)

???Winbond W83C553 PIB (PCI/ISA bus bridge controller)

???DECchip 21140 Ethernet controller

???SYM53C825A SCSI controller

???Universe ASIC (PCI/VME bus bridge controller)

???PMC Slot 1 (PCI mezzanine card)

???PMC Slot 2 (PCI expansion)

The Winbond W83C553 PIB device supplies the PCI arbitration support for these seven types of devices. The PIB supports flexible arbitration modes of fixed priority, rotating priority, and mixed priority, as appropriate in a given application. Details on PCI arbitration can be found in the MVME2600 Series Single Board Computer Programmer???s Reference Guide, listed in Appendix D, Related Documentation.

The arbitration assignments for the MVME2603/2604 are shown in the following table.

Table 2-2. PCI Arbitration Assignments

The Raven ASIC, which controls PHB (PCI Host Bridge) MPU/local bus interface functions on the MVME2603/2604, performs interrupt handling as well. Sources of interrupts may be any of the following:

???The Raven ASIC itself (timer interrupts or transfer error interrupts)

???The processor (processor self-interrupts)

???The Falcon chip set (memory error interrupts)

???The PCI bus (interrupts from PCI devices)

???The ISA bus (interrupts from ISA devices)

Figure 2-3 illustrates interrupt architecture on the MVME2603/2604. For details on interrupt handling, refer to the MVME2600 Series Single Board Computer Programmer???s Reference Guide, listed in Appendix D, Related Documentation.

Operating Instructions

INT

INT_

SERR_& PERR_

PCI Interrupts

ISA Interrupts

11559.00 9609

Figure 2-3. MVME2603/MVME2604 Interrupt Architecture

The PIB supports seven DMA channels. Channels 0 through 3 support 8-bit DMA devices. Channels 5 through 7 are dedicated to 16-bit DMA devices. The channels are allocated as follows:

Table 2-3. IBC DMA Channel Assignments

Sources of Reset

The MVME2603/2604 SBC has eight potential sources of reset:

1.Power-on reset

2.RESET switch (resets the VMEbus when the MVME2603/2604 is system controller)

3.Watchdog timer Reset function controlled by the SGS-Thomson MK48T559 timekeeper device (resets the VMEbus when the MVME2603/2604 is system controller)

The MVME2603/2604 supports both little-endian (for example, Windows NT) and big-endian (for example, AIX) software. The PowerPC processor and the VMEbus are inherently big-endian, while the PCI bus is inherently little-endian. The following sections summarize how the MVME2603/2604 handles software and hardware differences in big- and little-endian operations. For further details on endian considerations, refer to the MVME2600 Series Single Board Computer Programmer???s Reference Guide, listed in Appendix D, Related Documentation.

Processor/Memory Domain

The MPC603/604 processor can operate in both big-endian and little-endian mode. However, it always treats the external processor/memory bus as big-endian by performing address rearrangement and reordering when running in little-endian mode. The MPC registers in the Raven MPU/PCI bus bridge controller ASIC and the Falcon memory controller chip set, as well as DRAM, ROM/Flash, and system registers, always appear as big-endian.

Role of the Raven ASIC

Because the PCI bus is little-endian, the Raven performs byte swapping in both directions (from PCI to memory and from the processor to PCI) to maintain address invariance while programmed to operate in big-endian mode with the processor and the memory subsystem.

In little-endian mode, the Raven reverse-rearranges the address for PCI- bound accesses and rearranges the address for memory-bound accesses (from PCI). In this case, no byte swapping is done.

PCI Domain

The PCI bus is inherently little-endian. All devices connected directly to the PCI bus operate in little-endian mode, regardless of the mode of operation in the processor???s domain.

Functional Description 3

Introduction

This chapter describes the MVME2603/2604 single board computer on a block diagram level. The General Description provides an overview of the MVME2603/2604, followed by a detailed description of several blocks of circuitry. Figure 3-1 shows a block diagram of the overall board architecture.

Detailed descriptions of other MVME2603/2604 blocks, including programmable registers in the ASICs and peripheral chips, can be found in the Programmer???s Reference Guide, listed in Appendix D, Related Documentation. Refer to it for a functional description of the MVME2603/2604 in greater depth.

Features

The following table summarizes the features of the MVME2603/2604 single board computers.

3-1

General Description

The MVME2603/2604 is a VME module single board computer equipped with a PowerPC Series microprocessor. The MVME2603 is equipped with a PowerPC 603 microprocessor; the MVME2604 has a PowerPC 604.

256KB L2 cache (level 2 secondary cache memory) is available as an option on all versions.

As shown in the Features section, The MVME2603/2604 offers many standard features desirable in a computer system???such as synchronous and asynchronous serial ports, parallel port, boot ROM and DRAM, SCSI, Ethernet, support for an external disk drive, and keyboard and mouse support???in a single-slot VME package. Its flexible mezzanine architecture allows relatively easy upgrades in memory and functionality.

A key feature of the MVME2603/2604 family is the PCI (Peripheral Component Interconnect) bus. In addition to the on-board local bus peripherals, the PCI bus supports an industry-standard mezzanine interface, IEEE P1386.1 PMC (PCI Mezzanine Card). PMC modules offer a variety of possibilities for I/O expansion through FDDI (Fiber Distributed Data Interface), ATM (Asynchronous Transfer Mode), graphics, Ethernet, or SCSI ports. The base board supports PMC front panel I/O. There is also provision for additional expansion via a PMC carrier board.

Functional Description

Block Diagram

Falcon

Dram

Falcon

ISA Local Resource Bus

FLASH

33MHz 32/64-BIT PCI Local Bus

11540.00 96111 (3-3)

Figure 3-1. MVME2603/2604 Block Diagram

Block Diagram

SCSI Interface

SCSI Termination

The individual configuring the system must ensure that the SCSI bus is properly terminated at both ends.

In MVME712M I/O mode, the MVME2603/2604 base board uses the sockets provided for SCSI bus terminators on the P2 adapter board used with the MVME712M. If the SCSI bus ends at the adapter board, termination resistors must be installed there. +5V DC power to the SCSI bus TERMPWR signal and termination resistors is supplied through a fuse located on the adapter board.

In MVME761 I/O mode, the P2 adapter board used with the MVME761 has a jumper to enable/disable SCSI bus terminators. +5V DC power for SCSI termination is supplied through a polyswitch located on the adapter board.

Functional Description

Ethernet Interface

Note The unique Ethernet address is set at the factory and should not be changed. Any attempt to change this address may create node or bus contention and thereby render the board inoperable.

If the data in SROM is lost, use the number on the label in the PMC connector keepout area to restore it.

For the pin assignments of the transition module AUI or 10BaseT/100BaseTX connector, refer to the user???s manual for the MVME712M or MVME761 (listed in Appendix D, Related Documentation) respectively. Refer to the BBRAM/TOD Clock memory

Block Diagram

map description in the MVME2600 Series Single Board Computer Programmer???s Reference Guide, listed in Appendix D, Related Documentation, for detailed programming information.

3

PCI Mezzanine Interface

A key feature of the MVME2603/2604 family is the PCI (Peripheral Component Interconnect) bus. In addition to the on-board local bus devices (SCSI, Ethernet, graphics, etc.), the PCI bus supports an industry- standard mezzanine interface, IEEE P1386.1 PMC (PCI Mezzanine Card).

PMC modules offer a variety of possibilities for I/O expansion through FDDI (Fiber Distributed Data Interface), ATM (Asynchronous Transfer Mode), graphics, Ethernet, or SCSI ports. The base board supports PMC front panel and rear P2 I/O. There is also provision for stacking a PMC carrier board on the base board for additional expansion.

The MVME2603/2604 supports one PMC slot. Four 64-pin connectors on the base board (J11, J12, J13, and J14) interface with 32-bit IEEE P1386.1 PMC-compatible mezzanines to add any desirable function. The PCI Mezzanine Card slot has the following characteristics:

Mezzanine Type PMC (PCI Mezzanine Card)

Mezzanine Size S1B: Single width, standard depth (75mm x 150mm) with front panel

PMC Connectors J11 and J12 (32/64-bit PCI with front and rear I/O)

The PMC carrier board connector (J5) is a 114-pin Mictor connector.

Refer to Chapter 4, Connector Pin Assignments for the pin assignments of the PMC connectors. For detailed programming information, refer to the PCI bus descriptions in the MVME2603/2604 Programmer???s Reference Guide, listed in Appendix D, Related Documentation, and to the user documentation for the PMC modules you intend to use.

Functional Description

VMEbus Interface

The Universe chip includes Universe Control and Status Registers (UCSRs) for interprocessor communications. It can provide the VMEbus system controller functions as well. For detailed programming information, refer to the Universe User???s Manual and to the discussions in the MVME2603/2604 Programmer's Reference Guide,listed in Appendix D, Related Documentation.

ISA Super I/O Device (ISASIO)

The MVME2603/2604 uses a PC87308 ISASIO chip from National Semiconductor to implement certain segments of the P2 and front-panel I/O:

???Two asynchronous serial ports (COM1 and COM2) via P2 and transition module

???Parallel port via P2 and transition module:

???Centronics printer port in MVME712M-compatible models

???IEEE1284 bidirectional parallel port in MVME761-compatible models

???Floppy disk drive support via drive/power connector J4

???Keyboard and mouse interface via circular DIN connectors J6 and J8

PCI-ISA Bridge (PIB) Controller

The MVME2603/2604 uses a Winbond W83C553 bridge controller to supply the interface between the PCI local bus and the ISA system I/O bus (diagrammed in Figure 1-1 in Chapter 1, Hardware Preparation and Installation).

Real-Time Clock/NVRAM/Timer Function

The MVME2603/2604 employs an SGS-Thomson surface-mount M48T59/T559 RAM and clock chip to provide 8KB of non-volatile static RAM, a real-time clock, and a watchdog timer function. This chip supplies a clock, oscillator, crystal, power failure detection, memory write protection, 8KB of NVRAM, and a battery in a package consisting of two parts:

Programmable Timers

Among the resources available to the local processor are a number of programmable timers. Timers are incorporated into the PIB controller and the Z8536 CIO device (diagrammed in Figure 1-1 on page 1-2 and Figure 3-1 on page 3-4). They can be programmed to generate periodic interrupts to the processor.

Interval Timers

The PCI-ISA Bridge controller has three built-in counters that are equivalent to those found in an 82C54 programmable interval timer. The counters are grouped into one timer unit, Timer 1, in the PIB controller. Each counter output has a specific function:

???Counter 0 is associated with interrupt request line IRQ0. It can be used for system timing functions, such as a timer interrupt for a time-of-day function.

???Counter 1 generates a refresh request signal for ISA memory. This timer is not used in the MVME2603/2604.

Serial Communications Interface

The MVME2603/2604 uses a Zilog Z85230 ESCC (Enhanced Serial Communications Controller) to implement the two serial communications interfaces, which are routed through P2. The Z85230 supports synchronous (SDLC/HDLC) and asynchronous protocols. The MVME2603/2604 hardware supports asynchronous serial baud rates of 110B/s to 38.4KB/s.

Each interface supports the CTS, DCD, RTS, and DTR control signals as well as the TxD and RxD transmit/receive data signals, and TxC/RxC synchronous clock signals. Since not all modem control lines are available in the Z85230, a Z8536 CIO is used to provide the missing modem lines.

A PAL device performs decoding of register accesses and pseudo interrupt acknowledge cycles for the Z85230 and the Z8536 in ISA I/O space. The PIB controller supplies DMA support for the Z85230.

The Z85230 receives a 10MHz clock input. The Z85230 supplies an interrupt vector during pseudo interrupt acknowledge cycles. The vector is modified within the Z85230 according to the interrupt source. Interrupt request levels are programmed via the PIB controller. Refer to the Z85230 data sheet and to the MVME2603/ MVME2604 Programmer???s Reference Guide, both listed in Appendix D, Related Documentation, for further information.

Functional Description

Base Module Feature Register

The Base Module Feature Register contains the details of the MVME2603/2604 single board computer???s configuration. It is an 8-bit read-only register located on the base board at ISA I/O address $0802.

Base Module Feature Register ??? Offset $0802

SCCP??? Z85230 ESCC present. If set, there is no on-board synchronous serial support (the ESCC is not present). If cleared, the Z85230 ESCC is installed and there is on-board support for synchronous serial communication.

PMC2P??? PMC/PMCIX slot 2 present. If set, no PCI mezzanine card (or PCI expansion device) is installed in PMC slot 2. If cleared, PMC/PMCIX slot 2 contains a PCI mezzanine card (or PCI expansion device).

PMC1P??? PMC slot 1 present. If set, no PCI mezzanine card is installed in PMC slot 1. If cleared, PMC slot 1 contains a PCI mezzanine card.

VMEP??? VMEbus present. If set, there is no VMEbus interface. If cleared, the VMEbus interface is supported.

LANP??? Ethernet present. If set, no Ethernet transceiver interface is installed. If cleared, there is on-board Ethernet support.

Block Diagram

SCSIP??? SCSI present. If set, there is no on-board SCSI interface. If cleared, on-board SCSI is supported.

Due to the limited supply of available pins in the P2 backplane connectors of MVME2603/2604 models that are configured for MVME761 I/O mode, certain signals are multiplexed through VMEbus connector P2 for additional I/O capacity.

The signals affected are synchronous I/O control signals that pass between the base board and the MVME761 transition module. The multiplexing is a hardware function that is entirely transparent to software.

Four signals are involved in the P2 multiplexing function: MXDO, MXDI,

MXCLK, and MXSYNC???.

MXDO is a time-multiplexed data output line from the main board and MXDI is a time-multiplexed line from the MVME761 module. MXCLK is a 10 MHz bit clock for the MXDO and MXDI data lines. MXSYNC??? is asserted for one bit time at time slot 15 (Table 3-2) by the MVME2603/2604 base board. The MVME761 transition module uses MXSYNC??? to synchronize with the base board.

A 16-to-1 multiplexing scheme is used with MXCLK???s 10 MHz bit rate. 16 time slots are defined and allocated as follows:

Table 3-2. P2 Multiplexing Sequence

Functional Description

ABORT Switch (S1)

The ABORT switch is located on the LED mezzanine. When activated by software, the ABORT switch can generate an interrupt signal from the base board to the processor. The interrupt is normally used to abort program execution and return control to the debugger firmware located in the MVME2603/2604 EPROM and Flash memory. The interrupt signal reaches the processor module via ISA bus interrupt line IRQ8???. The signal is also available at pin PB7 of the Z8536 CIO device, which handles various status signals, serial I/O lines, and counters.

The interrupter connected to the ABORT switch is an edge-sensitive circuit, filtered to remove switch bounce.

RESET Switch (S2)

The RESET switch is located on the LED mezzanine. The RESET switch resets all onboard devices; it also drives a SYSRESET??? signal if the MVME2603/2604 is the system controller.

Block Diagram

Front Panel Indicators (DS1 ??? DS6)

Note Because the FUS LED monitors the status of several voltages on the MVME2603/2604, it does not directly indicate the condition of any single fuse. If the LED flickers or goes out, check all the fuses (polyswitches).

??? SYS (DS6, green). System Controller; lights when the Universe ASIC in the MVME2603/2604 is the VMEbus system controller.

Functional Description

Polyswitches (Resettable Fuses)

I/O Power

The MVME2603/2604 base board furnishes +12V DC and (in MVME761 I/O mode) ???12V DC power to the transition module through polyswitches (resettable fuses) R34 and R28 respectively. These voltage sources power the serial port drivers and any LAN transceivers connected to the transition module. Fused +5V DC power is supplied to the base board???s keyboard and mouse connectors through polyswitch R30 and to the 14-pin combined LED-mezzanine/remote-reset connector, J1. The FUS LED (DS5) on the MVME2603/2604 front panel illuminates when all three voltages are available.

In MVME712M I/O mode, the yellow DS1 LED on the MVME712M also signals the availability of +12V DC LAN power, indicating in turn that polyswitch R34 is good. If the Ethernet transceiver fails to operate, check polyswitch R34.

In MVME712M I/O mode, the MVME2603/2604 supplies SCSI terminator power through a 1A fuse (F1) located on the P2 adapter board. If the fuse is blown, the SCSI device(s) may function erratically or not at all. With the P2 adapter board cabled to a transition module and with an SCSI bus connected to the transition module, the green SCSI LED on the

Block Diagram

module illuminates when SCSI terminator power is available. If the SCSI LED on the transition module flickers during SCSI bus operation, check fuse F1 on the P2 adapter board.

Note Because any device on the SCSI bus can provide TERMPWR, and because the FUS LED monitors the status of several voltages, the LED does not directly indicate the condition of any single fuse. If the LED flickers or goes out, check all the fuses (polyswitches).

In MVME761 I/O mode, the MVME2603/2604 supplies SCSI terminator power through a polyswitch (resettable fuse) located on the P2 adapter board.

Speaker Control

The MVME2603/2604 base board supplies a SPEAKER_OUT signal to the 14-pin combined LED-mezzanine/remote-reset connector, J1. When J1 is used as a remote reset connector with the LED mezzanine removed, the SPEAKER_OUT signal can be cabled to an external speaker to obtain a beep tone. For the pin assignments of J1, refer to Table 4-1 in Chapter 4,

Connector Pin Assignments.

PM603/604 Processor

At present, you have the choice of a PowerPC 603 or a PowerPC 604 processor chip with 16MB to 256MB of ECC DRAM, 256KB of level 2 cache (L2 cache), and up to 9MB of Flash memory. The L2 cache and 1MB of 16-bit Flash memory reside on the MVME2603/2604 base board. The ECC DRAM and 4MB or 8MB of additional (64-bit) Flash memory are located on the RAM200 memory mezzanine.

The PowerPC 603 is a 64-bit processor with 32KB on-chip cache (16KB data cache and 16KB instruction cache). The PowerPC 604 is a 64-bit processor with 32KB on-chip cache (16KB data cache and 16KB instruction cache).

RAM200 Memory Module

The RAM200 is the ECC DRAM memory mezzanine module that (together with an LED mezzanine and an optional PCI mezzanine card) plugs into the base board to make a complete MVME2603 or MVME2604 single board computer. See Figure 1-18 on page 1-37.

MVME712M Transition Module

The MVME712M transition module (Figure 1-3 on page 1-16) and P2 adapter board are used in conjunction with the MVME2603/2604 base board.

The features of the MVME712M include:

???A parallel printer port (via P2 adapter)

???An Ethernet interface supporting AUI connections (via P2 adapter)

???Four EIA-232-D multi-protocol serial ports (via P2 adapter)

???An SCSI interface (via P2 adapter) for connection to both internal and external devices

???Socket-mounted SCSI terminating resistors for end-of-cable or middle-of-cable configurations

???Provision for modem connection

???Green LED for SCSI terminator power; yellow LED for Ethernet transceiver power

The features of the P2 adapter board include:

???A 50-pin connector for SCSI cabling to the MVME712M and/or to other SCSI devices

???Socket-mounted SCSI terminating resistors for end-of-cable or middle-of-cable configurations

MVME761 Transition Module

The MVME761 transition module (Figure 1-12 on page 1-26) and P2 adapter board are used in conjunction with the MVME2603/2604 base board.

The features of the MVME761 include:

???A parallel printer port (IEEE 1284-I compliant)

???An Ethernet interface supporting 10BaseT/100BaseTX connections

???Two EIA-232-D asynchronous serial ports (identified as COM1 and COM2 on the front panel)

???Two synchronous serial ports (SERIAL 3 and SERIAL 4 on the front panel), configurable for EIA-232-D, EIA-530, V.35, or X.21 protocols

???Two 60-pin Serial Interface Module (SIM) connectors

Serial Interface Modules

The synchronous serial ports on the MVME761 are configurable via serial interface modules (SIMs), used in conjunction with the appropriate jumper settings on the transition module and base board. The SIMs are small plug- in printed circuit boards which contain all the circuitry needed to convert

Connector Pin Assignments 4

MVME2603/2604 Connectors

This chapter summarizes the pin assignments for the following groups of interconnect signals for the MVME2603/2604:

???Connectors with pin assignments common to MVME712M, as well as MVME761-compatible versions of the base board

Connector

LED Mezzanine Connector J1 on page 4-3

Debug Connector J2 on page 4-4

Floppy/LED Connector J4 on page 4-7

PCI Expansion Connector J5 on page 4-8

Keyboard and Mouse Connectors J6, J8 on page 4-11

DRAM Mezzanine Connector J7 on page 4-12

PCI Mezzanine Card Connectors on page 4-15

VMEbus Connector P1 on page 4-18

???Connectors with pin assignments specific to MVME712M- compatible versions of the base board

Connector

VMEbus Connector P2 on page 4-19

SCSI Connector on page 4-21

Serial Ports 1-4 on page 4-22

Parallel Connector on page 4-23

Ethernet AUI Connector on page 4-24

4-1

Common Connectors

Common Connectors

The following tables describe connectors used with the same pin assignments by MVME712M, as well as MVME761-compatible versions of the base board.

A 14-pin connector (J1 on the base board) supplies the interface between the base board and the LED mezzanine module. On the base board, this connector is a 2x7 header. On the LED mezzanine, it is a 2x7 surface- mount socket strip.

Removing the LED mezzanine makes the mezzanine connector available for service as a remote status and control connector. In this application, J1 can be connected to a user-supplied external cable to carry the Reset and Abort signals and the LED lines to a control panel located apart from the MVME2603/2604. Maximum cable length is 15 feet. The pin assignments are as follows:

Table 4-1. LED Mezzanine Connector

Connector Pin Assignments

Debug Connector J2

Floppy/LED Connector J4

A 50-pin high-density connector (J4 on the base board) supplies the interface between the base board and an optional external floppy disk drive. In addition to the disk drive control signals, a set of 16 lines is available to drive an external LED array. The pin assignments are listed in the following table.

Table 4-3. Floppy/LED Connector

Connector Pin Assignments

PCI Expansion Connector J5

The MVME2603/2604 has provision for stacking a PMC carrier board on the base board for additional PCI expansion. A 114-pin connector (J5 on the base board) supplies the interface between the MVME2603/2604 and the carrier board. The pin assignments are listed in the following table.

Table 4-4. PCI Expansion Connector

Common Connectors

Keyboard and Mouse Connectors J6, J8

Table 4-6. Mouse Connector

Connector Pin Assignments

DRAM Mezzanine Connector J7

Common Connectors

PCI Mezzanine Card Connectors

Four 64-pin connectors (J11/12/13/14 on the MVME2603/2604) supply the interface between the base board and an optional PCI mezzanine card (PMC). The pin assignments are listed in Table 4-8.

Table 4-8. PCI Mezzanine Card Connector

Connector Pin Assignments

VMEbus Connector P1

MVME712M-Compatible Versions

The following tables summarize the pin assignments of connectors that are specific to MVME2603/2604 modules configured for use with MVME712M transition modules.

VMEbus Connector P2

Two 160-pin connectors (P1 and P2) supply the interface between the base board and the VMEbus. P1 provides power and VME signals for 24-bit addressing and 16-bit data. Its pin assignments are set by the VMEbus specification. P2 rows A, C, Z, and D provide power and interface signals to the MVME712M transition module. P2 row B supplies the MVME2603/2604 with power, with the upper eight VMEbus address lines, and with an additional 16 VMEbus data lines. The pin assignments for P2 are listed in the following table.

Table 4-10. VMEbus Connector P2 (MVME712M I/O Mode)

MVME712M-Compatible Versions

SCSI Connector

Connector Pin Assignments

Serial Ports 1-4

Connector Pin Assignments

Table 4-13. Parallel I/O Connector (MVME712M) (Continued)

Ethernet AUI Connector

The MVME2603/2604 provides both AUI and 10BaseT/100BaseTX LAN connections. For MVME712M-compatible base boards, the LAN interface is an AUI connection implemented with a DB15 connector (J6) located on the MVME712M transition module. The pin assignments are listed in the following table.

Table 4-14. Ethernet AUI Connector (MVME712M)

MVME761-Compatible Versions

MVME761-Compatible Versions

The following tables summarize the pin assignments of connectors that are specific to MVME2603/2604 modules configured for use with MVME761 transition modules.

Two 160-pin connectors (P1 and P2) supply the interface between the base board and the VMEbus. P1 provides power and VME signals for 24-bit addressing and 16-bit data. Its pin assignments are set by the VMEbus specification. P2 rows A, C, Z, and D provide power and interface signals to the MVME761 transition module. P2 row B supplies the MVME2603/2604 with power, with the upper eight VMEbus address lines, and with an additional 16 VMEbus data lines. The pin assignments for P2 are listed in the following table.

Table 4-15. VMEbus Connector P2 (MVME761 I/O Mode)

Connector Pin Assignments

Serial Ports 1 and 2

The MVME2603/2604 provides both asynchronous (ports 1 and 2) and synchronous/asynchronous (ports 3 and 4) serial connections. For the MVME761-compatible versions of the base board, the asynchronous interface is implemented with a pair of DB9 connectors (COM1 and COM2) located on the MVME761 transition module. The pin assignments are listed in the following table.

Table 4-16. Serial Connections???Ports 1 and 2 (MVME761)

Parallel Connector

Both versions of the base board provide parallel I/O connections. For MVME761-compatible models, the parallel interface is implemented with an IEEE P1284 36-pin connector (J10) located on the MVME761 transition module. The pin assignments are listed in the following table.

Table 4-18. Parallel I/O Connector (MVME761)

MVME761-Compatible Versions

Ethernet 10BaseT/100BaseTX Connector

The MVME2603/2604 provides both AUI and 10BaseT/100BaseTX LAN connections. For MVME761-compatible base boards, the LAN interface is a 10BaseT/100BaseTX connection implemented with a standard RJ-45 socket located on the MVME761 transition module. The pin assignments are listed in the following table.

Table 4-19. Ethernet 10BaseT/100BaseTX Connector (MVME761)

For detailed descriptions of the various interconnect signals, consult the support information documentation package for the MVME2603/2604 SBC or the support information sections of the transition module documentation as necessary.

PPCBug 5

Overview

The PowerPC debugger, PPCBug, is a powerful evaluation and debugging tool for systems built around Motorola PowerPC microcomputers. Facilities are available for loading and executing user programs under complete operator control for system evaluation.

The PowerPC debugger provides a high degree of functionality and user friendliness, and yet stresses portability and ease of maintenance. It achieves good portability and comprehensibility because it was written entirely in the C programming language, except where necessary to use assembler functions.

PPCBug includes commands for display and modification of memory, breakpoint and tracing capabilities, a powerful assembler and disassembler useful for patching programs, and a "self-test at power-up" feature which verifies the integrity of the main CPU board.

Various PPCBug routines that handle I/O, data conversion, and string functions are available to user programs through the System Call handler.

PPCBug consists of three parts:

???A command-driven user-interactive software debugger. It is hereafter referred to as ???the debugger??? or ???PPCBug.???

???A set of command-driven diagnostics, which is hereafter referred to as ???the diagnostics.???

???A user interface which accepts commands from the system console terminal.

When using PPCBug, you will operate out of either the debugger directory or the diagnostic directory. The debugger prompt

(PPC1-Bug or PPC1-Diag) tells you the current directory.

5-1

Memory Requirements

PPCBug requires a maximum of 768KB (maybe less) of read/write memory (that is, DRAM). The debugger allocates this space from the top of memory. For example, a system containing 64MB ($04000000) of read/write memory will place the PPCBug memory page at locations $03F80000 to $03FFFFFF.

PPCBug Implementation

PPCBug is written largely in the C programming language, providing benefits of portability and maintainability. Where necessary, assembly language has been used in the form of separately compiled program modules containing only assembler code. No mixed-language modules are used.

Physically, PPCBug is contained in two socketed 32-pin PLCC Flash devices that together provide 1MB of storage. The executable code is checksummed at every power-on or reset firmware entry, and the result (which includes a precalculated checksum contained in the Flash devices), is verified against the expected checksum.

Using the Debugger

Using the Debugger

PPCBug

Debugger Commands

Using the Debugger

Although a command (PFLASH) to allow the erasing and reprogramming

!of Flash memory is available to you, keep in mind that reprogramming any

Caution portion of Flash memory will erase everything currently contained in Flash, including the PPCBug debugger.

Note Both banks A and B of Flash contain the PPCBug debugger.

PPCBug

Diagnostic Tests

The individual diagnostic test sets are listed in the following table. The diagnostics are described in the PPC1Bug Diagnostics Manual, listed in Appendix D, Related Documentation.

Notes

1.Some diagnostics depend on restart defaults that are set up only in a particular restart mode. Refer to the documentation on a particular diagnostic for the correct mode.

2.Test Sets marked with an asterisk (*) are not available on PPCBug release 3.1 and earlier.

CNFG and ENV Commands 6

Overview

You can use the factory-installed debug monitor, PPCBug, to modify certain parameters contained in the PowerPC board???s Non-Volatile RAM (NVRAM), also known as Battery Backed-up RAM (BBRAM).

???The Board Information Block in NVRAM contains various elements concerning operating parameters of the hardware. Use the PPCBug command CNFG to change those parameters.

???Use the PPCBug command ENV to change configurable PPCBug parameters in NVRAM.

The CNFG and ENV commands are both described in the PPCBug Firmware Package User???s Manual, listed in Appendix D, Related Documentation. Refer to that manual for general information about their use and capabilities.

The following paragraphs present additional information about CNFG and ENV that is specific to the PPCBug debugger, along with the parameters that can be configured with the ENV command.

6-1

CNFG and ENV Commands

CNFG ??? Configure Board Information Block

ENV ??? Set Environment

ENV ??? Set Environment

Use the ENV command to view and/or configure interactively all PPCBug operational parameters that are kept in Non-Volatile RAM (NVRAM).

Refer to the PPCBug Firmware Package User???s Manual for a description of the use of ENV. Additional information on registers in the Universe ASIC that affect these parameters is contained in your PowerPC board programmer???s reference guide.

Configuring the PPCBug Parameters

The parameters that can be configured using ENV are:

Bug or System environment [B/S] = B?

BBug is the mode where no system type of support is displayed. However, system-related items are still available. (Default)

SSystem is the standard mode of operation, and is the default mode if NVRAM should fail. System mode is defined in the PPCBug Firmware Package User???s Manual.

Field Service Menu Enable [Y/N] = N?

CNFG and ENV Commands

If you use the NIOT debugger command, these parameters need to be

!saved somewhere in the offset range $00001000 through $000016F7. The

Caution NIOT parameters do not exceed 128 bytes in size. The setting of this ENV pointer determines their location. If you have used the same space for your

own program information or commands, they will be overwritten and lost.

You can relocate the network interface configuration parameters in this space by using the ENV command to change the Network Auto Boot Configuration Parameters Offset from its default of $00001000 to the value you need to be clear of your data within NVRAM.

Memory Size Starting Address = 00000000?

The default Starting Address is $00000000.

Memory Size Ending Address = 02000000?

The default Ending Address is the calculated size of local memory. If the memory start is changed from $00000000, this value will also need to be adjusted.

DRAM Speed in NANO Seconds = 60?

The default setting for this parameter will vary depending on the speed of the DRAM memory parts installed on the board. The default is set to the slowest speed found on the available banks of DRAM memory.

ROM First Access Length (0 - 31) = 10?

This is the value programmed into the MPC105 ???ROMFAL??? field (Memory Control Configuration Register 8: bits 23-27) to indicate the number of clock cycles used in accessing the ROM. The lowest allowable ROMFAL setting is $00; the highest allowable is $1F. The value to enter depends on processor speed; refer to your

Configuring the VMEbus Interface

ENV asks the following series of questions to set up the VMEbus interface for the MVME2300/MVME2600/MVME3600 /MVME4600 series modules. To perform this configuration, you should have a working knowledge of the Universe ASIC as described in the Programmer???s Reference Guide.

VME3PCI Master Master Enable [Y/N] = Y?

PCI Slave Image 0 Control = 00000000?

The configured value is written into the LSI0_CTL register of the

Universe chip.

PCI Slave Image 0 Base Address Register = 00000000?

The configured value is written into the LSI0_BS register of the

Universe chip.

ASpecifications A

Specifications

Table A-1 lists the general specifications for MVME2603/2604 base boards. Subsequent sections detail cooling requirements and FCC compliance.

A complete functional description of the MVME2603/2604 base boards appears in Chapter 3, Functional Description. Specifications for the optional PCI mezzanines can be found in the documentation for those modules.

Table A-1. MVME2603/2604 Specifications

A-1

Cooling Requirements

The Motorola MVME2603/2604 family of single board computers is specified, designed, and tested to operate reliably with an incoming air temperature range from 0?? to 55?? C (32?? to 131?? F) with forced air cooling of the entire assembly (base board and modules) at a velocity typically achievable by using a 100 CFM axial fan. Temperature qualification is performed in a standard Motorola VME system chassis. 25-watt load boards are inserted in two card slots, one on each side, adjacent to the board under test, to simulate a high power density system configuration. An assembly of three axial fans, rated at 100 CFM per fan, is placed directly under the VME card cage. The incoming air temperature is measured between the fan assembly and the card cage, where the incoming airstream first encounters the module under test. Test software is executed as the module is subjected to ambient temperature variations. Case temperatures of critical, high power density integrated circuits are monitored to ensure component vendors??? specifications are not exceeded.

While the exact amount of airflow required for cooling depends on the ambient air temperature and the type, number, and location of boards and other heat sources, adequate cooling can usually be achieved with 10 CFM and 490 LFM flowing over the module. Less airflow is required to cool the module in environments having lower maximum ambients. Under more favorable thermal conditions, it may be possible to operate the module reliably at higher than 55?? C with increased airflow. It is important to note that there are several factors, in addition to the rated CFM of the air mover, which determine the actual volume and speed of air flowing over a module.

FCC Compliance

The MVME2603/2604 single board computer was tested in an

FCC-compliant chassis and meets the requirements for Class A equipment.

FCC compliance was achieved under the following conditions:

???Shielded cables on all external I/O ports.

???Cable shields connected to earth ground via metal shell connectors bonded to a conductive module front panel.

???Conductive chassis rails connected to earth ground. This provides the path for connecting shields to earth ground.

???Front panel screws properly tightened.

For minimum RF emissions, it is essential that the conditions above be implemented. Failure to do so could compromise the FCC compliance of the equipment containing the module.

BSerial Interconnections B

Introduction

As described in previous chapters of this manual, the MVME2603/2604 serial communications interface has four ports. Two of them are combined synchronous/asynchronous ports; the other two are asynchronous only. Both synchronous and asynchronous ports supply an EIA-232-D DCE/DTE interface via P2 and the MVME712M transition module.

Asynchronous Serial Ports

The MVME2603/2604 uses a PC87308 ISASIO chip from National Semiconductor to implement the two asynchronous serial ports (in addition to the disk drive controller, parallel I/O, and keyboard/mouse interface).

The asynchronous ports provided by the ISASIO device are routed through P2 and the associated transition module. The TTL-level signals from the ISASIO chip are buffered through TTL drivers and series resistors, then routed through EIA-232-D drivers and receivers to complete the asynchronous serial interface enroute to the MVME712M transition module.

The MVME2603/2604 hardware supports asynchronous serial baud rates of 110B/s to 38.4KB/s. For detailed programming information, refer to the PCI and ISA bus discussions in the MVME2600 Series Single Board Computer Programmer???s Reference Guide, listed in Appendix D, Related Documentation, and to the vendor documentation for the ISASIO device.

Synchronous Serial Ports

The MVME2603/2604 uses a Zilog Z85230 ESCC (Enhanced Serial Communications Controller) with a 10 MHz clock to implement the two synchronous/asynchronous serial communications ports, which are routed through P2 to the transition module. The Z85230 handles both

B-1

EIA-232-D Connections

The EIA-232-D standard defines the electrical and mechanical aspects of this serial interface. The interface employs unbalanced (single-ended) signaling and is generally used with DB-25 connectors, although other connector styles (for example, DB-9 and RJ-45) are sometimes used as well.

Table B-1 lists the standard EIA-232-D interconnections. Not all pins listed in the table are necessary in every application.

To interpret the information correctly, remember that the EIA-232-D serial interface was developed to connect a terminal to a modem. Serial data leaves the sending device on a Transmit Data (TxD) line and arrives at the receiving device on a Receive Data (RxD) line. When computing equipment is interconnected without modems, one of the units must be configured as a terminal (data terminal equipment: DTE) and the other as a modem (data circuit-terminating equipment: DCE). Since computers are normally configured to work with terminals, they are said to be configured as a modem in most cases.

The EIA-232-D interface standard specifies all parameters for serial binary data interchange between DTE and DCE devices using unbalanced lines. EIA-232-D transmitter and receiver parameters applicable to the MVME2603/2604 are listed in the following tables.

Table B-2. EIA-232-D Interface Transmitter Characteristics

The MVME2603/2604 conforms to EIA-232-D specifications. Note that although the EIA-232-D standard recommends the use of short interconnection cables not more than 50 feet (15 m) in length, longer cables are permissible provided the total load capacitance measured at the interface point and including signal terminator does not exceed 2500pF.

Table B-3. EIA-232-D Interface Receiver Characteristics

The EIA-530 interface complements the EIA-232-D interface in function. The EIA-530 standard defines the mechanical aspects of this interface, which is used for transmission of serial binary data, both synchronous and asynchronous. It is adaptable to balanced (double-ended) as well as unbalanced (single-ended) signaling and offers the possibility of higher data rates than EIA-232-D with the same DB-25 connector.

Table B-4 lists the EIA-530 interconnections that are available at MVME761 serial ports 3 and 4 (J7 and J8 on the board surface) when those ports are configured via serial interface modules as EIA-530 DCE or DTE ports.

Table B-4. MVME761 EIA-530 Interconnect Signals

In specifying parameters for serial binary data interchange between DTE and DCE devices, the EIA-530 standard assumes the use of balanced lines, except for the Remote Loopback, Local Loopback, and Test Mode lines, which are single-ended. Balanced-line data interchange is generally employed in preference to unbalanced-line data interchange where any of the following conditions prevail:

???The interconnection cable is too long for effective unbalanced operation.

???The interconnection cable is exposed to extraneous noise sources that may cause an unwanted voltage in excess of ??1V measured

differentially between the signal conductor and circuit ground at the load end of the cable, with a 50?? resistor substituted for the transmitter.

???It is necessary to minimize interference with other signals.

???Inversion of signals may be required (for example, plus polarity MARK to minus polarity MARK may be achieved by inverting the cable pair).

EIA-530 interface transmitter and receiver parameters applicable to the

MVME2603/2604 are listed in Table B-5 and Table B-6.

Table B-5. EIA-530 Interface Transmitter Characteristics

Proper Grounding

Proper Grounding

An important subject to consider is the use of ground pins. There are two pins labeled GND. Pin 7 is the signal ground and must be connected to the distant device to complete the circuit. Pin 1 is the chassis ground, but it must be used with care. The chassis is connected to the power ground through the green wire in the power cord and must be connected to be in compliance with the electrical code.

The problem is that when units are connected to different electrical outlets, there may be several volts of difference in ground potential. If pin 1 of each device is interconnected with the others via cable, several amperes of current could result. This condition may not only be dangerous for the small wires in a typical cable, but may also produce electrical noise that causes errors in data transmission. That is why Table B-1 and Table B-4 show no connection for pin 1. Normally, pin 7 (signal ground) should only be connected to the chassis ground at one point; if several terminals are used with one computer, the logical place for that point is at the computer. The terminals should not have a connection between the logic ground return and the chassis.

CTroubleshooting CPU Boards:

Solving Startup Problems C

Introduction

In the event of difficulty with your CPU board, try the simple troubleshooting steps on the following pages before calling for help or sending the board back for repair. Some of the procedures will return the board to the factory debugger environment. (The board was tested under these conditions before it left the factory.) The self-tests may not run in all user-customized environments.

Table C-1. Troubleshooting MVME2603/2604 Boards

C-1

DRelated Documentation D

Motorola Computer Group Documents

The Motorola publications listed below are referenced in this manual. You can obtain paper or electronic copies of Motorola Computer Group publications by:

???Contacting your local Motorola sales office

???Visiting MCG???s World Wide Web literature site, http://www.motorola.com/computer/literature

To locate and view the most up-to-date product information in PDF or HTML format, visit http://www.motorola.com/computer/literature.

D-1

Related Documentation

Manufacturers??? Documents

Related Specifications

Related Specifications

Index

IN-1

Index

Index