PENT/ATCA???717
Reference Guide
P/N 6806800A15A
April 2006
PENT/ATCA???717
Reference Guide
P/N 6806800A15A
April 2006
Copyright
ECopyright 2006 Motorola GmbH
All rights reserved.
Motorola and the stylized M logo are trademarks of Motorola,Inc., registered in the U.S. Patent and Trademark Office.
All other product or service names mentioned in this document are the property of their respective owners.
Notice
While reasonable efforts have been made to assure the accuracy of this document, Motorola GmbH assumes no liability resulting from any ommissions in this document, or from the use of the information obtained herein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
Electronic versions of this material may be read online, downloaded for personal use, or referenced in another document as a URL to the Motorola Embedded Communications Computing Web site. The text itself may not be published commercially in print or electronic form, edited, translated, or otherwise altered without the permission of Motorola GmbH.
It is possible that this publication may contain reference to or information about Motorola products (machines and programs), programming, or services that are not available in your country. Such references or information must not be construed to mean that Motorola intends to announce such Motorola products, programming, or services in your country.
2 | PENT/ATCA???717 |
Contents
PENT/ATCA???717 | 3 |
6 | PENT/ATCA???717 |
Tables
Introduction
Tablei1aaaaaaaOrganization of this Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Tablei2aaaaaaaOrdering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Tablei3aaaaaaaAccessories Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Installation
Tablei4aaaaaaaEnvironmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Tablei5aaaaaaaPower Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Tablei6aaaaaaaSwitch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Controls, Indicators, and Connectors
Tablei7aaaaaaaFace Plate LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
BIOS
Tablei8aaaaaaaKey Codes for Terminal Emulation Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Tablei9aaaaaaaStandard BIOS Post Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Devices??? Features and Data Paths
Tablei10aaaaaaReset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Tablei11aaaaaaOn???board Sensors Accessible via IPMI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Tablei12aaaaaaEthernet Switching Unit ???Ethernet Port Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Tablei13aaaaaaEthernet Switching Unit ??? Port Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Maps and Registers
Tablei14aaaaaaMemory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Tablei15aaaaaaI/O Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Tablei16aaaaaaHardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Tablei17aaaaaaPCI Device Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Tablei18aaaaaaRegisters Accessible from CPU via LPC Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Tablei19aaaaaaIndex Addresses of Registers Accessible from CPU via LPC Bus . . . . . . . . . . . . . . . . . . . . . . 137 Tablei20aaaaaaIPMI Block Transfer Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Tablei21aaaaaaEthernet Switch Management Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Tablei22aaaaaaCommand and Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Tablei23aaaaaaReset Source Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Tablei24aaaaaaReset Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Tablei25aaaaaaMiscellaneous Switch Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Tablei26aaaaaaLED Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Tablei27aaaaaaPMC Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Tablei28aaaaaaClock Synchronisation Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Tablei29aaaaaaDPLL Input Select and Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Tablei30aaaaaaReference Clock Source Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Tablei31aaaaaaExamples of Division Factors Between Recovered and Reference Clock . . . . . . . . . . . . . . . 146 Tablei32aaaaaaLower Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
8 | PENT/ATCA???717 |
Tablei33aaaaaaUpper Divider Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Tablei34aaaaaaReference Clock Pulse Width Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Tablei35aaaaaaVersion Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Tablei36aaaaaaAccess Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
PENT/ATCA???717 | 9 |
Figures
Installation
Figurei1aaaaaaaLocation of Critical Blade Temperature Spots (Blade Top Side) . . . . . . . . . . . . . . . . . . . . . . . . 39 Figurei2aaaaaaaLocation of Critical Blade Temperature Spots (Blade Bottom Side) . . . . . . . . . . . . . . . . . . . . . 40 Figurei3aaaaaaaLocation of On???board Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figurei4aaaaaaaLocation of PMC Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Figurei5aaaaaaaLocation of On???Board Hard Disk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Figurei6aaaaaaaLocation of CompactFlash Disk Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Controls, Indicators, and Connectors
Figurei7aaaaaaaFace Plate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Figurei8aaaaaaaLocation of Face Plate LEDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Figurei9aaaaaaaLocation of Reset Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Figurei10aaaaaaLocation of USB Connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figurei11aaaaaaFace Plate USB Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figurei12aaaaaaLocation of PMC Connectors Pn1 to Pn4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figurei13aaaaaaPMC Sites 1 and 4 ??? Pn4 Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figurei14aaaaaaPMC Sites 2 and 3 ??? Pn4 Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Figurei15aaaaaaLocation of Parallel ATA Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Figurei16aaaaaaParallel ATA Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figurei17aaaaaaLocation of Serial ATA Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figurei18aaaaaaLocation of CMC Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figurei19aaaaaaP10 Backplane Connector Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figurei20aaaaaaP20 Backplane Connector Pinout ??? Rows A to D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figurei21aaaaaaP20 Backplane Connector Pinout ??? Rows E to H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figurei22aaaaaaP22 Backplane Connector Pinout ??? Rows A to D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Figurei23aaaaaaP22 Backplane Connector Pinout ??? Rows E to H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figurei24aaaaaaP23 Backplane Connector Pinout ??? Rows A to D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figurei25aaaaaaP23 Backplane Connector Pinout ??? Rows E to H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Figurei26aaaaaaP30 Backplane Connector Pinout ??? Rows A to D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figurei27aaaaaaP30 Backplane Connector Pinout ??? Rows E to H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Figurei28aaaaaaP31 Backplane Connector Pinout ??? Rows A to D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figurei29aaaaaaP31 Backplane Connector Pinout ??? Rows E to H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figurei30aaaaaaP32 Backplane Connector Pinout ??? Rows A to D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Figurei31aaaaaaP32 Backplane Connector Pinout ??? Rows E to H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
BIOS
Figurei32aaaaaaMain Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figurei33aaaaaaBoot Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Devices??? Features and Data Paths
Figurei34aaaaaaBase Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figurei35aaaaaaBoot Flash LPC Device ID Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Figurei36aaaaaaIPMI Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figurei37aaaaaaIPMI Temperature Sensors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
10 | PENT/ATCA???717 |
Figurei38aaaaaaClock Synchronization Building Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Figurei39aaaaaaBlade Power Supply Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figurei40aaaaaaVLAN Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Maps and Registers
Figurei41aaaaaaPCI Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Battery Exchange
Figurei42aaaaaaLocation of On???board Battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
PENT/ATCA???717 | 11 |
Using This Guide
This Reference Guide is intended for users qualified in electronics or electrical engineering. Users must have a working understanding of Peripheral Component Interconnect (PCI), AdvancedTCAR, and telecommunications.
Conventions
Notation | Description |
57 | All numbers are decimal numbers except when used with |
| the notations described below. |
0000000016 | Typical notation for hexadecimal numbers (digits 0 through |
or 0x00000000 | F), e.g. used for addresses and offsets |
00002 | Same for binary numbers (digits are 0 and 1) |
or 0b0000 |
|
x | Generic use of a letter |
n | Generic use of numbers |
0.75 | Decimal number |
Bold | Used to emphasize a word |
Courier | Used for on???screen output |
Courier+Bold | Used to characterize user input |
Italics | For references, table, and figure descriptions |
<text> | Notation for variables and keys |
[text] | Notation for buttons and optional parameters |
... | Repeated item (example: A1, A2, A3, ..., A12) |
| No danger encountered. Pay attention to important |
| information |
Possibly dangerous situation: slight injuries to people or damage to objects possible
12 | PENT/ATCA???717 |
Notation | Description |
| Dangerous situation: injuries to people or severe damage to |
| objects possible |
Abbreviations
Abbreviationa | Descriptiona |
|
|
A | A |
AC | Alternating Current |
ANSI | American National Standards Institute |
API | Application Programming Interface |
APIC | Advanced Programmable Interrupt |
| Controller |
ATA | Advanced Technology Attachment |
ATCA | Advanced Telecommunications Computing |
| Architecture |
B | B |
BIOS | Basic Input/Output System |
BMC | Base Board Management Controller |
C | C |
CMC | Common Mezzanine Card |
CMOS | Complementary Metal Oxide Semiconductor |
CPU | Central Processing Unit |
D | D |
DDR | Double Data Rate |
DMA | Direct Memory Access |
DPLL | Digital Phase Locked Loop |
DRAM | Dynamic Random Access Memory |
E | E |
ECC | Error???Correction Code |
EMC | Electromagnetic Compatibility |
EN | European Norm |
ESCD | Extended System Configuration Data |
ESD | Electrostatic Sensitive Device |
F | F |
FAE | Field Application Engineers |
PENT/ATCA???717 | 13 |
Abbreviationa | Descriptiona |
|
|
FCC | Federal Communications Commission |
FIFO | First In First Out |
FPGA | Field???Programmable Gate Array |
FRU | Field Replacable Unit |
G | G |
GND | Ground |
I | I |
IDE | Integrated Device Electronics |
IEC | International Electric Code |
IPMB | Intelligent Platform Management Bus |
IPMC | Intelligent Platform Management Controller |
IPMI | Intelligent Platform Management Interface |
ISA | Industry Standard Architecture |
ISO | International Organization for |
| Standardization |
L | L |
LCCB | Line Card Clock Building Block |
LED | Light Emitting Diode |
LFM | Linear Feet per Minute |
LPC | Low Pin Count |
M | M |
MAC | Media Access Control |
N | N |
NEBS | Network Equipment Building System |
NVRAM | Nonvolatile Random Access Memory |
O | O |
OEM | Original Equipment Manufacturer |
OOS | Out???Of???Service |
P | P |
PCB | Printed Circuit Board |
PCI | Peripheral Component Interconnect |
PEM | Power Entry Module |
PICMG | PCI Industrial Computer Manufacturers |
| Group |
PMC | PCI Mezzanine Card |
POST | Power???On Self???Test |
PROM | Programmable Read???Only Memory |
14 | PENT/ATCA???717 |
Abbreviationa | Descriptiona |
|
|
R | R |
RAM | Random Access Memory |
ROM | Read???Only Memory |
RTC | Real Time Clock |
RTM | Rear Transition Module |
S | S |
S.M.A.R.T. | Software Maintenance and Reference Tool |
SATA | Serial ATA |
SCSI | Small Computer System Interface |
SDR | Sensor Data Record |
SDRAM | Synchronous Dynamic Random Access |
| Memory |
SELV | Safety Extra Low Voltages |
SMI | Serial Management Interface |
SPD | Serial Presence Detect |
SPI | Serial Peripheral Interface |
SRAM | Static Random Access Memory |
SROM | Serial Read???Only Memory |
U | U |
UL | Underwriters Laboratory Inc. |
USB | Universal Serial Bus |
V | V |
VGA | Video Graphics Array |
VLAN | Virtual Local Area Network |
Revision History
Order No.a | Rev. | Date | Description |
|
|
|
|
222282 | AA | June 2004 | Preliminary Reference Guide |
222282 | AB | January 2005 | Final release version |
222282 | AC | February 2005 | Corrected naming of Ethernet |
|
|
| controllers Intel 82546EB/GB and |
|
|
| 82540EM |
225444 | AA | March 2005 | Corrected figure showing the switch |
|
|
| locations; corrected description of |
|
|
| SW4???1 default setting; enhanced |
description of redundant BIOS feature
PENT/ATCA???717 | 15 |
Order No.a | Rev. | Date | Description |
|
|
|
|
226132 | AA | May 2005 | Changed logo, copyright, ... from |
|
|
| Force Computers to |
Motorola;generalized safety notes regarding maximum combined power dissipation of installed PMC modules; in power requirements: added exceptions applicable to US and Canada; in standard compliances: removed IEC60068 (officially withdrawn) and UL94V???0/1 (already covered by 60950 and NEBS) standard; added section "Restoring BIOS Default Settings"; added "Restore BIOS Default Settings" procedure; added info on redundant FPGA feature (section Devices Features and Datapaths???>FPGA); in switch setting description and Flashes section: renamed boot flash to default flash and user flash to backup flash; extended description of redundant flash feature; in standard compliances section: added note on NEBS compliance and grounding; adapted figures showing the blade face plate to new Motorola face plate; added note to section "Updating BIOS"; updated list of IPMI sensors in section: Intelligent Platform Management Controller
in section "Switch Settings" extended description of "Clear CMOS RAM" and "Serial COM port swapping" switch ; extended section BIOS???>Serial Console Redirect???>Default Configuration; added section "About this Manual"
16 | PENT/ATCA???717 |
Order No.a | Rev. | Date | Description |
|
|
|
|
6806800A15A | April 2006 | Created separate manual for blade |
|
| used in AXP systems; Changed |
parallel ATA connector pinout; modified description of on???board switches SW4???1, SW4???2 and SW4???4 (default settings were changed); updated description of Ethernet switch configuration (new routing); updated PMC Pn4 pinout description; extended description of face plate LEDs; updated description of P23 backplane connector pinout; added section: BIOS???>Crisis Recovery Mode; updated on???board switch description: crisis recovery switch no more reserved;changed location of two temperature sensors and adapted list of IPMI sensors; removed references to full mesh routing: no longer an available option; in blade installation: removed warning regarding plastic handles (new handles are used now); updated ordering information
PENT/ATCA???717 | 17 |
Other Sources of Information
For further information refer to the following documents.a
Note:aCheck the Motorola literature catalog for errata sheets that may be applicable to the blade.a
Company or | www. | Document |
Organisation |
|
|
|
|
|
Motorola | motorola.com/co | ACC/ARTM???717 Installation Guide |
| mputing |
|
|
| ACC/CABLE/RJ45/DSUB Installation Information |
aa | aa | ACC/ATCA???715/HDD Installation Guide |
|
| ACC/ATCA???715/HDD???SATA Installation Guide |
aa | aa | ACC/ATCA*CMC*MODULE Installation Guide. |
aa | aa | PENT/ATCA???715/717/7105/7107: Control via IPMI |
|
| Programmer???s Guide Guide |
|
| PENT/ATCA???715/717/7105/7107 BIOS Information |
|
| Sheeta |
Intel | intel.com | 6300ESB I/O Controller Datasheet |
aa | aa | 82540EM Gigabit Ethernet Controller Documentation |
aa | aa | 82546EB/GB Gigabit Ethernet Controller Documentation |
|
| 82802AC Firmware Hub (FWH) Datasheet |
aa | aa | 82870P2 PCI/PCI???X 64???bit Hub 2 (P64H2) Datasheet |
aa | aa | E7501 Memory Controller Datasheet |
|
| IPMI V1.5 Specifications |
|
| Pentium M Processor Technical Documents |
Marvell | marvell.com | Prestera DX160 16???Port Gigabit Ethernet Packet |
|
| Processor Documentationa |
PCI???SIG | pcisig.com | PCI Local Bus Specification Revision 2.2 |
|
| PCI???X Addendum to the PCI Local Bus Specification 1.0 |
18 | PENT/ATCA???717 |
Company or | www. | Document |
Organisation |
|
|
|
|
|
PICMG | picmg.org | PICMG 3.0 Revision 1.0 Advanced TCA Base |
|
| Specification |
|
| PICMG 3.1 Revision 1.0 Specification |
|
| Ethernet/Fiber Channel for AdvancedTCA Systems |
SMSC | smsc.com | LPC47S422 Enhanced Super I/O Controller Datasheets |
|
| and Application Notes |
PENT/ATCA???717 | 19 |
Safety Notes
This section provides safety precautions to follow when installing, operating, and maintaining the product.
We intend to provide all necessary information to install and handle the product in this manual. However, as the product is complex and its usage manifold, we do not guarantee that the given information is complete. If you need additional information, ask your Motorola representative.
The product has been designed to meet the standard industrial safety requirements. It must not be used except in its specific area of office telecommunication industry and industrial control.
Only personnel trained by Motorola or persons qualified in electronics or electrical engineering are authorized to install, remove or maintain the product. The information given in this manual is meant to complete the knowledge of a specialist and must not be taken as replacement for qualified personnel.
EMC
The blade has been tested in a standard Motorola system and found to comply with the limits for a Class A digital device in this system, pursuant to part 15 of the FCC Rules, EN 55022 Class A respectively. These limits are designed to provide reasonable protection against harmful interference when the system is operated in a commercial environment.
The blade generates and uses radio frequency energy and, if not installed properly and used in accordance with this guide, may cause harmful interference to radio communications. Operating the system in a residential area is likely to cause harmful interference, in which case the user will be required to correct the interference at his own expense.
Installation
Damage of Circuits
Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life.
Before touching the blade or electronic components, make sure that you are working in an ESD???safe environment.
Data loss
Removing the blade with the blue LED still blinking causes data loss.
Wait until the blue LED is permanently illuminated, before removing the blade.
20 | PENT/ATCA???717 |
Damage of Blade and Additional Devices and Modules
Incorrect installation of additional devices or modules may damage the blade or the additional devices or modules.
Before installing or removing an additional device or module, read the respective documentation
Operation
Blade damage Blade surface
High humidity and condensation on the blade surface causes short circuits.
Do not operate the blade outside the specified environmental limits. Make sure the blade is completely dry and there is no moisture on any surface before applying power. Do not operate the blade below 0??C.
Blade Overheating and Blade Damage
Operating the blade without forced air cooling may lead to blade overheating and thus blade damage.
When operating the blade, make sure that forced air cooling is available in the shelf.
When operating the blade in areas of electromagnetic radiation ensure that the blade is bolted on the system and the system is shielded by enclosure.
Injuries or short circuits Blade or power supply
In case the ORing diodes of the blade fail, the blade may trigger a short circuit between input line A and input line B so that line A remains powered even if it is disconnected from the power supply circuit (and vice versa).
To avoid damage or injuries, always check that there is no more voltage on the line that has been disconnected before continuing your work.
Switch Settings
Blade Malfunction
Switches marked as ???reserved??? might carry production???related functions and can cause the blade to malfunction if their setting is changed.
Therefore, do not change settings of switches marked as ???reserved???. The setting of switches which are not marked as ???reserved??? has to be checked and changed before blade installation.
Blade Damage
Setting/resetting the switches during operation can cause blade damage. Therefore, check and change switch settings before you install the blade.
PENT/ATCA???717 | 21 |
Environment
Always dispose of used blades according to your country???s legislation, if possible in an environmentally acceptable way.
PMC Modules
Limited Power on PMC Modules and RTMs
The blade does not provide an extra fuse for PMC modules and RTMs.
PMC modules and RTMs used together with the blade have to be qualified according to the following standards: IEC 60950???1, EN 60950???1, UL 60950???1, CAN/CSA C22???2 No 60950???1
Excession of blade???s power consumption
Exceeding the maximum combined power dissipation of installed PMC modules may damage the blade.a
Make sure that the combined power dissipation of installed PMC modules on the 3.3V and 5V rail does not exceed 60W.
PMC Module Malfunctioning
Processor PMC modules (as defined in ANSI/VITA 32???2003) can be operated in two different modes: monarch and non???monarch mode.a
Make sure to operate any installed processor PMC modules (as defined in ANSI/VITA 32???2003) only in non???monarch mode.a
Damage of Installed Hard Disk
If PPMC/270 or PPMC/280 modules are installed into PMC slot 1 or 2, the heat radiated by the heat sink of theses PMC modules heats up an installed hard disk that may be installed at the same time.a
If PPMC/270 or PPMC/280 modules are installed into PMC slot 1 or 2, make sure not to have a hard disk installed at the same time.a
Battery
Blade/System damage
Incorrect exchange of lithium batteries can result in a hazardous explosion.a Therefore, exchange the battery as described in this manual.
Data loss
If the battery does not provide enough power anymore, the RTC is initialized and the data in the NVRAM is lost.
Therefore, exchange the battery before seven years of actual battery use have elapsed.
22 | PENT/ATCA???717 |
Data loss
Exchanging the battery always results in data loss of the devices which use the battery as power backup.a
Therefore, back up affected data before exchanging the battery.
Data loss
If installing another battery type than is mounted at blade delivery may cause data loss since other battery types may be specified for other environments or may have a shorter lifetime.
Therefore, only use the same type of lithium battery as is already installed.
PENT/ATCA???717 | 23 |
Sicherheitshinweise
Dieser Abschnitt enth??lt Sicherheitshinweise, die bei Installation, Betrieb und Wartung des Produkts zu beachten sind.
Wir sind darauf bedacht, alle notwendigen Informationen, die f??r die Installation und den Betrieb erforderlich sind, in diesem Handbuch bereit zu stellen. Da es sich jedoch um ein komplexes Produkt mit vielf??ltigen Einsatzm??glichkeiten handelt, k??nnen wir die Vollst??ndigkeit der im Handbuch enthaltenen Informationen nicht garantieren. Falls Sie weitere Informationen ben??tigen sollten, wenden Sie sich bitte an die f??r Sie zust??ndige Gesch??ftsstelle von Motorola.
Das Produkt erf??llt die f??r die Industrie geforderten Sicherheitsvorschriften und darf ausschlie??lich f??r Anwendungen in der Telekommunikationsindustrie und im Zusammenhang mit Industriesteuerungen verwendet werden.
Installation, Wartung und Betrieb d??rfen nur von durch Motorola ausgebildetem oder im Bereich Elektronik oder Elektrotechnik qualifiziertem Personal durchgef??hrt werden. Die in diesem Handbuch enthaltenen Informationen dienen ausschlie??lich dazu, das Wissen von Fachpersonal zu erg??nzen, k??nnen es aber in keinem Fall ersetzen.
EMV
Das Blade wurde in einem Motorola Standardsystem getestet. Es erf??llt die f??r digitale Ger??te der Klasse A g??ltigen Grenzwerte in einem solchen System gem???? den FCC???Richtlinien Abschnitt 15 bzw. EN 55022 Klasse A. Diese Grenzwerte sollen einen angemessenen Schutz vor St??rstrahlung beim Betrieb des Blades in Gewerbe??? sowie Industriegebieten gew??hrleisten.
Das Blade arbeitet im Hochfrequenzbereich und erzeugt St??rstrahlung. Bei unsachgem????em Einbau und anderem als in diesem Handbuch beschriebenen Betrieb k??nnen St??rungen im Hochfrequenzbereich auftreten.
Warnung! Dies ist eine Einrichtung der Klasse A. Diese Einrichtung kann im Wohnbereich Funkst??rungen verursachen. In diesem Fall kann vom Betreiber verlangt werden, angemessene Ma??nahmen durchzuf??hren.
Installation
Besch??digung von Schaltkreisen
Elektrostatische Entladung und unsachgem????er Ein??? und Ausbau von Blades kann Schaltkreise besch??digen oder ihre Lebensdauer verk??rzen.
Bevor Sie Blades oder elektronische Komponenten ber??hren, vergewissern Sie sich, da?? Sie in einem ESD???gesch??tzten Bereich arbeiten.
24 | PENT/ATCA???717 |
Datenverlust
Wenn Sie das Blade aus dem Shelf herausziehen, und die blaue LED blinkt noch, gehen Daten verloren.
Warten Sie bis die blaue LED durchgehend leuchtet, bevor Sie das Blade herausziehen.
Besch??digung des Blades und von Zusatzmodulen
Fehlerhafte Installation von Zusatzmodulen, kann zur Besch??digung des Blades und der Zusatzmodule f??hren.
Lesen Sie daher vor der Installation von Zusatzmodulen die zugeh??rige Dokumentation.a
Betrieb
Besch??digung des Blades
Hohe Luftfeuchtigkeit und Kondensat auf der Oberfl??che des Blades k??nnen zu Kurzschl??ssen f??hren.
Betreiben Sie das Blade nur innerhalb der angegebenen Grenzwerte f??r die relative Luftfeuchtigkeit und Temperatur. Stellen Sie vor dem Einschalten des Stroms sicher, dass sich auf dem Blade kein Kondensat befindet und betreiben Sie das Blade nicht unter 0??C.
??berhitzung und Besch??digung des Blades
Betreiben Sie das Blade ohne Zwangsbel??ftung, kann das Blade ??berhitzt und schlie??lich besch??digt werden.
Bevor Sie das Blade betreiben, m??ssen Sie sicher stellen, dass das Shelf ??ber eine Zwangsk??hlung verf??gt.
Wenn Sie das Blade in Gebieten mit starker elektromagnetischer Strahlung betreiben, stellen Sie sicher, dass das Blade mit dem System verschraubt ist und das System durch ein Geh??use abgeschirmt wird.
Verletzungen oder Kurzschl??sse Blade oder Stromversorgung
Falls die ORing Dioden des Blades durchbrennen, kann das Blade einen Kurzschluss zwischen den Eingangsleitungen A und B verursachen. In diesem Fall ist Leitung A immer noch unter Spannung, auch wenn sie vom Versorgungskreislauf getrennt ist (und umgekehrt).
Pr??fen Sie deshalb immer, ob die Leitung spannungsfrei ist, bevor Sie Ihre Arbeit fortsetzen, um Sch??den oder Verletzungen zu vermeiden.
PENT/ATCA???717 | 25 |
Schaltereinstellungen
Fehlfunktion des Blades
Schalter, die mit ???Reserved??? gekennzeichnet sind, k??nnen mit produktionsrelevanten Funktionen belegt sein. Das ??ndern dieser Schalter kann im normalen Betrieb St??rungen ausl??sen.a
Verstellen Sie nur solche Schalter, die nicht mit ???Reserved??? gekennzeichnet sind. Pr??fen und ??ndern Sie die Einstellungen der nicht mit ???Reserved??? gekennzeichneten Schalter, bevor Sie das Blade installieren.
Besch??digung der Blade
Das Verstellen von Schaltern w??hrend des laufenden Betriebes kann zur Besch??digung des Blades f??hren.
Pr??fen und ??ndern Sie die Schaltereinstellungen, bevor Sie das Blade installieren.
Umweltschutz
Entsorgen Sie alte Batterien und/oder Blades stets gem???? der in Ihrem Land g??ltigen Gesetzgebung, wenn m??glich immer umweltfreundlich.
PMC???Module
Begrenzte Leistung auf dem PMC???Modul und RTM
Das Blade verfuegt ueber keine Sicherung fuer PMC???Module und RTMs. PMC???Module und RTMs, die zusammen mit dem Blade eingesetzt werden, muessen gemaess den folgenden Standards qualifiziert sein: IEC 60950???1, EN 60950???1, UL 60950???1, CAN/CSA C22???2 No 60950???1
Ueberschreitung der zulaessigen Leistungsaufnahme des Blades
Wird die maximal zulaessige Leistungsaufnahme fuer alle installierten PMC???Module zusammen ueberschritten, so kann dies zu einer Beschaedigung des Blades fuehren.a Stellen Sie sicher, dass die Leistungsaufnahme aller installierten PMC???Module zusammen auf der 3.3V??? und 5V???Schiene insgesamt 60W nicht ueberschreitet.
Fehlfunktion von PMC???Modulen
Prozessor???PMC???Module (ANSI/VITA 32???2003) koennen generell in zwei Modi betrieben werden: Monarch??? und Nonmonarch???Modus.a
Betreiben Sie auf dem Blade installierte PMC???Module (ANSI/VITA 32???2003) nur im Nonmonarch???Modus.
26 | PENT/ATCA???717 |
Beschaedigung einer installierten Festplatte
Falls PPMC/270 oder PPMC/280???PMC???Module in PMC???Slot 1 oder 2 installiert sind, erhitzen die Kuehlkoerper dieser PMC???Module eine moeglicherweise gleichzeitig installierte Festplatte.a
Falls PPMC/270??? oder PPMC/280???PMC???Module in den PMC???Slots 1 oder 2 installiert sind, stellen Sie sicher, dass keine Festplatte zur gleichen Zeit auf dem Blade installiert ist.
Batterie
Beschaedigung des Blades/des Systems
Fehlerhafter Austausch von Lithium???Batterien kann zu gef??hrlichen Explosionen f??hren.a
Fuehren Sie den Austausch so durch, wie er in diesem Manual beschrieben ist.
Datenverlust
Wenn die Batterie nur noch ungen??gend geladen ist, wird der RTC zur??ckgesetzt und Daten im NVRAM gehen verloren.a
Tauschen Sie daher die Batterie innerhalb einer Zeit von sp??testens sieben Jahren aus.a
Datenverlust
Der Austausch der Batterie f??hrt unweigerlich zu Datenverlust bei Bauteilen, die die Batterie als Backup verwenden.a
Sichern Sie daher alle Daten, die bei Austausch der Batterie verloren gehen.a
Datenverlust
Wenn Sie einen anderen Batterietyp installieren als der, der bei Auslieferung des Blades installiert war, kann Datenverlust die Folge sein, da die neu installierte Batterie f??r andere Umgebungsbedingungen oder eine andere Lebenszeit ausgelegt sein k??nnte.
Verwenden Sie daher den gleichen Batterietyp, der bei Auslieferung des Blades installiert war.
PENT/ATCA???717 | 27 |
1
Introduction
28 | PENT/ATCA???717 |
About this Manual | Introduction |
|
|
About this Manual
This Reference Guide provides the information you need to install, access and operate the blade.a
Organization of this Manual
The Reference Guide is organized as follows.a
Table 1: Organization of this Manual
Chapter | Description |
Using this Guide | Lists all conventions and abbreviations used in this manual and |
| outlines the revision history |
Other Sources of Information | Lists related documentation and specifications |
Safety Notes | Provides safety relevant information when handling the product |
Sicherheitshinweise | German translation of the Safety Notes section |
Introduction | Provides a basic overview of the features of the product and this |
| manual |
Installation | Outlines the installation requirements, hardware accessories, |
| switch settings, installation and removal procedures |
Controls, Indicators and | Describes the LEDs, keys, and connectors of the product |
Connectors |
|
BIOS | Describes the basic features of the blade???s BIOS. Also explains how |
| to restore the BIOS default settings and how to connect to the blade |
| using the serial console redirect feature.a |
Devices??? Features and Data Paths | Provides detailled information on the devices, such as controllers, |
| CPU etc., used on the blade and how they are interconnected |
Maps and Registers | Provides information that is relevant for programmers, such as |
| register reference and memory mapsa |
Battery Exchange | Describes how to exchange the blade???s on???board battery |
Feedback
Motorola welcomes and appreciates your comments on its documentation. We want to know what you think about our manuals and how we can make them better. Mail comments to:
SMotorola GmbH
ECC Embedded Communication Computing Lilienthalstr. 15
85579 Neubiberg???Munich/Germany
PENT/ATCA???717 | 29 |
Introduction | About this Manual |
|
|
Sreader???comments@mcg.mot.com
In all your correspondence, please list your name, position, and company. Be sure to include the title, part number, and revision of the manual and tell how you used it.
30 | PENT/ATCA???717 |
Features | Introduction |
|
|
Features
The PENT/ATCA???717 is an AdvancedTCA compliant single blade computer offering high processing performance. Four on???board PMC sites, GBit Ethernet connection to the AdvancedTCA Base and Fabric interface as well as standard I/O interfaces make it ideal for telecommunication and datacom applications. An on???board 16???port Ethernet switch allows switching between PMC sites, Base and Fabric interface and the base board.aaa
Important features are:
SPentium M processor with up to 1.8 GHz speed
SUp to four GByte main memory DDR2 SDRAM with ECC protection
SDesigned for PICMG 3.0 and 3.1 compliant systems
S16???port Ethernet switch with host interface for configuration and management
SRedundant AdvancedTCA Base interface
SUp to eight AdvancedTCA Fabric Channel interfaces
SFour 64???bit/100MHz PCI???X compliant PMC slots
STwo USB 2.0 interfaces at face plate
SOptional on???board CompactFlash and 2.5 inch hard diska
SSupport for Windows 2000/2003 and Carrier Grade Linux Ed. 3.1
SIntelligent Platform Management Controller (IPMC) compliant to IPMI V.1.5 with redundant IPMB support
SSupport for four PMC Modules with Telecom clocking synchronization
SDifferent accessory kits, for example:
???Rear Transition Modules (RTMs)
???CMC debug module
???Hard disk accessory kit
???Cable accessory kits
PENT/ATCA???717 | 31 |
Introduction | Standard Compliances |
|
|
Standard Compliances
Standard | Description |
UL 60950???1 | Legal safety requirements |
EN 60950???1 |
|
IEC 60950???1 |
|
CAN/CSA C22.2 No 60950???1 |
|
EN 55022
EN 55024
EN 300386
FCC Part 15a
ANSI/IPC???A610 Rev.C Class 2 ANSI/IPC???7711 ANSI/IPC???7721 ANSI???J???001...003
EMC requirements on system level (predefined Motorola system)
Manufacturing Requirements
ISO 8601 | Y2K compliance |
NEBS Standard GR???63???CORE, | NEBS level three |
NEBS Standard GR???1089 CORE | Product is designed to support NEBS level three. |
| The compliance tests must be done with the |
| customer target system. |
PICMG 3.0 R1.0 | Defines mechanics, blade dimensions, power |
| distribution, power and data connectors, and |
| system management |
Note:aThis blade contains an embedded power source rated >150W. To achieve NEBS compliance on system level, Shelf Ground (chassis ground) and Logic Ground (logic signal return) have to be connected. The connection may be implemented inside the shelf, e.g. at the backplane, or the shelf has to provide a possibility to lead Logic Ground out of the shelf for external connection to Central Office Ground. For further information refer to Telcordia GR???1089???CORE, section 9.8.2, requirement R9???14.a
32 | PENT/ATCA???717 |
Ordering Information | Introduction |
|
|
Ordering Information
When ordering the board variants, upgrades and accessories, use the order numbers given below.
Product Nomenclature
In the following you find the key for the product name extensions.aa
PENT/ATCA???717/xx???yyyy | aa |
xx | Main memory in GByte |
yyyy | CPU frequency in MHz |
Order Numbers
The table below is an excerpt from the blade???s ordering information. Ask your local Motorola representative for the current ordering information.aaaa
Note:aThis manual describes the blades listed below (PCA revision 1.3) and is delivered with these blades. For blades with other PCA revisions refer to the manuals that are delivered with those blades.a
Table 2: Ordering Information
Order Number | PENT/ATCA???717/ | Description |
123065 | 2G???1800 | Two GByte main memory, 1800 MHz CPU |
|
| frequency; (PCA revision 1.3)aa |
123066 | 4G???1800 | Four GByte main memory, 1800 MHz CPU |
|
| frequency; (PCA revision 1.3) |
The table below is an excerpt from the blade???s accessories ordering information. Ask your local Motorola representative for the current ordering information.aaaa
Table 3: Accessories Ordering Information
Order Number | Accessory | Description |
123036 | ACC/ARTM???717 | Rear transition module for |
|
| PENT/ATCA???717 bladesa |
|
| Provides access to four serial interfaces |
|
| deriving from PMCs as well as two USB |
|
| 2.0, two serial, two SATA and one |
|
| keyboard/mouse interface; supports |
|
| PPMC???280 modules installed on the |
|
| PENT/ATCA???717 |
120980 | ACC/ATCA???715/HDD | Parallel ATA hard disk |
PENT/ATCA???717 | 33 |
Introduction | Ordering Information |
|
|
Order Number | Accessory | Description |
122240 | ACC/ATCA???715/HDD???SATA | Serial ATA hard disk |
122241 | ACC/ATCA???CMC???MODULE | CMC module for debugging |
121793 | ACC/CABLE/RJ45/DSUB | Adapter cable: RJ???45 <???> DSUB |
122242 | ACC/CABLE/PMC/RJ45 | Splitter cable for accessing serial |
|
| interfaces of installed PMC*8260/DS1 |
|
| or PPMC*280 modules |
121792 | ACC/CABLE/USB | Adapter cable: mini USB B???male <???> |
|
| USB A female |
34 | PENT/ATCA???717 |
2
Installation
PENT/ATCA???717 | 35 |
Installation | Action Plan |
|
|
Action Plan
To install the blade, the following steps are necessary and described in detail in the sections of this chapter. The installation takes about five minutes.
Start installation
environmental requirements are met
Set on???board switches, if applicable
Install on???board hardware accessories, if applicable
Install Rear Transition
Module, if applicable
Install blade
Install cable accessories, if applicable
Installation finished
36 | PENT/ATCA???717 |
Requirements | Installation |
|
|
Requirements
In order to meet the environmental requirements, the blade has to be tested in the system in which it is to be installed.a
Before you power up the blade, calculate the power needed according to your combination of blade upgrades and accessories.
Environmental Requirements
The environmental conditions must be tested and proven in the shelf configuration used. The conditions refer to the surrounding of the blade within the user environment.aaa
Note:a
SThe environmental requirements of the blade may be further limited down due to installed accessories, such as hard disks or PMC modules, with more restrictive environmental requirements
SOperating temperatures refer to the temperature of the air circulating around the blade and not to the actual component temperature.
SBlade damage Blade surface
High humidity and condensation on the blade surface causes short circuits.
Do not operate the blade outside the specified environmental limits. Make sure the blade is completely dry and there is no moisture on any surface before applying power. Do not operate the blade below 0??C.
SBlade Overheating and Blade Damage
Operating the blade without forced air cooling may lead to blade overheating and thus blade damage.
When operating the blade, make sure that forced air cooling is available in the shelf.
Table 4: Environmental Requirements
Requirement | Operating | Non???Operating |
Temperature | 0??C to +55??C (may be | |
| further limited by | further limited by |
| installed | installed accessories)aa |
| accessories)aaaa |
|
Temp. Change | a +/??? 0.5??C/min | a +/??? 1??C/min |
PENT/ATCA???717 | 37 |
Installation | Requirements |
|
|
Requirement | Operating | Non???Operating |
Rel. Humidity | 5% to 95% non | 5% to 95% non condensing |
| condensing at +40?? | at +40??C |
Altitude | ||
Vibration |
|
|
20 to 2000Hz | 2 g(RMS) random | 2 g(RMS) random |
Shock | 5 g/30 ms half sine | 15 g/11 ms half sine |
Free Fall | aa | 1,200 mm/all edges and |
|
| corners (packed state) |
|
| 100 mm/3 axis (unpacked) |
To guarantee proper blade operation, you have to make sure that the temperatures at the following locations are not exceeded. If not stated otherwise, the temperatures should be measured by placing a sensor exactly at the given locations.aaa
Location No. | Component | Temperature Limit |
1 | Pentium M CPU 1) | 100 ??C |
2 | Intel 82540EM Gbit Ethernet controller | 100 ??C |
3 | Intel 6300ESB Southbridge | 105 ??C |
4 | Lithium battery | 70 ??C |
5 | Intel 82546EB/GB Dual Gbit Ethernet | 90 ??C |
| controller |
|
6 | Electrolytic capacitor CE9902 | 100 ??C |
7 | Electrolytic capacitor CE9903 | 100 ??C |
8 | Ericsson DC/DC converter | 90 ??C |
9 | QM48T DC/DC converter | 115 ??Ca |
|
| (105 ??C coated blade variant) |
10 | Power MOSFET IRF 6603 | 105 ??C |
1)Temperature must be measured via on???die sensor which can be accessed via IPMI
38 | PENT/ATCA???717 |
Requirements | Installation |
|
|
Figure 1: Location of Critical Blade Temperature Spots (Blade Top Side)
PENT/ATCA???717 | 39 |
Installation | Requirements |
|
|
10
Figure 2: Location of Critical Blade Temperature Spots (Blade Bottom Side)
Power Consumption
The blade???s power requirements depend on the installed hardware accessories. If you want to install accessories on the board, the load of the respective accessory has to be added to that of the blade.In the following table you will find typical examples of power requirements with and without accessories installed. For information on the accessories??? power requirements, refer to the documentation delivered together with the respective accessory or consult your local Motorola representative for further details.aaaa
The blade must be connected to a TNV???2 or a safety???extra???low???voltage (SELV) circuit. A TNV???2 circuit is a circuit whose normal operating voltages exceed the limits for a SELV circuit under normal operating conditions, and which is not subject to overvoltages from telecommunication networks.
Table 5: Power Requirements
Characteristic | Value |
Rated Voltage | ???48VDC to ???60VDC |
Exception in the US and Canada | ???48VDC |
Operating Voltage | ???40.5VDC to ???72VDC |
Exception in the US and Canada | ???40.5VDC to ???60VDC |
40 | PENT/ATCA???717 |
Requirements | Installation |
|
|
Characteristic | Value |
Max. current | 3.6A |
Max. power consumption of blade equipped with | 75W |
4 GByte SDRAM without accessories |
|
Max. total power consumption of all four PMC | 60W |
sites |
|
Max. total power consumption of all installed | 65W |
blade accessories (PMCs + hard disk) |
|
The blade provides two independent power inputs according to the AdvancedTCA Specification. Each input has to be equipped with an additional fuse of max. 90A located either in the shelf where the blade is installed or the power entry module (PEM).
PENT/ATCA???717 | 41 |
Installation | Switch Settings |
|
|
Switch Settings
The blade provides the on???board switches SW2, SW3, SW4 and SW7. The following figure shows their location. Note that in the switch drawings the switch handle is represented by a little white square and that the shown switch settings reflect the default switch settings.aaa
Figure 3: Location of On???board Switches
42 | PENT/ATCA???717 |
Switch Settings | Installation |
|
|
SBlade Malfunction
Switches marked as ???reserved??? might carry production???related functions and can cause the blade to malfunction if their setting is changed.
Therefore, do not change settings of switches marked as ???reserved???. The setting of switches which are not marked as ???reserved??? has to be checked and changed before blade installation.
SBlade Damage
Setting/resetting the switches during operation can cause blade damage. Therefore, check and change switch settings before you install the blade.
Table 6: Switch Settings
Switch | Description |
SW2???1 | Reserved (default: OFF) |
SW2???2 | Reserved (default: OFF) |
SW2???3 | Clear CMOS RAM contentaa |
| OFF: Normal operation (default) |
| ON: Clear CMOS RAM |
| For the exact procedure of how to clear the CMOS RAM content, |
| i.e. restore the default BIOS settings, refer toasection "Restoring |
| |
SW2???4 | BIOS crisis recovery mode |
| OFF: Disabled (default) |
| ON: Enabled |
| For details refer toasection "BIOS Crisis Recovery Mode" on |
| |
SW3???1 | Reserved (default: OFF) |
SW3???2 | Reserved (default: OFF) |
SW3???3 | Reserved (default: OFF) |
SW3???4 | Serial COM interface swapping at blade start???up |
| OFF: No swapping (default) |
| As a result, COM1 and COM2 are accessible at an installed RTM, |
| COM3 and COM4 are accessible at an installed CMC module |
| ON: COM1 is swapped with COM 3, and COM 2 is swapped |
| with COM 4 |
| As a result, COM1 and COM2 are accessible at an installed CMC |
| module, and COM3 and COM4 are accessible at an installed |
| RTM |
PENT/ATCA???717 | 43 |
Installation | Switch Settings |
|
|
Switch | Description |
| Note: the routing described above is only applicable to BIOS |
| versions w 2.0.0. Earlier BIOS versions used a different routing. |
| For further information refer to |
| theaPENT/ATCA???715/717/7105/7107 BIOS Information Sheeta |
| which can be downloaded from the former Force Computers |
| S.M.A.R.T. server or the Motorola literature catalog web site.a |
| Note: The COM port swapping can also be enabled via a System |
| Boot Option IPMI command. COM port swapping is enabled if |
| either the switch or the IPMI command or both enable it. For |
| further details about the System Boot Option IPMI command, |
| refer to theaPENT/ATCA???715/717/7105/7107: Control via IPMI |
| Programmer???s Guide. |
SW4???1 | Backup boot flash boot block write protection |
| OFF: Write???enabled (default) |
| ON: Write???disableda |
| For details on the flash devices and the blade???s redundant BIOS |
| feature, refer toasection "Flash Devices" on pagea113. |
SW4???2 | Default boot flash boot block write protection |
| OFF: Write???enabled (default) |
| ON: Write???disabled |
| For details on the flash devices and the blade???s redundant BIOS |
| feature, refer toasection "Flash Devices" on pagea113. |
SW4???3 | Reserved (default: OFF) |
SW4???4 | Backup boot flash data/instruction block write protection |
| OFF: Write???enabled (default)a |
| ON: Write???disabled |
| For details on the flash devices and the blade???s redundant BIOS |
| feature, refer toasection "Flash Devices" on pagea113. |
SW7???1 | Routing of PMC slot 1 Pn4 connector pins 30 and 31 |
| OFF: Pin 30 and 31 are routed to zone 3 backplane connector and |
| are available as PMC I/O signals (default) |
| ON: Pin 30 and 31 hold clock reference signals generated by |
| clock synchronization building block |
SW7???2 | Routing of PMC slot 2 Pn4 connector pins 30 and 31 |
| OFF: Pin 30 and 31 are routed to zone 3 backplane connector and |
| are available as PMC I/O signals (default) |
| ON: Pin 30 and 31 hold clock reference signals generated by |
| clock synchronization building block |
44 | PENT/ATCA???717 |
Switch Settings | Installation |
|
|
Switch | Description |
SW7???3 | Routing of PMC slot 3 Pn4 connector pins 30 and 31 |
| OFF: Pin 30 and 31 are routed to zone 3 backplane connector and |
| are available as PMC I/O signals (default) |
| ON: Pin 30 and 31 hold clock reference signals generated by |
| clock synchronization building block |
SW7???4 | Routing of PMC slot 4 Pn4 connector pins 30 and 31 |
| OFF: Pin 30 and 31 are routed to zone 3 backplane connector and |
| are available as PMC I/O signals (default) |
| ON: Pin 30 and 31 hold clock reference signals generated by |
| clock synchronization building block |
PENT/ATCA???717 | 45 |
Installation | On???Board Hardware Accessories |
|
|
On???Board Hardware Accessories
The following hardware upgrades can be installed on the blade:
SPMC modules
SHard Disk
SCompactFlash card
SCMC module
PMC Modules
The blade provides four PMC slots supporting PCI/PCI???X based PMC modules. When operated in PCI mode, PMC modules run at 33/66Mhz, when operated in PCI???X mode they run at 66/100MHz. All four PMC slots use a signaling level of 3.3V.aaaaa
The four PMC slots are numbered from 1 to 4. Their location is shown in the following figure.a
46 | PENT/ATCA???717 |
On???Board Hardware Accessories |
|
| Installation | ||||||||||||||||
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Figure 4: Location of PMC Slots
PMC slots 1 and 2 belong to one PCI segment and PMC slots 3 and 4 belong to another PCI segment. Within the same PCI segment, it is possible to install two PMC modules of different modes (PCI/PCI???X) and speeds (33/66/100 MHz). The PMC module with the overall lower performance (combination of speed and PCI mode) determines the speed and PCI mode of the second PMC module.aaa
Example:aA PMC module supporting PCI???X/66MHz is installed into PMC slot 1 and a PMC module supporting PCI/66MHz is installed into PMC slot 2. In this case both PMC modules are operated in PCI/66 MHz mode because the PMC module with the overall less performance is the one supporting PCI/66 MHz and consequently the second PMC module is operated in this mode as well.a
Before installing PMC modules, the following general safety notes must be observed.a
PENT/ATCA???717 | 47 |
Installation | On???Board Hardware Accessories |
|
|
SLimited Power on PMC Modules and RTMs
The blade does not provide an extra fuse for PMC modules and RTMs. PMC modules and RTMs used together with the blade have to be qualified according to the following standards: IEC 60950???1, EN 60950???1, UL 60950???1, CAN/CSA C22???2 No 60950???1
SExcession of blade???s power consumption
Exceeding the maximum combined power dissipation of installed PMC modules may damage the blade.a
Make sure that the combined power dissipation of installed PMC modules on the 3.3V and 5V rail does not exceed 60W.
SPMC Module Malfunctioning
Processor PMC modules (as defined in ANSI/VITA 32???2003) can be operated in two different modes: monarch and non???monarch mode.a
Make sure to operate any installed processor PMC modules (as defined in ANSI/VITA 32???2003) only in non???monarch mode.a
SDamage of Installed Hard Disk
If PPMC/270 or PPMC/280 modules are installed into PMC slot 1 or 2, the heat radiated by the heat sink of theses PMC modules heats up an installed hard disk that may be installed at the same time.a
If PPMC/270 or PPMC/280 modules are installed into PMC slot 1 or 2, make sure not to have a hard disk installed at the same time.a
SDamage of Rear Transition Module and Blade
The ACC/ARTM???717 was designed to be used in conjunction with PPMC/270 or PPMC/280 modules modules installed on the blade at the same time.
In order to avoid damage of the blade or RTM, only use the ACC/ARTM???717 in conjunction with PPMC/270 or PPMC/280 modules.
Installation Procedure
1.Connect PMC module carefully to PMC slot
2.Make sure that 15 mm standoffs of PMC module cover mounting holes of the blade.
3.Place screws delivered with PMC module into mounting holes
4.Fasten screws
Removal Procedure
1.Remove screws
2.Disconnect PMC module carefully from slot
48 | PENT/ATCA???717 |
On???Board Hardware Accessories | Installation |
|
|
Hard Disk
The blade allows to install one 2.5" hard disk which may be connected to either an on???board parallel or serial Advanced Technology Attachment (ATA) interface connector. The hard disk can be mounted directly on the blade without the need for an additional wire.aaa
Figure 5: Location of On???Board Hard Disk
The serial ATA interface supports up to 150 MByte/s data transfer rate and the parallel ATA supports all PIO and DMA modes up to Ultra ATA100. Hard disks which are connected to the parallel ATA interface act as master.a
Two hard disk accessory kits are available for the blade. One is called ACC/ATCA???715/HDD and contains a parallel ATA hard disk drive. The second is called ACC/ATCA???715/HDD???SATA and contains a serial ATA hard disk drive.a
Installing a Hard Disk
PENT/ATCA???717 | 49 |
Installation | On???Board Hardware Accessories |
|
|
1.Position hard disk above blade so that the blade???s parallel ATA or serial ATA or SATA connector faces the hard disk???s interface connector
2.Connect hard disk with blade???s connectora
3.Turn blade to face its bottom side
4.Fasten four screws to blade???s bottom side
Removing a Hard Disk
1.Removing Hard Disk
2.Place blade on table with blade???s bottom side facing you
3.Remove four screws holding hard disk
4.Carefully remove hard disk from blades???s parallel ATA or SATA connector
5.Store hard disk and screws in a safe place in case you want to use the accessory kit components again
CompactFlash Disk
The blade provides a connector to install a CompactFlash card of type I and II.aaa
50 | PENT/ATCA???717 |
On???Board Hardware Accessories |
|
| Installation | ||||||||||
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Figure 6: Location of CompactFlash Disk Connector
The CompactFlash card is operated in True IDE mode and is connected to the secondary IDE interface where it acts as IDE master.a
CompactFlash Installation
1. Open locking bow
2. Check that disk???s connectors face the CompactFlash socket
PENT/ATCA???717 | 51 |
Installation | On???Board Hardware Accessories |
|
|
3. Plug CompactFlash into socket
4. Close locking bow over CompactFlash disk
Note:aThe locking bow must enclose the disk completely.a
Removal Procedure
1.Open locking bow
2.Take CompactFlash disk???s ends and pull CompactFlash disk carefully out of socket
3.Close locking bow again
CMC Debug Module
A CMC debug module is available as accessory kit for the blade. It is called ACC/ATCA???CMC???MODULE and provides two serial and one keyboard/mouse interface at its face plate. The CMC debug module is installed into PMC slot 4. For further details refer to theaACC/ATCA???CMC???MODULE Installation Guide.aa
52 | PENT/ATCA???717 |
Rear Transition Modules | Installation |
|
|
Rear Transition Modules
At the time of writing this manual the following Rear Transition Modules (RTMs) was available for the blade: ACC/ARTM???717aa
It provides the following interfaces:a
STwo USB 2.0
STwo RS???232
SKeyboard/Mouse
SOne serial ATA
SFour RS???232 interfaces routed from PMC modules installed on the base blade
Note:a
SRefer to the RTM documentation for the RTM installation procedure
SCheck the documentation of the system where you operate the blade and the RTM for any restrictions that may apply to the blade or the RTM
SNo hot???swap is supported for the RTMs
The RTM furthermore incorporates an Intelligent Platform Management Interface Controller (IPMC) which enables you to monitor the RTM???s temperature and voltage sensors. For further information, refer to theaACC/ARTM???715/717/7105/7107: Control via IPMI Programmer???s Guideawhich can be downloaded from the former Force Computers S.M.A.R.T. server or the Motorola literature catalog.a
PENT/ATCA???717 | 53 |
Installation | Blade Installation |
|
|
Blade Installation
The blade is fully compatible to the AdvancedTCA standard and is designed to be used in AdvancedTCA shelfs. Since the installation and removal procedures are different for powered and nonpowered shelfs, they are described in separate sections.aaaaa
Damage of Circuits
Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life.
Before touching the blade or electronic components, make sure that you are working in an ESD???safe environment.
Installation into Powered Shelves
Installation Procedure
1.Ensure that the top and bottom ejector handles are in the outward positionaa
2.Insert blade into the shelf by placing the top and bottom edges of the blade in the card guides of the shelf. Ensure that the guiding module of shelf and blade are aligned properly.a
3.Carefully slide the blade into the shelf until you feel resistance.a
If an RTM is already installed in the same slot, be careful not to bend any pins of the P30 to P32 backplane connectors.a
4.Hook the lower and the upper handle into the shelf rail recesses
5.Fully insert the blade and lock it to the shelf by pressing the two components of the lower and the upper handles together and turning the handles towards the face plate
As soon as the blade is connected to the backplane power pins, the blue LED is illuminated.a
When the blade is completely installed, the blue LED starts to blink. This indicates that the blade announces its presence to the shelf management controller.
Note:aIf an ARTM is connected to the front blade, make sure that the handles ofabotha the ARTM and the front blade are closed in order to power up the blade???s payload.
6.Wait until the blue LED is switched OFFa
The switched off blue LED indicates that the blade???s payload has been powered up and that the blade is active.a
54 | PENT/ATCA???717 |
Blade Installation | Installation |
|
|
7.Tighten the face plate screws which secure the blade to the shelfa
8.Connect cables to the face plate, if applicable
Removal Procedure
1.Remove face plate cables, if applicableaa
2.Unfasten the screws of face plate until the blade is detached from shelf
3.Open the lower and the upper handle by pressing the two handle components together and turning the handles outwarda
The blue LED blinks indicating that the blade power???down process is on???going.a
4.Wait until the blue LED is illuminated permanently
Note: if the LED continues to blink, a possible reason may be that upper layer software rejects the blade extraction request.a
Data loss
Removing the blade with the blue LED still blinking causes data loss.
Wait until the blue LED is permanently illuminated, before removing the blade.
5. Remove the blade from the shelf
Installation in Nonpowered Shelves
Installation Procedure
1.Power down the shelfaa
2.Ensure that the top and botton ejector handles are in the outward position
3.Insert blade into the shelf by placing the top and bottom edges of the blade in the card guides of the shelf. Ensure that the guiding module of shelf and blade are aligned properly.a
4.Slide the blade into the shelf until you feel resistance
If an RTM is already installed in the same slot, be careful not to bend any pins of the P30 to P32 backplane connectors.a
5.Hook the lower and upper handle into the shelf rail recessed
6.Fully insert the blade and lock it to the shelf by pressing the two components of the lower and upper handles together and turning the handles towards the face plate
PENT/ATCA???717 | 55 |
Installation | Blade Installation |
|
|
7.Tighten the face plate screws which secure the blade to the shelf.a
8.Connect cables to the face plate, if applicable
Removal Procedure
1.Remove face plate cables, if applicableaa
2.Unfasten the screws of the face plate until the blade is detached from the shelf
3.Open the lower and the upper handle by pressing the two handle components together and turning the handles outward
4.Remove the blade from the shelf
56 | PENT/ATCA???717 |
Cable Accessory Kits | Installation |
|
|
Cable Accessory Kits
At the time of writing this manual the following cable accessory kits are available:aa
SACC/CABLE/PMC/RJ???45
SACC/CABLE/RJ45/DSUB
SACC/CABLE/USB
Note:aCheck with your local Motorola representative for the availability of further accessory kits.a
ACC/CABLE/PMC/RJ???45
The ACC/CABLE/PMC/RJ45 is an accessory kit compiled for the ACC/ARTM???717 rear transition module. It contains a splitter cable which allows to access the serial interfaces of PPMC???280 modules installed on the front blade via the ARTM???717 face plate.
ACC/CABLE/RJ45/DSUB
The ACC/CABLE/RJ45/DSUB/5E is an accessory kit containing a shielded cable of 2m length and an RJ???45/DSUB adapter plug. The cable provides Null???modem functionality which enables you to connect a laptop to the serial interface of the blade. The cable can be connected to either an installed CMC module or RTM.
ACC/CABLE/USB
The ACC/CABLE/USB/5E is an USB adapter cable of 200 mm length which converts the mini USB face plate connectors to USB A female.
PENT/ATCA???717 | 57 |
3
Controls, Indicators, and Connectors
58 | PENT/ATCA???717 |
Face Plate | Controls, Indicators, and Connectors |
|
|
Face Plate
The following figure shows the connectors, keys and LEDs available on the face plate.a
P
M
C 1
OOS
OK
ACT
HDD
U
S
B
1P
M
C 2
U
S
B 2
P
M
C 3
R
E 
S
E
T
H/S
P
M
C 4
Figure 7: Face Plate
LEDs
The following figure shows all LEDs available at the face plate.aaa
PENT/ATCA???717 | 59 |
Controls, Indicators, and Connectors | Face Plate | |||
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OOS
OK
ACT
HDD
H/S
Figure 8: Location of Face Plate LEDs
The meaning of these LEDs is described in the following table.a
Table 7: Face Plate LEDs
LED | Description |
OOS | Out Of Serviceaa |
| Red: Blade out of service |
| OFF: Blade working properly |
OK | Payload power statusaa |
| Green: Supply voltages are within threshold values |
| OFF: Supply voltages are outside threshold values |
ACT | Redundancy status |
| Amber: Blade is active |
| OFF: Blade is stand???by |
60 | PENT/ATCA???717 |
Face Plate | Controls, Indicators, and Connectors |
|
|
LED | Description |
HDD | After power???up or reset |
| If no valid BIOS image has been found, the LED is lit red and the |
| blade enters into BIOS crisis recovery mode.a |
| Note that the enterring into BIOS crisis recovery mode can also be |
| enforced via the on???board switch SW2???4.a |
| For further details about the BIOS crisis recovery mode, refer |
| |
| During booting |
| During booting this LED indicates the boot status. For each task the |
| BIOS POST executes, the LED is toggled between red and green.a |
| During normal blade operation: |
| Now the LED indicates the combined parallel/serial ATA activity or is |
| used as user LED. Toggling between both modes is done via the LED |
| control registeraa |
| In user mode: |
| Depending on the FPGA LED control register, the LED is either red, |
| green or OFF.a |
| In parallel/serial ATA activity mode: |
| Green: Combined activity of parallel and serial ATA interfaces.a |
| OFF: No activity |
H/S | FRU State Machineaa |
| During blade installation |
| Permanently blue: On???board IPMC powers up |
| Blinking blue: Blade communicates with shelf manager |
| OFF: Blade is active |
| During blade removal |
| Blinking blue: Blade notifies shelf manager of its desire to deactivate |
| Permanently blue: Blade is ready to be extracted |
Keys
The blade provides one face plate reset key.a
PENT/ATCA???717 | 61 |
Controls, Indicators, and Connectors | Face Plate | |||
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Reset
Key
P
M
C 3
R
E
S
E
T
Figure 9: Location of Reset Key
On pressing it, a hard reset is triggered and all attached on???board devices are reset.
Note:aThe IPMC is not reset via this key.a
Connectors
The blade provides two mini USB 2.0 connectors of type AB at its face plate. They correspond to the USB interfaces 1 and 2. An adapter cable accessory kit called ACC/CABLE/USB is available for the blade. It converts the mini USB male face plate connectors to USB female connectors.aaa
62 | PENT/ATCA???717 |
Face Plate |
| Controls, Indicators, and Connectors |
|
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USB 1
USB 2
ACT
HDD
U
S
B
1P
M
C 2
U
S
B 2
Figure 10: Location of USB Connectors
Their pinout is given below.a
| +5V |
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1 |
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2 | USB_X_D??? |
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3 | USB_X_D+ |
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4 | n.c. |
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5 | GND |
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Figure 11: Face Plate USB Connector Pinout
PENT/ATCA???717 | 63 |
Controls, Indicators, and Connectors | On???Board Connectors |
|
|
On???Board Connectors
The blade provides the following on???board connectors:
SCompactFlash
SPMC
SParallel ATAa
SSerial ATA
SCMC
SATCA backplane connectors
Note:aThe blade may provide further on???board connectors. These are used for debug purposes only and are therefore not documented in this guide.a
CompactFlash
The CompactFlash connector is standard and is therefore not further described in this guide.a
PMC
The blade provides the four PMC sites PMC#1 to PMC#4. For each PMC site the four PMC connectors Pn1 to Pn4 are provided. See the following figure.aaa
64 | PENT/ATCA???717 |
On???Board Connectors |
|
| Controls, Indicators, and Connectors | ||||||||||||||||||||
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Figure 12: Location of PMC Connectors Pn1 to Pn4
The connectors Pn1 to Pn3 implement the PMC pinouts as specified by the IEEE P1386.1 standard. Therefore they are not documented in this guide. The connector Pn4 contains PMC I/O signals and is described in the following.a
Pn4 carries the following types of signals:
SPower signals (GND)
SClock signals (CLK_*, NETREF))
SSignals routed to on???board Ethernet switch (ETH*_)
SSignals routed to RTM (PMC_IO_*)
Part of the signals that are routed to the on???board switch and RTM (with the exception of PMC_IO_25, 26, 28, 29, 30 and 31) are grouped into length???matched differential pairs of 100 ??? impedance.a
PENT/ATCA???717 | 65 |
Controls, Indicators, and Connectors | On???Board Connectors |
|
|
On the PMC sites 1 and 4, two Ethernet ports (signals named ETH*_) are routed to the on???board switch. On the PMC sites 2 and 3, only one port is routed to the on???board switch. The following two figures show the connector pinouts.aaa
Diff. Pair
Diff. Pair
Diff. Pair
Diff. Pair
Diff. Pair
Diff. Pair
Diff. Pair
Diff. Pair
Diff. Pair
Diff. Pair
Diff. Pair
Diff. Pair
{ | 1 | n.c. |
3 | n.c. | |
| 5 | n.c. |
{ | 7 | n.c. |
9 | n.c. |
11GND
{13 ETHB_DA+
15ETHB_DA???
17GND
{19 ETHB_DB+
21ETHB_DB???
23NETREF
25PMC_IO_25
27n.c.
29PMC_IO_29
31CLK8_B or PMC_IO_31
{33 PMC_IO_33
35PMC_IO_35
{37 PMC_IO_37
39PMC_IO_39
{41 PMC_IO_41
43PMC_IO_43
{45 PMC_IO_45
47PMC_IO_47
{49 PMC_IO_49
51PMC_IO_51
{53 PMC_IO_53
55PMC_IO_55
{57 PMC_IO_57
59PMC_IO_59
{61 PMC_IO_61
63PMC_IO_63
n.c.
n.c.
n.c.
n.c.
n.c.
GND ETHB_DC+ ETHB_DC???
GND ETHB_DD+ ETHB_DD??? n.c. PMC_IO_26 PMC_IO_28
CLK8_A or PMC_IO_30 n.c.
PMC_IO_34
PMC_IO_36
PMC_IO_38
PMC_IO_40
PMC_IO_42
PMC_IO_44
PMC_IO_46
PMC_IO_48 n.c. PMC_IO_52 PMC_IO_54 n.c. PMC_IO_58 PMC_IO_60 PMC_IO_62 PMC_IO_64
42 | } Diff. Pair |
6 |
|
108 | } Diff. Pair |
12 |
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1614 | } Diff. Pair |
18 |
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2220 | } Diff. Pair |
24 |
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2826 | } Diff. Pair |
30 |
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32 |
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3634 | } Diff. Pair |
4038 | } Diff. Pair |
4442 | } Diff. Pair |
4846 | } Diff. Pair |
50 |
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5452 | } Diff. Pair |
56 |
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6058 | } Diff. Pair |
6462 | } Diff. Pair |
Figure 13: PMC Sites 1 and 4 ??? Pn4 Connector Pinout
66 | PENT/ATCA???717 |
On???Board Connectors | Controls, Indicators, and Connectors |
|
|
Diff. Pair
Diff. Pair
Diff. Pair
Diff. Pair
Diff. Pair
Diff. Pair
Diff. Pair
Diff. Pair
Diff. Pair
Diff. Pair
Diff. Pair
Diff. Pair
{1 ETHA_DA+
3 ETHA_DA???
5 GND
{7 ETHA_DB+
9 ETHA_DB???
11GND
{13 ETHB_DA+
15ETHB_DA???
17GND
{19 ETHB_DB+
21ETHB_DB???
23NETREF
25PMC_IO_25
27n.c.
29PMC_IO_29
31CLK8_B or PMC_IO_31
{33 PMC_IO_33
35PMC_IO_35
{37 PMC_IO_37
39PMC_IO_39
{41 PMC_IO_41
43PMC_IO_43
{45 PMC_IO_45
47PMC_IO_47
{49 PMC_IO_49
51PMC_IO_51
{53 PMC_IO_53
55PMC_IO_55
{57 PMC_IO_57
59PMC_IO_59
{61 PMC_IO_61
63PMC_IO_63
ETHA_DC+
ETHA_DC???
GND ETHA_DD+ ETHA_DD???
GND ETHB_DC+ ETHB_DC???
GND ETHB_DD+ ETHB_DD??? n.c. PMC_IO_26 PMC_IO_28
CLK8_A or PMC_IO_30 n.c.
PMC_IO_34
PMC_IO_36
PMC_IO_38
PMC_IO_40
PMC_IO_42
PMC_IO_44
PMC_IO_46
PMC_IO_48 n.c. PMC_IO_52 PMC_IO_54 n.c. PMC_IO_58 PMC_IO_60 PMC_IO_62 PMC_IO_64
42 | } Diff. Pair |
6 |
|
108 | } Diff. Pair |
12 |
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1614 | } Diff. Pair |
18 |
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2220 | } Diff. Pair |
24 |
|
2826 | } Diff. Pair |
30 |
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32 |
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3634 | } Diff. Pair |
4038 | } Diff. Pair |
4442 | } Diff. Pair |
4846 | } Diff. Pair |
50 |
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5452 | } Diff. Pair |
56 |
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6058 | } Diff. Pair |
6462 | } Diff. Pair |
Figure 14: PMC Sites 2 and 3 ??? Pn4 Connector Pinout
Note:a
SThe signals available at pins 30 and 31 depend on the settings of the on???board switches SW7???1 to SW7???4. Seeasection "Switch Settings" on pagea42a for further details.a
SBy default, the PMC I/O Ethernet signals (ETH_xxx) are routed to the on???board switch via magnetics. As an assembly option the magnetics can be by???passed and the Ethernet signals can be accessed via an installed PMC uplink module from Motorola. Consult your local Motorola representative for details.a
SBy default the signals at pins 61 to 64 are routed the zone 3 connectors where they are available as PMC I/O signals. As an assembly option these signals can be routed to the on???board Ethernet switch as further 100BaseTX interface. Consult your local Motorola representative for details.a
Parallel ATA Connector
The blade provides one parallel Advanced Technology Attachment (ATA) connector which allows to connect a 2.5" hard disk to the blade. The location of this connector is shown in the following figure.aaa
PENT/ATCA???717 | 67 |
Controls, Indicators, and Connectors |
|
| On???Board Connectors | ||||||||||||
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Figure 15: Location of Parallel ATA Connector
The pinout of the connector is as follows.a
68 | PENT/ATCA???717 |
On???Board Connectors | Controls, Indicators, and Connectors |
|
|
1 | IDE1_RST# | GND | 2 |
3 | IDE1_D7 | IDE1_D8 | 4 |
5 | IDE1_D6 | IDE1_D9 | 6 |
7 | IDE1_D5 | IDE1_D10 | 8 |
9 | IDE1_D4 | IDE1_D11 | 10 |
11 | IDE1_D3 | IDE1_D12 | 12 |
13 | IDE1_D2 | IDE1_D13 | 14 |
15 | IDE1_D1 | IDE1_D14 | 16 |
17 | IDE1_D0 | IDE1_D15 | 18 |
19 | GND | KEY | 20 |
21 | IDE1_DREQ | GND | 22 |
23 | IDE1_IOW# | GND | 24 |
25 | IDE1_IOR# | GND | 26 |
27 | IDE1_IORDY | IDE1_CSEL | 28 |
29 | IDE1_DACK# | GND | 30 |
31 | IDE1_INT | n.c. | 32 |
33 | IDE1_A1 | IDE1_CBLID# | 34 |
35 | IDE1_A0 | IDE1_A2 | 36 |
37 | IDE1_CS0# | IDE1_CS1# | 38 |
39 | IDE1_DASP# | GND | 40 |
41 | 5V | 5V | 42 |
43 | GND | n.c. | 44 |
Figure 16: Parallel ATA Connector Pinout
Serial ATA Connector
The blade provides one Serial Advanced Technology Attachment (SATA) connector which allows to connect a hard disk to the blade. The location of the SATA connector is shown in the following figure.aaa
PENT/ATCA???717 | 69 |
Controls, Indicators, and Connectors |
|
| On???Board Connectors | ||||||||||
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Figure 17: Location of Serial ATA Connector
The pinout of the SATA connector is given in the following figure.a
70 | PENT/ATCA???717 |
On???Board Connectors | Controls, Indicators, and Connectors |
|
|
1 | GND |
| 1 | ||
| |||||
2 | SATA0_TX+ |
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3 | SATA0_TX??? |
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4 | GND |
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5 | SATA0_RX??? |
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6 | SATA0_RX+ |
| 7 | ||
| |||||
| |||||
7 | GND |
| |||
| |||||
| |||||
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| 3.3V |
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1 |
| 1 | |||
| |||||
2 | 3.3V |
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3 | 3.3V |
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4 | GND |
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5 | GND |
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6 | GND |
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7 | 5V |
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8 | 5V |
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9 | 5V |
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10 | GND |
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11 | RSV |
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12 | 12V |
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13 | 12V |
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14 | 12V |
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| 15 | |
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15 | 12V |
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CMC Module Connector
The blade provides one CMC connector which allows to connect a CMC debug module to the blade. A CMC debug module is available as accessory kit for the blade. The CMC module uses the same mounting holes as PMC slot #4.a
PENT/ATCA???717 | 71 |
Controls, Indicators, and Connectors |
|
| On???Board Connectors | ||||||||||
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Figure 18: Location of CMC Connector
The pinout of the CMC connector is given in the following figure.a
72 | PENT/ATCA???717 |
On???Board Connectors | Controls, Indicators, and Connectors |
|
|
1 | V3P3 |
|
| V3P3 | |
3 | RS232_1_DCD??? |
|
| RS232_1_DSR??? | |
5 | RS232_1_RXD |
|
| RS232_1_RTS??? | |
7 | RS232_1_TXD |
|
| RS232_1_CTS??? | |
9 | RS232_1_DTR??? |
|
| RS232_1_RI??? | |
11 | RS232_3_DCD??? |
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| RS232_3_DSR??? | |
13 | RS232_3_RXD |
|
| RS232_3_RTS??? | |
15 | RS232_3_TXD |
|
| RS232_3_CTS??? | |
17 | RS232_3_DTR??? |
|
| RS232_3_RI??? | |
19 | GND |
|
| GND | |
21 | KBD_DATA |
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|
| MSE_DATA |
23 | KBD_CLK |
|
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| MSE_CLK |
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| |||
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| |||
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| |||
25 | VP5_KBD |
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| GND |
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| |||
27 | GND |
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| Reserved |
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| |||
29 | Reserved |
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| Reserved |
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| |||
31 | Reserved |
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| Reserved |
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33 | Reserved |
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| Reserved |
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35 | Reserved |
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| Reserved |
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37 | Reserved |
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| Reserved |
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39 | Reserved |
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| Reserved |
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41 | Reserved |
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| Reserved |
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43 | Reserved |
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| Reserved |
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45 | GND |
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| GND | |
47 | Reserved |
|
| Reserved | |
49 | Reserved |
|
| Reserved | |
51 | Reserved |
|
| Reserved | |
53 | Reserved |
|
| GND | |
55 | n.c. |
|
| Reserved | |
57 | Reserved |
|
| Reserved | |
59 | n.c. |
|
| VP12 | |
61 | Reserved |
|
| Reserved | |
63 | V3P3 |
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| V3P3 | |
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2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
For further information about the CMC module refer to theaACC/ATCA???CMC???MODULE Installation Guide.aa
AdvancedTCA Backplane Connectors
The AdvancedTCA backplane connectors reside in the three zones 1 to 3 as specified by the AdvancedTCA standard and are called P10, P20, P22, P23, P30, P31, and P32. The location of these connectors is shown in the following figure.aaa
PENT/ATCA???717 | 73 |
Controls, Indicators, and Connectors |
|
| On???Board Connectors | ||||||||||
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The pinouts of all these connectors are given in this section.a
The connector residing in zone 1 is called P10 and carries the following signals:
SPower feed for the blade (ABP_VM48_x_CON and ABP_RTN_A_CON)
SPower enable (ABP_ENABLE_x)
SIPMB bus signals (APMB_P10_IPMB0_x_yyy)
SGeographic address signals (ABP_P10_HAx)
SGround signals (ABP_P10_SHELF_GND and GND)
SReserved signals
74 | PENT/ATCA???717 |
On???Board Connectors | Controls, Indicators, and Connectors |
|
|
|
|
| 21 17 |
| |
33 | 30 | 28 | 25 | 13 | 1 |
| 32 |
| 27 |
|
|
34 | 31 | 29 | 26 | 16 | 4 |
|
|
| 24 | 20 |
|
| Reserved |
1 | |
2 | Reserved |
3 | Reserved |
4 | Reserved |
5 | ABP_P10_HA0 |
6 | ABP_P10_HA1 |
7 | ABP_P10_HA2 |
8 | ABP_P10_HA3 |
9 | ABP_P10_HA4 |
10 | ABP_P10_HA5 |
11 | ABP_P10_HA6 |
12 | ABP_P10_HA7 |
13 | ABP_P10_IPMB0_A_SCL |
14 | ABP_P10_IPMB0_A_SDA |
15 | ABP_P10_IPMB0_B_SCL |
16 | ABP_P10_IPMB0_B_SDA |
17 | n.c. |
|
|
18n.c.
19n.c.
20n.c.
21n.c.
22n.c.
23n.c.
24n.c.
25ABP_P10_SHELF_GND
26GND
27ABP_ENABLE_B
28ABP_RTN_A_CON
29ABP_RTN_B_CON
30n.c.
31n.c.
32ABP_ENABLE_A
33ABP_VM48_A_CON
34ABP_VM48_B_CON
Figure 19: P10 Backplane Connector Pinout
Zone 2 contains the three connectors P20, P22 and P23. They carry the following types of signals:
STelecom clock signals (CLKx_)
SBase interface signals (BASE_)
SFabric channel interfaces (FAB_)
Some of the pins provided by P20, P21 and P23 are defined as optional in the AdvancedTCA specification and are unused on the blade. If the AdvancedTCA specification defines these signals as input signals, they are terminated on the blade and marked as "TERM_" in the following pinouts. In all other cases the pins are unconnected and consequently marked as "n.c.".a
The pinouts of P20, P21 and P23 are as follows.a
PENT/ATCA???717 | 75 |
Controls, Indicators, and Connectors | On???Board Connectors |
|
|
| a | b | a b | c d | e f | g h | c | d |
|
1 | CLK_1A+ | CLK1A??? |
|
|
|
| CLK1B+ | CLK1B??? | 1 |
2 | n.c. | n.c. |
|
|
|
| TERM_RX4_UP+ | TERM_RX4_UP??? 2 | |
3 | n.c. | n.c. |
|
|
|
| TERM_RX2_UP+ | TERM_RX2_UP??? 3 | |
4 | FAB8_TX+ | FAB8_TX??? |
|
|
|
| FAB8_RX+ | FAB8_RX??? | 4 |
5 | n.c. | n.c. |
|
|
|
| TERM_RX15_2+ | TERM_RX15_2??? 5 | |
6 | n.c. | n.c. |
|
|
|
| TERM_RX15_0+ | TERM_RX15_0??? 6 | |
7 | n.c. | n.c. |
|
|
|
| TERM_RX14_2+ | TERM_RX14_2??? 7 | |
8 | n.c. | n.c. |
|
|
|
| TERM_RX14_0+ | TERM_RX14_0??? 8 | |
9 | n.c. | n.c. |
|
|
|
| TERM_RX13_2+ | TERM_RX13_2??? 9 | |
10 n.c. | n.c. |
|
|
|
| TERM_RX13_0+_ | TERM_RX13_0??? | 10 | |
Figure 20: P20 Backplane Connector Pinout ??? Rows A to D
|
|
|
|
| a b | c d | e f | g h |
|
|
|
|
| |||
| e | f | g | h |
|
|
| |||||||||
1 | CLK2A+ | CLK_2A??? |
|
|
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|
|
| CLK_2B+ | CLK_2B??? | 1 |
| |
2 | CLK_3A+ | CLK_3A??? |
|
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|
|
| CLK_3B+ | CLK_3B??? | 2 |
| |
|
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|
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| |||||||
3 | n.c. | n.c. |
|
|
|
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|
| TERM_RX3_UP+ TERM_RX3_UP??? | 3 |
| ||
|
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|
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| |||||||
4 | n.c. | n.c. |
|
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|
|
| TERM_RX1_UP+ | TERM_RX1_UP??? | 4 |
| |
|
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|
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|
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|
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| |||||||
5 | n.c. | n.c. |
|
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| TERM_RX15_3+ TERM_RX15_3??? | 5 |
| ||
|
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| |||||||
6 | n.c. | n.c. |
|
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| TERM_RX15_1+ TERM_RX15_1??? | 6 |
| ||
|
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| |||||||
7 | n.c. | n.c. |
|
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| TERM_RX14_3+ TERM_RX14_3??? | 7 |
| ||
|
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| |||||||
8 | n.c. | n.c. |
|
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| TERM_RX14_1+ TERM_RX14_1??? | 8 |
| ||
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| |||||||
9 | n.c. | n.c. |
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| TERM_RX13_3+ TERM_RX13_3??? | 9 |
| ||
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| |||||||
10 | n.c. | n.c. |
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| TERM_RX13_1+ | TERM_RX13_1??? | 10 |
| |
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Figure 21: P20 Backplane Connector Pinout ??? Rows E to H |
|
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| |||||||||||
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|
| a b | c d | e f | g h |
|
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| ||||
| a | b |
| c | d |
|
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| ||||||||
1 | n.c. | n.c. |
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|
| TERM_RX7_2+ | TERM_RX7_2??? |
| 1 |
| |
2 | FAB7_TX+ | FAB7_TX??? |
|
|
|
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|
|
| FAB7_RX+ | FAB7_RX??? |
| 2 |
| |
|
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| |||||||
3 | n.c. | n.c. |
|
|
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|
|
| TERM_RX6_2+ | TERM_RX6_2??? |
| 3 |
| |
|
|
|
|
|
|
|
|
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| |||||||
4 | FAB6_TX+ | FAB6_TX??? |
|
|
|
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|
|
| FAB6_RX+ | FAB6_RX??? |
| 4 |
| |
|
|
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|
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| |||||||
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| |||||||
5 | n.c. | n.c. |
|
|
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|
|
| TERM_RX5_2+ | TERM_RX5_2??? |
| 5 |
| |
|
|
|
|
|
|
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|
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| |||||||
6 | FAB5_TX+ | FAB5_TX??? |
|
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|
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| FAB5_RX+ | FAB5_RX??? |
| 6 |
| |
|
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| |||||||
7 | n.c. | n.c. |
|
|
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|
|
| TERM_RX4_2+ | TERM_RX4_2??? |
| 7 |
| |
|
|
|
|
|
|
|
|
|
| |||||||
8 | FAB4_TX+ | FAB4_TX??? |
|
|
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|
|
| FAB4_RX+ | FAB4_RX??? |
| 8 |
| |
|
|
|
|
|
|
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|
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| |||||||
9 | n.c. | n.c. |
|
|
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|
|
| TERM_RX3_2+ | TERM_RX3_2??? |
| 9 |
| |
|
|
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|
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| |||||||
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| |||||||
10 | FAB3_TX+ | FAB3_TX??? |
|
|
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| FAB3_RX+ | FAB3_RX??? |
| 10 | ||
|
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| ||||||||
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Figure 22: P22 Backplane Connector Pinout ??? Rows A to D
76 | PENT/ATCA???717 |
On???Board Connectors | Controls, Indicators, and Connectors |
|
|
|
|
|
| a b c d e f g h |
|
| ||||||||
|
|
|
| g | h |
| ||||||||
| e | f | ||||||||||||
1 | n.c. | n.c. |
|
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|
| TERM_RX7_3+ TERM_RX7_3??? | 1 | ||
2 | n.c. | n.c. |
|
|
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|
|
| TERM_RX7_1+ TERM_RX7_1??? | 2 | ||
|
|
|
|
|
|
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| |||||||
3 | n.c. | n.c. |
|
|
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|
|
| TERM_RX6_3+ TERM_RX6_3??? | 3 | ||
|
|
|
|
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| |||||||
4 | n.c. | n.c. |
|
|
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|
| TERM_RX6_1+ TERM_RX6_1??? | 4 | ||
|
|
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| |||||||
5 | n.c. | n.c. |
|
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|
| TERM_RX5_3+ TERM_RX5_3??? | 5 | ||
|
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| |||||||
6 | n.c. | n.c. |
|
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| TERM_RX5_1+ TERM_RX5_1??? | 6 | ||
|
|
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| |||||||
7 | n.c. | n.c. |
|
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| TERM_RX4_3+ TERM_RX4_3??? | 7 | ||
|
|
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| |||||||
8 | n.c. | n.c. |
|
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| TERM_RX4_1+ | TERM_RX4_1??? | 8 | |
|
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| |||||||
9 | n.c. | n.c. |
|
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|
| TERM_RX3_3+ | TERM_RX3_3??? | 9 | |
|
|
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| |||||||
10 | n.c. | n.c. |
|
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|
| TERM_RX3_1+ | TERM_RX3_1??? | 10 | |
|
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| |||||||
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Figure 23: P22 Backplane Connector Pinout ??? Rows E to H
a
b
a b | c d | e f | g h c | d |
1n.c.
2FAB2_TX+
3n.c.
4FAB1_TX+
5BASE_DA1+
6BASE_DA2+
7n.c.
8n.c.
9n.c.
10 n.c.
n.c.
FAB2_TX???
n.c.
FAB1_TX+ BASE_DA1??? BASE_DA2???
n.c.
n.c.
n.c.
n.c.
TERM_RX2_2+
FAB2_RX+
TERM_RX1_2+
FAB1_RX+
BASE_DB1+
BASE_DB2+
n.c. 
n.c.
n.c. |
n.c.
|
|
TERM_RX2_2??? | 1 |
FAB2_RX??? | 2 |
TERM_RX1_2??? | 3 |
FAB1_RX??? | 4 |
BASE_DB1??? | 5 |
BASE_DB2??? | 6 |
n.c. | 7 |
n.c. | 8 |
n.c. | 9 |
n.c. | 10 |
|
|
Figure 24: P23 Backplane Connector Pinout ??? Rows A to D
|
|
|
| a b c d e f g h |
|
|
| ||||||
| e | f | g | h |
| ||||||||
1 | n.c. | n.c. |
|
|
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|
|
| TERM_RX2_3+ TERM_RX2_3??? | 1 | |
2 | FAB2T_TX+ | FAB2T_TX??? |
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| FAB2T_RX+ | FAB2T_RX??? | 2 |
|
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| ||||||
3 | n.c. | n.c. |
|
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| TERM_RX3_1+ TERM_RX3_1??? | 3 | |
|
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|
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| ||||||
4 | FAB1T_TX+ | FAB1T_TX??? |
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| FAB1T_RX+ | FAB1T_RX??? | 4 |
|
|
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| ||||||
5 | BASE_DC1+ | BASE_DC1??? |
|
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| BASE_DD1+ | BASE_DD1??? | 5 |
|
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| ||||||
6 | BASE_DC2+ | BASE_DC2??? |
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| BASE_DD2+ | BASE_DD2??? | 6 |
|
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| ||||||
7 | n.c. | n.c. |
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| n.c. | n.c. | 7 |
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| ||||||
8 | n.c. | n.c. |
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| n.c. | n.c. | 8 |
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| ||||||
9 | n.c. | n.c. |
|
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| n.c. | n.c. | 9 |
|
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| ||||||
10 | n.c. | n.c. |
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| n.c. | n.c. | 10 |
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Figure 25: P23 Backplane Connector Pinout ??? Rows E to H
PENT/ATCA???717 | 77 |
Controls, Indicators, and Connectors | On???Board Connectors |
|
|
Zone 3 contains the three connectors P30 to P32. They are used to connect an RTM to the blade and carry the following signals
SSerial (RS232_x_yyyy)
SSerial ATA (SATAx_yyy)
SUSB (USBxy)
SKeyboard/Mouse (KBD_xxx, MS_xxx)
SIPMI (IPMB1_xxx, ISMB_xxx))
SPower (VP12_RTM, V3P3_RTM)
SPMC user I/O (PMCx_IO_yy)
SGeneral control signals (BD_PRESENTx, RTM_PRSNT_N, RTM_RST_KEY*, RTM_RST*)
a
1R232_2_RXD
2RS232_2_DCD???
3RTM_GPO
4USB0+
5n.c.
6n.c.
7SATA0_TX+
8n.c.
9IPMB1_SCL
10 VP12_RTM
| a b c d e f g h |
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b | c | d |
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| RS232_2_RTS??? RS232_2_CTS??? |
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R232_2_TXD | 1 | |||||||||
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RS232_2_DTR??? |
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| RS232_2_DSR???RS232_2_RI??? | 2 | ||
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n.c. |
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| n.c. | n.c. | 3 | |
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USB0??? |
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| USB1+ | USB1??? | 4 | |
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n.c. |
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| n.c. | n.c. | 5 | |
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n.c. |
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| n.c. | n.c. | 6 | |
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SATA0_TX??? |
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| SAT0_RX+ | SATA0_RX??? | 7 | |
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n.c. |
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| n.c. | n.c. | 8 | |
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IPMB1_SDA |
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| IPMB1_V3P3 | ISMB_ALERT_N | 9 | |
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VP12_RTM |
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| V3P3_RTM | V3P3_RTM | 10 | |
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Figure 26: P30 Backplane Connector Pinout ??? Rows A to D
| e | f | a b | c d | e f | g h | g | h |
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1 | RS232_4_RXD RS232_4_TXD |
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| RS232_4_RTS??? RS232_4_CTS??? 1 | |||
2 | RS232_4_DCD???RS232_4_DTR??? |
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| RS232_4_DSR???RS232_4_RI??? 2 | |||
3 | KBD_DAT | KBD_CLK |
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| MS_DAT | MS_CLK | 3 |
4 n.c. | n.c. |
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| n.c. | n.c. | 4 | |
5 n.c. | n.c. |
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| n.c. | n.c. | 5 | |
6 n.c. | n.c. |
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| n.c. | n.c. | 6 | |
7 | SATA1_TX+ | SATA1_TX??? |
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| SATA1_RX+ | SATA1_RX??? | 7 |
8 n.c. | n.c. |
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| n.c. | n.c. | 8 | |
9 | BD_PRESENT??? | RTM_PRSNT_N |
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| RTM_RST??? | 9 |
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| RTM_RST_KEY??? | ||||
10VCC_RTM | n.c. |
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| SMB_CLK | SMB_DATA | 10 | |
Figure 27: P30 Backplane Connector Pinout ??? Rows E to H
78 | PENT/ATCA???717 |
On???Board Connectors | Controls, Indicators, and Connectors |
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| a | b |
| PMC1_IO_26 |
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1 | PMC1_IO_28 | |
2 | PMC1_IO_34 | PMC1_IO_36 |
3 | PMC1_IO_42 | PMC1_IO_44 |
4 | PMC1_IO_52 | PMC1_IO_54 |
5 | PMC1_IO_61 | PMC1_IO_63 |
6 | PMC2_IO_29 | PMC2_IO_31 |
7 | PMC2_IO_38 | PMC2_IO_40 |
8 | PMC2_IO_46 | PMC2_IO_48 |
9 | PMC2_IO_58 | PMC2_IO_60 |
10 | VP12_RTM | VCC_RTM |
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c | d |
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| PMC1_IO_30 |
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| PMC1_IO_25 | 1 | |
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| PMC1_IO_37 | PMC1_IO_39 | 2 |
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| PMC1_IO_45 | PMC1_IO_47 | 3 |
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| PMC1_IO_53 | PMC1_IO_55 | 4 |
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| PMC1_IO_62 | PMC1_IO_64 | 5 |
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| PMC2_IO_33 | PMC2_IO_35 | 6 |
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| PMC2_IO_41 | PMC2_IO_43 | 7 |
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| PMC2_IO_49 | PMC2_IO_51 | 8 |
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| PMC2_IO_57 | PMC2_IO_59 | 9 |
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| V3P3_RTM | n.c. | 10 |
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Figure 28: P31 Backplane Connector Pinout ??? Rows A to D
| e | f |
| PMC1_IO_29 | PMC1_IO_31 |
1 | ||
2 | PMC1_IO_38 | PMC1_IO_40 |
3 | PMC1_IO_46 | PMC1_IO_48 |
4 | PMC1_IO_58 | PMC1_IO_60 |
5 | PMC2_IO_26 | PMC2_IO_28 |
6 | PMC2_IO_34 | PMC2_IO_36 |
7 | PMC2_IO_42 | PMC2_IO_44 |
8 | PMC2_IO_52 | PMC2_IO_54 |
9 | PMC2_IO_61 | PMC2_IO_63 |
10 | n.c. | n.c. |
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a b | c d | e f | g h | g | h |
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| PMC1_IO_33 | PMC1_IO_35 1 | |
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| PMC1_IO_41 | PMC1_IO_43 2 | |
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| PMC1_IO_49 | PMC1_IO_51 3 | |
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| PMC1_IO_57 | PMC1_IO_59 4 | |
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| PMC2_IO_25 | PMC2_IO_30 5 | |
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| PMC2_IO_37 | PMC2_IO_39 6 | |
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| PMC2_IO_45 | PMC2_IO_47 7 | |
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| PMC2_IO_53 | PMC2_IO_55 8 | |
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| PMC2_IO_62 | PMC2_IO_64 9 | |
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| n.c. | n.c. | 10 |
Figure 29: P31 Backplane Connector Pinout ??? Rows E to H
| a | b |
| PMC3_IO_26 |
|
1 | PMC3_IO_28 | |
2 | PMC3_IO_34 | PMC3_IO_36 |
3 | PMC3_IO_42 | PMC3_IO_44 |
4 | PMC3_IO_52 | PMC3_IO_54 |
5 | PMC3_IO_61 | PMC3_IO_63 |
6 | PMC4_IO_29 | PMC4_IO_31 |
7 | PMC4_IO_38 | PMC4_IO_40 |
8 | PMC4_IO_46 | PMC4_IO_48 |
9 | PMC4_IO_58 | PMC4_IO_60 |
10 | VP12_RTM | VP5_RTM |
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| a b c d e f g h |
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c | d |
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| PMC3_IO_30 |
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| PMC3_IO_25 | 1 | |
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| PMC3_IO_37 | PMC3_IO_39 | 2 |
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| PMC3_IO_45 | PMC3_IO_47 | 3 |
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| PMC3_IO_53 | PMC3_IO_55 | 4 |
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| PMC3_IO_62 | PMC3_IO_64 | 5 |
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| PMC4_IO_33 | PMC4_IO_35 | 6 |
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| PMC4_IO_41 | PMC4_IO_43 | 7 |
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| PMC4_IO_49 | PMC4_IO_51 | 8 |
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| PMC4_IO_57 | PMC4_IO_59 | 9 |
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| V3P3_RTM | n.c. | 10 |
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Figure 30: P32 Backplane Connector Pinout ??? Rows A to D
PENT/ATCA???717 | 79 |
Controls, Indicators, and Connectors | On???Board Connectors |
|
|
| e | f |
| PMC3_IO_29 | PMC3_IO_31 |
1 | ||
2 | PMC3_IO_38 | PMC3_IO_40 |
3 | PMC3_IO_46 | PMC3_IO_48 |
4 | PMC3_IO_58 | PMC3_IO_60 |
5 | PMC4_IO_26 | PMC4_IO_28 |
6 | PMC4_IO_34 | PMC4_IO_36 |
7 | PMC4_IO_42 | PMC4_IO_44 |
8 | PMC4_IO_52 | PMC4_IO_54 |
9 | PMC4_IO_61 | PMC4_IO_63 |
10 | n.c. | n.c. |
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a b | c d | e f | g h | g | h |
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| PMC3_IO_33 | PMC3_IO_35 1 | |
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| PMC3_IO_41 | PMC3_IO_43 2 | |
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| PMC3_IO_49 | PMC3_IO_51 3 | |
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| PMC3_IO_57 | PMC3_IO_59 4 | |
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| PMC4_IO_25 | PMC4_IO_30 5 | |
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| PMC4_IO_37 | PMC4_IO_39 6 | |
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| PMC4_IO_45 | PMC4_IO_47 7 | |
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| PMC4_IO_53 | PMC4_IO_55 8 | |
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| PMC4_IO_62 | PMC4_IO_64 9 | |
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| n.c. | n.c. | 10 |
Figure 31: P32 Backplane Connector Pinout ??? Rows E to H
80 | PENT/ATCA???717 |
4
BIOS
PENT/ATCA???717 | 81 |
BIOS | Introduction |
|
|
Introduction
BIOS (Basic Input Output System) provides an interface between the operating system and the hardware of the blade. It is used for hardware configuration. Before loading the operating system, BIOS performs basic hardware tests and prepares the blade for the initial boot???up procedure.
During blade production, identical BIOS images are programmed into the blade???s boot and user flash. By default the blade boots from the boot flash. It is possible to select between boot and user flash as device to boot from. This is done via a OEM IPMI command. For further details refer to theaPENT/ATCA???715/717/7105/7107: Control via IPMI Programmer???s Guidea which can be downloaded from the Motorola literature catalog. The presence of two redundant flash devices also allows for updating the BIOS image without affecting running processes.aaa
The BIOS used on the blade is based on the Phoenix 4.0 Release 6.0 BIOS with several Motorola extensions integrated. Its main functions are:
SHardware set???up utility for setting configuration data
SMultiboot for a flexible boot order
SSerial console redirection for remote blade configuration
SSoftware upgrade utility
Note:aThe BIOS contains on???line documentation which provides detailed description of all BIOS functions. Therefore the description in this manual is restricted to the main BIOS functions.a
The BIOS set???up program is required to configure the hardware of the blade. This configuration is necessary for operating the blade and connected peripherals. It is stored in the battery backed???up CMOS memory as well as in the blade???s boot flash.a
Whenever you are not sure about configuration settings, restore the default values. They are provided in case a value has been changed and you wish to reset settings. To restore the default values, press <F9> in setup.
Note:a
SLoading the BIOS default values will affect all set???up items and will reset options previously altered.a
SIf you set the default values, the displayed default values are not yet stored to be effective for the next boot. They are just loaded to be displayed. However, they become effective if the BIOS setup is exited after changes have been saved.
82 | PENT/ATCA???717 |
Introduction | BIOS |
|
|
The BIOS complies to the following specifications:
SPlug and Play BIOS Specification 1.0A
SPCI BIOS Specification 2.1
SSMBIOS Specification 2.3
SBIOS Boot Specification 1.01
SPXE 2.0
PENT/ATCA???717 | 83 |
BIOS | Serial Console Redirection |
|
|
Serial Console Redirection
The firmware of the blade provides a serial console redirection feature. This allows remote blade configuration by connecting a terminal to the blade via a serial communication link.a
The terminal can be connected to display VGA text information. Terminal keyboard input is redirected and treated as a normal PC keyboard input. The serial console redirection feature can be configured via setup utility.
Note:aIf serial console redirection is enabled the terminal represents an option and is not necessarily required for boot???up procedure.a
Requirements
For serial console redirection, the following is required:
STerminal which supports a VT100 or ANSI modea
SNULL???modem cable
Terminal emulation programs such as TeraTermPro can be used. In order to use TeraTermPro via the function keys, the keyboard configuration file of TeraTermPro has to be modified as follows:
Table 8: Key Codes for Terminal Emulation Program
Function Key | Key Code |
PF1 | 59 |
PF2 | 60 |
Default Configuration
By default, the blade can be accessed via the serial interface COM1. This interface is, by default, accessible via an installed RTM through an RJ???45 connector. If no RTM is present or you wish to access COM1 from the blade???s face plate, COM1 can alternatively be made accessible at an installed CMC module. Whether COM1 is available via RTM or CMC module depends on the setting of the on???board switch SW3???4 which enables/disables COM port swapping. The following table provides details.aaa
Setting of SW3???4 | COM1 is accessible via: |
OFF (default) | RTM (upper serial connector) |
ON | CMC module (upper serial connector) |
84 | PENT/ATCA???717 |
Serial Console Redirection | BIOS |
|
|
Note:a
SThe COM port routing described above is only applicable to BIOS versions w 2.0.0. Earlier BIOS versions used a different routing. For details refer to theaPENT/ATCA???715/717/7105/7107 BIOS Information Sheeta which can be downloaded from the Motorola literature catalog web site.
SCOM port swapping can also be enabled via an IPMI System Boot Options command. COM port swapping is enabled if either the on???board switch 3???4, the IPMI System Boot Options command or both enable it.a
A NULL???Modem cable is available as accessory kit for the blade. It converts the RJ???45 connector to a standard DSUB connector which can be connected to a remote terminal. The following communication parameters are used by default:
SBaud rate: 9600
SNo handshake
SPC ANSI
S8 data bits
SNo parity
S1 stop bit
All configuration parameters listed above can be modified via the BIOS.a
Connecting to the Blade
In order to connect to the blade using the serial console redirect feature, proceed as follows:.
Procedure
1.Configure terminal to communicate using the same parameters as in BIOS setup
2.Connect terminal to NULL???modem cable
3.Connect NULL???modem cable to COM port you have selected in BIOS setup
4.Start up blade
PENT/ATCA???717 | 85 |
BIOS | BIOS Crisis Recovery Mode |
|
|
BIOS Crisis Recovery Mode
Immediately after a reset or power???up a routine in the boot flash boot block is invoked which checks whether a valid BIOS image is available. If no valid image is found and consequently the blade is unable to boot, the blade enters into BIOS crisis recovery mode. In this mode a routine tries to load a BIOS crisis recovery image from a disk drive connected to the blade??? s USB interface. The BIOS crisis recovery image is basically a mini DOS with minimum functionality which replaces the corrupted image.a
A valid BIOS crisis recovery image can be downloaded from the former Force Computers SMART server or the Motorola website as part of the BIOS upgrade kit which which is available for this blade. The image is accompanied by readme files which describe how to create the BIOS upgrade/recovery disk and how to to replace a corrupted BIOS with the BIOS crisis recovery image.a
If the blade has enterred BIOS crisis recovery mode,the face plate LED "HDD" is lit ed. After the BIOS recovery image has been successfully flashed, the LED is lit green.a
Note:aFlashing the BIOS crisis recovery image may take up to two minutes. In order to avoid blade damage, it is absolutely important not to interrupt the flashing process. Therefore wait until the LED is lit green again, which indicates a successful flashing.a
86 | PENT/ATCA???717 |
Changing Configuration Settings | BIOS |
|
|
Changing Configuration Settings
When the system is turned on or rebooted, the presence and functionality of the system components is tested by POST (Power???On Self???Test).a
Press <F2> when requested. The main menu appears. It looks similar to the menu shown in the following figure. Note that the layout may slightly vary with new BIOS versions.a
Figure 32: Main Menu
Note:a
SMake sure that BIOS is properly configured prior to installing the operating system and its drivers.
SIf you save changes in setup, the next time the blade boots BIOS will configure the system according to the setup selections stored. If those values cause the system boot to fail, reboot and enter setup to get the default values or to change the selections that caused the failure. If the boot fails or is interrupted three times in a row, the default values are then loaded automatically.
In order to navigate in setup, use the arrow keys on the keyblade to highlight items on the menu. All other navigation possibilities are shown at the bottom of the menu.
Additionally, an item???specific help is displayed on the right side of the menu window.
PENT/ATCA???717 | 87 |
BIOS | Selecting The Boot Device |
|
|
Selecting The Boot Device
There are two possibilities to determine the device from which BIOS attempts to boot:
SVia setup to select a permanent order of boot devices
SVia boot selection menu to select any device for the next boot???up procedure only
Via Setup
1.In the menu line, select [Boot]
A menu similar to the one shown in the following figure appears. Note that the layout may vary slightly with new BIOS versions.a
2.Select [Boot Device Priority]
A menu similar to the one shown in the following figure appears. Note that the layout may vary slightly with new BIOS versions.a
88 | PENT/ATCA???717 |
Selecting The Boot Device | BIOS |
|
|
3.Select the order of the devices from which BIOS attempts to boot the operating system
If BIOS is not successful at booting from one device, it tries to boot from the next device on the list.
If there is more than one device of the same type, e.g. several hard disks, the displayed entry represents the first of these devices as specified in the boot configuration via setup.
The same options determine the order in which POST installs the devices and the operating system assigns device letters. BIOS supports up to two floppy devices to which the operating system may assign, e.g. drive letters A: and B:. The drives C:, D:, E: etc. are reserved for hard???disk drives.
Note:aThere is not always an exact correspondence between the order specified in setup and the letters assigned by the operating system. Many devices, such as legacy option ROMs, support more than one device that can be assigned to several letters. If the CD???ROM drive should have a letter coming before the one assigned to the hard drive, move it in front of the hard drive. The group of bootable add???in cards refers to devices with non???multiboot???compliant BIOS option ROM from which you can boot the operating system.a
Via Boot Selection Menu
To enter the boot menu, press <ESC> during POST. The menu that appears looks similar to the one shown in the following figure. Note that the layout may vary slightly with new BIOS versions.a
PENT/ATCA???717 | 89 |
BIOS | Selecting The Boot Device |
|
|
Figure 33: Boot Menu
Continue with one of the following options:
a)Override existing boot sequence by selecting another boot device from the boot order list or
b)Select [Enter Setup] to enter setup utility or
c)Press <Esc> to return to POST screen and continue with previous boot sequence
Note:aIf the selected device does not load the operating system, BIOS reverts to the previous boot sequence.
90 | PENT/ATCA???717 |
Restoring BIOS Default Settings | BIOS |
|
|
Restoring BIOS Default Settings
The blade provides an on???board configuration switch that allows to clear the blade???s CMOS and thus to restore the BIOS default settings. In order to restore the BIOS default settings using this switch, you have to proceed as follows.aa
Procedure
1.Remove the blade from the system
Seeasection "Installation into Powered Shelves" on pagea54a for the exact procedure
2.Set the on???board switch SW2???3 to ON
Seeasection "Switch Settings" on pagea42a for the exact location of SW2???3
3.Install and power up the blade
Seeasection "Installation into Powered Shelves" on pagea54a for the exact procedure.a Note that the blade will not boot, because the "Clear CMOS RAM" switch SW2???3 is set to ON.a
4.Remove the blade from the system again
Seeasection "Installation into Powered Shelves" on pagea54a for the exact procedure
5.Set switch SW2???3 to OFF
Now the BIOS default settings are restored.a
PENT/ATCA???717 | 91 |
BIOS | Updating BIOS |
|
|
Updating BIOS
For the blade a BIOS upgrade kit is offered. It is available via the former Force Computers S.M.A.R.T. web site or the Motorola web site.aaa
Note:aWhen upgrading the BIOS, all BIOS settings are reset to their default state.a
92 | PENT/ATCA???717 |
BIOS Messages | BIOS |
|
|
BIOS Messages
If your system fails after you made changes in the setup menus, you may be able to correct the problem by entering setup and restoring the original values.a
Message | Explanationa | Corrective Action |
|
|
|
nnnn Cache SRAM Passed | nnnn is amount of system | None |
| cache in KBytes |
|
| successfully tested |
|
CD???ROM Drive Identified | Autotyping identified |
| CD???ROM Drive |
Diskette drive A | Drive A: or B: fails the BIOS |
errorDiskette drive B error | POST disk tests. Drive is |
| selected via setup but |
| either not present or defect. |
Entering SETUP ... | Starting setup program |
Extended RAM Failed at | Extended memory not |
offset: nnnn | working or not configured |
| properly at offset nnnn |
None
Check that drive is defined with proper disk type in setup, that disk drive is attached correctly and that controller is enabled.
None
Check if memory modules are installed correctly. Otherwise contact your local sales representative or FAE for further support.
nnnn Extended RAM Passed | nnnn is amount of RAM in |
| MBytes successfully tested. |
Failing Bits: nnnn | nnnn is a map of the bits at |
| the RAM address (in |
| system, extended or |
| shadow memory) which |
| failed the memory test. |
| Each 1 (one) in the map |
| indicates a failed bit. |
None
Check if memory modules are installed correctly. Otherwise contact your local sales representative or FAE for further support.
Fixed Disk 0 Failure | Fixed disk not working or | Check if fixed disk is |
Fixed Disk 1 Failure | not configured properly | attached properly. Run |
Fixed Disk Controller |
| setup to be sure the |
Failure |
| fixed???disk type is correctly |
|
| identified. |
Fixed Disk 0...3 Identified | Autotyping identified | None |
| specified fixed disk |
|
Incorrect Drive A type ??? | Type of floppy drive not | Check for correct floppy |
run SETUP | correctly identified in setup | drive in setup. |
Incorrect Drive B type ??? |
|
|
run SETUP |
|
|
Keyblade controller error | Keyblade controller failed | Replace keyblade |
| test |
|
PENT/ATCA???717 | 93 |
BIOS | BIOS Messages |
|
|
Message | Explanationa | Corrective Action |
|
|
|
Keyblade error | Keyblade not working | Check for correct keyblade |
|
| connection. |
Keyblade error nnn | BIOS discovered a stuck | Replace keyblade, check for |
| key and displays scan code | stuck keys |
| nn for stuck key |
|
Operating system not found | Operating system cannot |
| be located on either drive |
| A: or drive C:. |
Parity Check 1 nnnn | Parity error found in |
| system bus. BIOS attempts |
| to locate address nnnn and |
| display it on screen. If it |
| cannot locate the address, it |
| displays ????. |
Enter setup and check if fixed disk and drive A: are properly identified.
Check for correct memory module types.
Parity Check 2 nnnn | Parity error found in | Check for correct memory |
| system bus. BIOS attempts | module types. |
| to locate address nnnn and |
|
| display it on the screen. If it |
|
| cannot locate the address, it |
|
| displays ????. |
|
Press <F1> to resume, <F2> | Displayed after any |
to setup | recoverable error message |
Previous boot incomplete ??? | Previous POST did not |
Default configuration used | complete successfully. |
| POST loads default values |
| and offers to run setup. If |
| failure was caused by |
| incorrect values and they |
| are not corrected, the next |
| boot will likely fail. |
Press <F1> to start boot process or <F2> to enter setup and change any settings.
Run setup to restore original configuration. This error is cleared the next time the system is booted.
Real time clock error | Real???time clock fails BIOS |
| test |
Resource allocation | Possible interrupt or |
conflict on motherblade ??? | interface resource conflict. |
Run Configuration Utility |
|
Shadow RAM Failed at | Shadow RAM failed at |
offset: nnnn | offset nnnn of the 64k block |
| at which error was |
| detected. |
nnnn Shadow RAM Passed | nnnn is amount of shadow |
| RAM in KBytes |
| successfully tested |
May require blade repair
Run ISA or EISA Configuration Utility to resolve resource conflict.
Contact your local sales representative or FAE for further support.
None
94 | PENT/ATCA???717 |
BIOS Messages | BIOS |
|
|
Message | Explanationa | Corrective Action |
|
|
|
System battery is dead ??? | The NVRAM (CMOS) clock | Replace battery and run |
Replace and run SETUP | battery indicator shows the | setup to reconfigure |
| battery is dead. | system. |
System BIOS shadowed | System BIOS copied to | None |
| shadow RAM |
|
System cache error ??? Cache | RAM cache failed BIOS | Contact your local sales |
disabled | test. BIOS disabled cache | representative or FAE for |
|
| further support. |
System CMOS checksum bad ??? | System NVRAM (CMOS) | Run setup and reconfigure |
run SETUP | has been corrupted or | system either by getting |
| modified incorrectly, | default values and/or |
| perhaps by an application | making your own |
| program that changes data | selections. |
| stored in NVRAM (CMOS). |
|
System RAM Failed at | System RAM failed at offset |
offset: nnnn | nnnn in the 64k block at |
| which the error was |
| detected. |
nnnn System RAM Passed | nnnn is amount of system |
| RAM in KBytes |
| successfully tested |
Check for correct memory modules. Otherwise contact your local sales representative or FAE for further support.
None
System timer error | Timer test failed | Requires repair of system |
|
| blade |
UMB upper limit segment | Address nnnn of the upper | None |
address: nnnn | limit of upper memory |
|
| blocks indicates released |
|
| segments of BIOS which |
|
| may be reclaimed by a |
|
| virtual memory manager. |
|
Video BIOS shadowed | Video BIOS successfully | None |
| copied to shadow RAM |
|
Invalid System | ??? | Enter setup and use |
Configuration Data ??? run |
| advanced configuration |
configuration utility |
| option to reset |
|
| configuration data (due to |
|
| corrupted ESCD data). |
PENT/ATCA???717 | 95 |
BIOS | BIOS Post Codes |
|
|
BIOS Post Codes
The following table lists BIOS post codes applicable to the used Phoenix 4.0 Release 6.0 BIOS. The BIOS POST codes are stored in the blade???s Port 80 register and can also be obtained by reading an on???board IPMI sensor. For details refer to theaPENT/ATCA*715/717/7105/7107: Control via IPMI Programmer???s Guide which can be downloaded from the Motorola literature catalog.aaa
Table 9: Standard BIOS Post Codes
Post Code | Description |
02 | Verify real mode |
03 | Disable non???maskable interrupt (NMI) |
04 | Get CPU type |
06 | Initialize system hardware |
07 | Disable shadow and execute code from the ROM |
08 | Initialize chipset with initial POST values |
09 | Set IN POST flag |
0A | Initialize CPU registers |
0B | Enable CPU cache |
0C | Initialize caches to initial POST values |
0E | Initialize I/O component |
0F | Initialize the local bus IDE |
10initialize power management
11Load alternate registers with initial POST values
12Restore CPU control word during warm boot
13Initialize PCI bus mastering devices
14Initialize keyboard controller
16BIOS ROM checksum
17Initialize cache before memory autosize
188254 programmable interrupt timer initialization
1A | 8237 DMA controller initialization |
1C | Reset programmable interrupt controller |
20 | Test DRAM refresh |
22 | Test 8742 keyboard controller |
96 | PENT/ATCA???717 |
BIOS Post Codes | BIOS |
|
|
Post Code | Description |
24 | Set ES segment register to 4GB |
26 | Enable gate A20 line |
28Autosize DRAM
29Initialize POST memory manager
2A | Clear 512KB base RAM |
2C | RAM failure on address line xxxx |
2E | RAM failure on data bits xxxx of low byte of memory bus |
2F | Enable cache before system BIOS shadow |
30 | RAM failure on data bits xxxx of high byte of memory bus |
32Test CPU bus clock frequency
33Initialize Phoenix Dispatch Manager
36 | Warm start shut down |
38 | Shadow system BIOS ROM |
3A | Autosize cache |
3C | Advanced configuration of chipset registers |
3D | Load alternate registers with CMOS values |
41Initialize extended memory for RomPilot
42Initialize interrupt vectors
45POST device initialization
46Check ROM copyright notice
47Initialize I20 support
48Check video configuration against CMOS
49Initialize PCI bus and devices
4A | Initialize all video adapters in system |
4B | QuietBoot start (optional) |
4C | Shadow video BIOS ROM |
4E | Display BIOS copyright notice |
4F | Initialize MultiBoot |
50Display CPU type and speed
51Initialize EISA board
PENT/ATCA???717 | 97 |
BIOS | BIOS Post Codes |
|
|
Post Code | Description |
52 | Test keyboard |
54Set key click if enabled
55Enable USB devices
58Test for unexpected interrupts
59Initialize POST display service
5A | Display prompt "Press F2 to enter SETUP" |
5B | Disable CPU cache |
5C | Test RAM between 512KB and 640KB |
60 | Test extended memory |
62 | Test extended memory address lines |
64 | Jump to UserPatch1 |
66Configure advanced cache registers
67Initialize Multi Processor APIC
68Enable external and CPU caches
69Setup system management mode (SMM) area
6A | Display external L2 cache size |
6B | Load custom defaults (optional) |
6C | Display shadow area message |
6E | Display possible high address for UMB recovery |
70 | Display error messages |
72 | Check for configuration errors |
76 | Check for keyboard errors |
7C | Set up hardware interrupt vectors |
7D | Initialize Intelligent System Monitoring |
7E | Initialize coprocessor if present |
80Disable onboard super I/O ports and IRQ???s
81Late POST device initialization
82Detect and install external RS232 ports
83Configure non???MCD IDE controllers
84Detect and install external parallel ports
98 | PENT/ATCA???717 |
BIOS Post Codes | BIOS |
|
|
Post Code Description
85Initialize PC compatible PnP ISA devices
86Reinitialize onboard I/O ports
87Configure motherboard configurable devices (optional)
88Initialize BIOS data area
89Enable non???maskable interrupts (NMI???s)
8A | Initialize extended BIOS data area |
8B | Test and initialize PS/2 mouse |
8C | Initialize floppy controller |
8F | Determine number of ATA drives (optional) |
90Initialize hard disk controllers
91Initialize local bus hard disk controllers
92Jump to UserPatch2
93Build MPTABLE for multi processor boards
95Install CD ROM for boot
96Clear huge ES segment register
97Fixup multi processor table
98Search for option ROM???s
99Check for SMART drive (optional)
9A | Shadow option ROM???s |
9C | Set up power management |
9D | Initialize security engine (optional) |
9E | Enable hardware interrupts |
9F | Determine number of ATA and SCSI drives |
A0 | Set time of day |
A2 | Check key lock |
A4 | Initialize typematic rate |
A8 | Erase F2 prompt |
AA | Scan for F2 key stroke |
AC | Enter setup |
AE | Clear boot flag |
PENT/ATCA???717 | 99 |
BIOS | BIOS Post Codes |
|
|
Post Code | Description |
B0 | Check for errors |
B1 | Inform RomPilot about the end of POST |
B2 | POST done ??? prepare to boot operating system |
B4 | One short beep |
B5 | Terminate QuietBoot (optional) |
B6 | Check password |
B7 | Initialize ACPI BIOS |
B9 | Prepare boot |
BA | Initialize DMI parameters |
BB | Initialize PnP option ROM???s |
BC | Clear parity checkers |
BD | Display multiboot menu |
BE | Clear screen |
BF | Check virus and backup reminders |
C0 | Try to boot with interrupt 19 |
C1 | Initialize POST Error Manager (PEM) |
C2 | Initialize error logging |
C3 | Initialize error display function |
C4 | Initialize system error handler |
C5 | PnP dual CMOS (optional) |
C6 | Initialize notebook docking (optional) |
C7 | Initialize notebook docking late |
C8 | Motorola check (optional) |
C9 | Extended checksum (optional) |
CA | Redirect Int 15h to enable remote keyboard |
CB | Redirect Int 13 to Memory Technologies Devices such as ROM, RAM, |
| PCMCIA, and serial disk |
CC | Redirect Int 10h to enable remote serial video |
CD | Re???map I/O and memory for PCMCIA |
CE | Initialize digitizer and dispaly messagea |
100 | PENT/ATCA???717 |
BIOS Post Codes | BIOS |
|
|
Post Code | Description |
D2 | Unknown interrupt |
aa | The following are for boot block in Flash ROM |
E1 | Initialize the bridgea |
E2 | Initialize the CPUa |
E3 | Initialize the system timera |
E4 | Initialize system I/Oa |
E5 | Check recovery boota |
E6 | Checksum BIOS ROMa |
E7 | Go to BIOSa |
E8 | Set Huge Segmenta |
E9 | Initialize Multi Processora |
EA | Initialize OEM special codea |
EB | Initialize PIC and DMAa |
EC | Initialize Memory typea |
ED | Initialize Memory sizea |
EE | Shadow Boot Blocka |
EF | System memory testa |
F0 | Initialize interrupt vectorsa |
F1 | Initialize Run Time Clocka |
F2 | Initialize videoa |
F3 | Initialize System Management Menagera |
F4 | Output one beepa |
F5 | Clear Huge Segementa |
F6 | Boot to mini DOSa |
F7 | Boot to Full DOSa |
E1 | Initialize the bridgea |
E2 | Initialize the CPUa |
E3 | Initialize the system timera |
E4 | Initialize system I/Oa |
E5 | Check recovery boota |
PENT/ATCA???717 | 101 |
BIOS | BIOS Post Codes |
|
|
Post Code | Description |
E6 | Checksum BIOS ROMa |
E7 | Go to BIOSa |
E8 | Set Huge Segmenta |
E9 | Initialize Multi Processora |
EA | Initialize OEM special codea |
EB | Initialize PIC and DMAa |
EC | Initialize Memory typea |
102 | PENT/ATCA???717 |
5
Devices??? Features and Data Paths
PENT/ATCA???717 | 103 |
104 | PENT/ATCA???717 |
Block Diagram | Devices??? Features and Data Paths |
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Block Diagram
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| RS???232 | RS???232 | 2x USB 2.0 |
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PMC#1 PMC#2 PMC#3 PMC#4 |
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| 32 bit |
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| Boot Flash |
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| 33 MHz |
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| 64 bit | LPC47S422 |
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| 66 MHz |
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| 82546EB/GB |
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| Clock |
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Figure 34: Base Board Block Diagram
PENT/ATCA???717 | 105 |
Devices??? Features and Data Paths | CPU |
|
|
CPU
The used Central Processing Unit (CPU) is a Pentium M processor. The CPU provides 32 kBytes of on???die data and instruction cache as well as two MByte L2 cache.aaa
An on???die temperature sensor measures the CPU temperature. It is connected to the blade???s Intelligent Peripheral Management Controller (IPMC). This way software can monitor the CPU temperature via IPMI.aaa
106 | PENT/ATCA???717 |
Host Bridge | Devices??? Features and Data Paths |
|
|
Host Bridge
The used host bridge is an Intel E7501 Memory Controller Hub (MCH) device. It is part of the Intel Plumas chipset and provides bus control signals, address and data paths for transfers between the CPU front side bus, main memory and the four hub interfaces provided by the host bridge.aaa
Host Interface
The host interface supports a 64???bit wide data bus and a 32???bit wide address bus. The data bus is quadpumped and runs at 100 MHz, resulting in a total bandwidth of 3.2 GB/s. The memory bus is double pumped and supports an address range of up to 4 GByte. Its bandwidth is 200 Mb/s per data line resulting in a total bandwidth of 128 x 200MB/S = 3.2GB/s.a
Memory Interface
The memory interface is a 144???bit wide SDRAM interface supporting 64, 128, 256 and 512 MBit DDR SDRAM technology. The bus speed is 100 MHz running synchronously to the front side bus. Additionally ECC is supported.a
Although theoretically up to 16 GByte are supported by the memory interface, the actual maximum memory size is limited to 4 GByte due to the CPU???s 32???bit address bus.a
Hub Interfaces
The Host Bridge provides the four hub interfaces A, B, C and D.a
Hub interface A is quad pumped, 8???bit wide and runs at 66 MHz. It is connected to the South Bridge and provides a maximum data transfer rate of 266MByte/s. Parity protection is provided for hub interface A. Any parity errors are detected by the host bridge and reported to the South Bridge, which in turn generates an NMI.a
The hub interfaces B, C and D are octal pumped, 16???bit wide and run at 66 MHz. The maximum data transfer rate provided by each hub interface is 1.066 GByte/s.a
ECC protection is provided for hub interfaces B, C and D. Any ECC errors are detected by the host bridge and reported to the South Bridge, which in turn generates an NMI.a
PENT/ATCA???717 | 107 |
Devices??? Features and Data Paths | South Bridge |
|
|
South Bridge
The used South Bridge is an Intel 6300ESB I/O controller hub device. It provides the interface between the Host Bridge and the legacy I/O. Integrated into the South Bridge are:aa
STwo 8237 DMA controllers
SOne 8254 counter timer
SInterrupt controller
SReal???time clock
SWatchdog
The interfaces provided by the South Bridge include:a
SHub interface 1.5
SPCI 2.2 interface
SPCI???X 1.0 interface
STwo parallel ATA interfaces
STwo serial ATA interfaces
STwo serial RS???232 interfaces
SFour USB interfaces
SLPC interface
SSMBus interface
Interrupt Controller
The interrupt controller residing in the South Bridge is 8259A???compliant and runs in PIC mode.a
The interrupts of the four PMC slots are merged and are routed through an FPGA to the interrupt controller where they are mapped to ISA compatible interrupts.a
The interrupt controller is also able to generate CPU Non???Maskable Interrupts (NMIs). Possible sources of NMIs are:aa
SMemory ECC and parity errors
108 | PENT/ATCA???717 |
South Bridge | Devices??? Features and Data Paths |
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SHub interface ECC and parity errors
SPCI bus parity errors
Real???Time Clock
The Real???Time Clock (RTC) resides inside the South Bridge and is sourced by an external 32.768 crystal providing a frequency tolerance of 20 ppm. The RTC provides 242 bytes backed???up CMOS RAM and is fully compliant to:aa
SDS1287
SMC14618
SY2K
SPC87911
Watchdog
The Southbridge incorporates a two???stage watchdog timer. For details refer to the Intel 6300ESB I/O controller documentation. On expiry, the watchdog is able to issue a blade reset.a
PCI???X Interface
The PCI???X interface is 64???bit wide and runs at 66 MHz. It is compliant to the PCI???X 1.0 specification. On the board 3.3V signalling level is used and an 82546EB/GB dual Ethernet controller is connected to the PCI???X interface.a
Parallel ATA Interfaces
The South Bridge provides two separate parallel Advanced Technology Attachment (ATA) interfaces: one primary and one secondary parallel ATA interface. Both interfaces support all Programmed I/O (PIO) modes as well as all Direct Memory Access (DMA) modes up to Ultra ATA/100. The combined parallel and serial ATA interface traffic is indicated by a face plate LED.a
Primary Parallel ATA Interface
The primary parallel ATA interface is connected to an on???board 2.5" hard disk which can be mounted on the blade. The hard disk operates as IDE master.a
PENT/ATCA???717 | 109 |
Devices??? Features and Data Paths | South Bridge |
|
|
Secondary Parallel ATA Interface
The secondary parallel ATA interface is connected to an on???board CompactFlash connector which supports CompactFlash cards of type I and II. An inserted card runs in true IDE mode and is master on the secondary parallel ATA interface.a
USB Interfaces
The South Bridge provides four USB interfaces. Two are routed to the blade???s face plate and two to the rear transition module. All interfaces are compliant to the USB 2.0 standard.a
PCI Interface
The South Bridge provides a 32???bit/33 MHz PCI interface that is compliant to the PCI 2.2 specification. Up to four external PCIbus master devices are supported and a 3.3V signaling level is used.
Serial ATA Interfaces
The South Bridge provides two Serial Advanced Technology Attachment (SATA) interfaces which are compliant to the SATA 1.0 specification and support a data transfer rate of up to 1.5GByte/s. One interface is routed to the Zone 3 connector and is accessable via an installed RTM. One interface is routed to an on???board SATA connector to which a SATA hard disk can be connected.a
Serial RS232 Interfaces
The South Bridge provides two serial full???duplex RS232 interfaces. Supported baud rates are: 600, 1200, 2400, 4800, 9600, 19200, 38400 and 115200 kb/s. Both serial interfaces are +/??? 15 KV ESD protected.
Both interfaces correspond to the blade???s serial interface ports 1 and 3. Serial interface port 1 is routed via a zone 3 connector to an installed RTM. Serial interface port 3 is accessible via an installed CMC module. The BIOS maps the serial interfaces ports to the desired I/O addresses (COM ports) and interrupts.aaaaa
LPC Interface
The South Bridge provides a 4???bit wide Low Pin Count (LPC) interface running at 33 MHz. It has the following devices attached to it:
SSuper I/O
110 | PENT/ATCA???717 |
South Bridge | Devices??? Features and Data Paths |
|
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SBoot flash
SUser flash
SGlue Logic FPGA
SMBus Interface
The following table lists all devices which are connected to the South Bridge via its SMBus interface:aaaa
Device Name | Device Type | SMBus Address |
SPD EEPROM (contains memory | 24C02 | 0xA0 |
configuration data of memory module, |
|
|
used by BIOS) |
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SPD EEPROM (contains memory | 24C02 | 0xA1 |
configuration data of memory module, |
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used by BIOS) |
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Host Bridge | Intel E7501 | 0x60 |
PCI bridge | P64H2 | 0xC0 |
South Bridge | 6300ESB | 0x44 |
PENT/ATCA???717 | 111 |
Devices??? Features and Data Paths | Super I/O |
|
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Super I/O
The used Super I/O is a Standard Microsystems Corporation LPC47S422 device. It provides the following interfaces:aa
STwo serial interfaces
SFloppy disk interface
SKeyboard/Mouse interface
SParallel interface
Serial Interfaces
The Super I/O device provides two serial full???duplex RS232 interfaces. Supported baud rates are: 600, 1200, 2400, 4800, 9600, 19200, 38400 and 115200 kb/s. Both serial interfaces are +/??? 15 KV ESD protected.
Both interfaces correspond to the blade???s serial interface ports 2 and 4. Serial interface port 2 is routed via a zone 3 connector to an installed RTM. Serial interface port 4 is accessible via an installed CMC module. The BIOS maps the serial interface ports to the desired I/O addresses (COM ports) and interrupts.aaaaa
Floppy Disk Interface
The floppy disk interface is unused on the blade.a
Keyboard/Mouse Controller
The Super I/O integrates an 8042H compatible keyboard/mouse controller. The corresponding interfaces are accessible via RTM and CMC debug module.a
Parallel Interface
The parallel interface is unused on this blade.
112 | PENT/ATCA???717 |
Flash Devices | Devices??? Features and Data Paths |
|
|
Flash Devices
The blade provides two redundant boot flash devices: one default boot flash and one backup boot flash. During blade production, both flashes are programmed with identical BIOS images. The presence of two redundant flash devices allows for remotely updating BIOS images from the operating level without interrupting running processes and without being affected by possibly corrupt BIOS images. The backup boot flash, furthermore, can be used to store customized images. Note that in this case the redundant BIOS feature is no longer available.a
Both flash devices are Intel???compatible firmware hubs that are connected to the LPC interface of the South Bridge. Each flash device has a unique four bit LPC device ID. Bit 1 to 3 of the device ID are fixed to 0. Bit 0 is controlled by a boot flash select signal provided by the IPMC in such a way that bit 0 of one flash is set to 0 while bit 0 of the other flash is set to 1 and vice versa. The following figure shows the implementation on hardware???level.a
IPMC | Boot Flash |
| |
| Select Signal |
Default Boot |
Flash |
ID0 |
ID1 |
ID2 |
ID3 |
Backup Boot |
Flash |
ID0 |
ID1 |
ID2 |
ID3 |
Figure 35: Boot Flash LPC Device ID Control
The blade??? s CPU always boots from the boot flash with the LPC device ID 0. Thus the boot flash select signal of the IPMC allows to select the flash device that the CPU is to boot from.a
An IPMI Set System Boot Options command allows to control the boot flash select signal and thus select between the default and backup boot flash as device to boot from. For details refer to theaPENT/ATCA???715/717/7105/7107: Control via IPMI Programmer???s Guidea which can be downloaded from the former Force Computers S.M.A.R.T. server or the Motorola literature catalog.aaaaaaaa
By default, the data/instruction areas of the default and backup boot flash are writable. This is necessary because during booting the BIOS writes some configuration data back to
PENT/ATCA???717 | 113 |
Devices??? Features and Data Paths | Flash Devices |
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|
some reserved spaces in the data/instruction area. The boot block of default and backup boot flash are writeable per default, too. The on???board switches SW4???1, SW4???2 and SW4???4 allow to enable/disable the write???protection of both default and backup boot flash as well as the data/instruction area of the backup boot flash.a
114 | PENT/ATCA???717 |
FPGA | Devices??? Features and Data Paths |
|
|
FPGA
The FPGA implements the following functions:aaaaa
SLPC interface
SIPMC interface
SClock synchronization extensions
SReset controller
SInterrupt routing unit
SMiscellaneous glue logic
SEthernet switch interface
The FPGA loads its configuration stream from one of two EEPROMs which are connected to the FPGA. One EEPROM serves as default, the second as backup EEPROM. The IPMC controls which EEPROM the configuration stream is loaded from. After IPMC startup the FPGA loads its configuration stream from the default EEPROM. An IPMI System Boot Options command allows to select between default and backup EEPROM. For details about switching between default and backup FPGA refer to theaPENT/ATCA???715/717/7105/7107: Control via IPMI Programmer???s Guidea which can be downloaded from the Motorola literature site.aaa
LPC Interface
The LPC interface is compliant to the Intel LPC specification 1.1 and connects the FPGA to the South Bridge.a
IPMC Interface
The FPGA is connected to the on???board IPMC and implements the following IPMC related features:
STwo Block Transfer interfaces
SPort 80 register
SIPMC extensions
Block Transfer Interfaces
Two Block Transfer interfaces (BT) reside inside the FPGA. Each provides one control and status register, two 64???byte FIFOs and an interrupt mask register. Both BT interfaces are
PENT/ATCA???717 | 115 |
Devices??? Features and Data Paths | FPGA |
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compliant to the IPMI specification V1.5 Rev. 1.0 and share one Interrupt Source register. The first BT interface is used as the only System Interface and uses IPMI channel 0x0F. The second BT interface uses IPMI channel 0x06.aaa
Port 80 Register
The FPGA provides an 8???bit wide register to store POST codes. The register is located at I/O address 8016.. It is only readable for the IPMC and read???writeable for the host. The IPMC polls this register to monitor the boot up sequence of the board. The content of the port 80 register can also be obtained and read via IPMI.a
IPMC Extensions
The FPGA implements three registers which are only visible for the IPMC. These registers reflect the following:
SCPU core voltage identifier
SFrame signal on LPC bus
SSystem and parity errors on PCI buses
SEnabling/disabling of backplane signals used for electronic keying
SAlert signals
Clock Synchronization Extensions
The FPGA contains extensions which are related to the AdvancedTCA clock synchronization feature. These extensions include:
SRegisters accessible via host and IPMC for controlling and monitoring clock synchronization
SSPI interface for controlling DPLL device
SProgrammable clock dividera
For further details refer toasection "Clock Synchronization Interface" on pagea124a andasection "Clock Synchronization Interface Registers" on pagea144.
Reset Controller
The FPGA contains part of the blade???s reset logic. Furthermore it provides two registers which allow to determine the source of the last reset issued and to mask resets.a
Reset Types
Two different types of resets are possible: hard resets and soft resets.a
116 | PENT/ATCA???717 |
FPGA | Devices??? Features and Data Paths |
|
|
During a hard reset all internal registers, state machines and caches of the CPU are reset. Furthermore all on???board PCI devices as well as the host bridge are reset.a
During a soft reset the CPU is reset, with the exception of the internal caches and state machinesaaa
Reset Sources
The following table lists all possible reset sources and the corresponding reset types.aaa
Table 10: Reset Sources
Reset Source | Hard Reset | Soft Reset |
Software reset | x | x |
Watchdog inside Southbridge | x |
|
Power???up reset | x |
|
Face plate reset key | x |
|
RTM reset | x |
|
IPMC reset | x |
|
Keyboard reset |
| x |
Interrupt Routing Unit
The FPGA is used for fixed interrupt routing on the blade.a
All interrupts from PCI devices are routed via the FPGA to the South Bridge. All other interrupts are routed to the Super I/O device from where they are routed to the South Bridge.a
Miscellaneous Glue Logic
The miscellaneous glue logic includes:
SSerial interface
SReset mask and source register
SFlash control register
SPMC status register
SShut???down register
PENT/ATCA???717 | 117 |
Devices??? Features and Data Paths | FPGA |
|
|
SLEDs
SVersion register
Serial Interface
The FPGA provides routing options of one of the two serial interfaces provided by the Southbridge. This feature is intended for Motorola???internal purposes and should be ignored. .a
Reset Mask and Source Register
The FPGA provides two registers which allow to obtain the last reset source and to mask resets. Seeasection "Reset Registers" on pagea139.a
Flash Control Register
The FPGA provides one register which allows to monitor the boot and user flash write???protection status as well as to control the write???protection of the boot flash boot block. Seeasection "Flash Control and Status Register" on pagea141
PMC Status Register
The FPGA provides one register which allows to monitor the status of the four PMC sites. Seeasection "PMC Status Register" on pagea143
Shut???Down Register
The FPGA provides one register which allows to control the blades??? FRU???EN signal. Seeasection "Shut Down Register" on pagea143
LEDs
The FPGA provides a register to control the HDD LED available at the face plate. This LED indicates the combined parallel and serial ATA activity or is operated in user LED mode. Seeasection "LED Control Register" on pagea142.a
Version Register
This register allows to obtain the current FPGA version. Seeasection "Version Register" on pagea147.a
118 | PENT/ATCA???717 |
Intelligent Platform Management Controller | Devices??? Features and Data Paths |
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Intelligent Platform Management Controller
The blade provides an Intelligent Platform Management Controller (IPMC) unit based an the 8???bit Atmel ATmega AVR microcontrollers. The IPMC is fully compliant to the IPMI V1.5 standard and provides the following interfaces:aaa
SIPMB0A and IPMB0B available via the backplane
SIPMB???L connected to rear transition modulea
SI2C interfaces connected to on???board PMCs slots and sensors
SAnalog???to???Digital Conversion (ADC)interfaces connected to on???board sensors
SDigital I/O interfaces connected to on???board sensors
One of the main tasks of the IPMC is to control the power up and power down of the blade. For this purpose the IPMC is connected to the on???board power supply module via control and status lines. Various on???board IPMI sensors provide detailed information on the current power status of the blade to any interested party connected to the IPMI network.a
The following figure gives an overview of the IPMI structure used on???board.aaa
Blade |
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PMC 1 | Host |
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IDROM |
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PMC 2 |
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I2C MUX |
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PMC 3 |
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PMC 4 |
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Power Supply | Control and |
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Figure 36: IPMI Structure
For details about accessing the IPMC via IPMI commands as well as Sensor Data Records (SDRs) and Field Replacable Unit (FRU) information provided by the blade, refer to the "PENT/ATCA???715/717/7105/7107 Control via IPMI Programmer???s Guide" which can be downloaded from the Motorola literature catalog.a
PENT/ATCA???717 | 119 |
Devices??? Features and Data Paths | Intelligent Platform Management Controller |
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Sensors
The blade provides various sensors which are accessible via IPMI. Some of these sensors measure on???board temperatures. Their names and locations are shown in the following figure.aaa
Memory Temp
CPU Board Temp (other side of PCB)
CPU Die Temp
12V DCDC Temp
Ambient Temp
Figure 37: IPMI Temperature Sensors
Other sensors available on???board include voltage sensors and sensors which provide particular status information. A summary of all sensors is given in the following table.a
120 | PENT/ATCA???717 |
Intelligent Platform Management Controller | Devices??? Features and Data Paths |
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Table 11: On???board Sensors Accessible via IPMI
Sensor Name | Type of | What Does It Measure? | Sensor Type | Availability |
| Measurement |
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Ambient Temp | Temperature | Ambient temperature near Compact | Analog | Always |
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Memory Temp | Temperature | Temperature of on???board memorya | Analog | Always |
CPU Board Temp | Temperature | Board temperature near the CPU | Analog | Always |
CPU Die Temp | Temperature | CPU temperature | Analog | Always |
Voltage +1.8V | Voltage | +1.8V voltage level | Analog | While |
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Voltage +1.5V | Voltage | +1.5V voltage level | Analog | While |
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Voltage +3.3V | Voltage | +3.3V voltage level | Analog | While |
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Voltage +5V | Voltage | +5V voltage level | Analog | While |
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Voltage +12V | Voltage | +1.2V voltage level | Analog | While |
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Voltage +1.05V | Voltage | +1.05V voltage level | Analog | While |
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Voltage +1.25V | Voltage | +1.25V voltage level | Analog | While |
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Mem Volt +1.2V | Voltage | +1.2V voltage level of the memory | Analog | While |
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PENT/ATCA???717 | 121 |
Devices??? Features and Data Paths | Intelligent Platform Management Controller |
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Sensor Name | Type of | What Does It Measure? | Sensor Type | Availability |
| Measurement |
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Mem Volt +2.5V | Voltage | +2.5V voltage level of the memory | Analog | While |
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Sw Volt +1.2V | Voltage | +1.2V voltage level of Ethernet switch | Analog | While |
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CPU THERM TRIP | Temperature | CPU has stopped execution because | Discrete | While |
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| Payload |
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ICH PROC HOT | Temperature | CPU temperature has reached | Discrete | While |
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FPGA | Status | FPGA programming status | Discrete | While |
PROGRAMMED |
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Sw Volt +2.5V | Voltage | +2.5V voltage level of Ethernet switch | Analog | While |
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CPU CORE Volt | Voltage | CPU core voltage level | Discrete | While |
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715 Watchdog | Status | Watchdog status | Discrete | Always |
715 RTM HotSwap | Status | RTM presence | Discrete | Always |
715 IPMB0 State | IPMB status | ATCA IPMB0 | Discrete | Always |
715 POST Code | Status | POST status | Discrete | While |
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PCI BUS ERR | Status | PCI bus status | Discrete | While |
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122 | PENT/ATCA???717 |
Intelligent Platform Management Controller | Devices??? Features and Data Paths |
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Sensor Name | Type of | What Does It Measure? | Sensor Type | Availability |
| Measurement |
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715 FPGA Version | Version | FPGA version of ATCA???715 | Discrete | Always |
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FW Revision ISC0 | Revision | Revision of the Intelligent Slave | Discrete | Always |
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FW Revision ISC1 | Revision | Revision of the Intelligent Slave | Discrete | Always |
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715 IPMC | Status | IPMC status | Discrete | Always |
SYS FW | Status | BIOS boot progress | Discrete | While |
PROGRESS |
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Boot Error | Status | BOOT error | Discrete | While |
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Supply Current | Current | 12V payload current | Analog | While |
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12V DCDC Temp | Temperature | Temperature at 12V DC/DC converter | Analog | While |
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For further details refer to the "PENT/ATCA???715/717/7105/7107 Control via IPMI Programmer???s Guide" which can be downloaded from the Motorola literature catalog.
I2C Addresses
The blade provides one IDROM which is attached to the IPMC via an I2C bus. The I2C address of the IDROM is 0xA0.a
PENT/ATCA???717 | 123 |
Devices??? Features and Data Paths | Clock Synchronization Interface |
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Clock Synchronization Interface
AdvancedTCA systems provide a telecom clock synchronization interface which allows to synchronize elements within a telecommunication network. The telecom clock synchronization interface consists of three redundant clock buses (CLK1, CLK2 and CLK3) which are available at the system backplane. Each clock bus is implemented as a differential pair of MDS/LDS signals which connects to each system slot.aaa
In compliance with the AdvancedTCA PICMG 3.0 specification, CLK1 and CLK2 are used as system clocks and CLK3 is used as reference clock.a
The blade provides a clock synchronization building block which allows to synchronize the four on???board PMC modules to the system clock and to derive a reference clock. The main components of the clock synchronization building block as well as the main signal paths are shown in the following figure.aaa
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PMC Slots |
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CLK_0 |
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Buffer |
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SYNC_1 | Clock |
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Figure 38: Clock Synchronization Building Block |
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The key component of the clock synchronization building block is the DPLL device ACS8525 from Semtech. Its main features include:
SSoftware programmable output clock synthesis (CLK_0, 1, 2, 3)
124 | PENT/ATCA???717 |
Clock Synchronization Interface | Devices??? Features and Data Paths |
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S8 kHz frame clock/pulse with programmable pulse width and polarity (SYNC_0,1,2,3))
SAutomatic hit???less switch???over if one system clock fails
SActivity monitor for system clocks
SPhase build???out for output clock phase continuity during switch???over
SMeets jitter requirements up to OC???3 line rates
SProgrammable reference clock divider
The DPLL is clocked by an external oscillator running at 12.8 MHz. Two clock buffers provide a separate clock and synchronization signal for each of the four on???board PMC sites. The FPGA contains extensions which are related to the clock synchronization building block. Some of these extensions include registers that are accessible via the host and which allow to control and monitor the functionality of the clock synchronization building block. For details refer toasection "Clock Synchronization Interface Registers" on pagea144.a
PENT/ATCA???717 | 125 |
Devices??? Features and Data Paths | Power Supply Module |
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Power Supply Module
The blade is fed via two redundant ???48V inputs. Both are converted via a DC/DC converter to an intermediate voltage of +12V. This voltage, in turn, is converted via further DC/DC converters to on???board voltages which are used by the on???board devices. A ???48V/+3.3V DC/DC converter converts the ???48V input voltage to +3.3V which is used to feed the IPMC and power???up logic.
The blade???s power up and power down cycles are under full control of the IPMC. It controls both the ???48V/+12V DC/DC converter as well as power???up logic which controls the remaining on???board DC/DC converters. If the IPMC detects a failure on any of the local on???board voltages, it shuts off the entire blade power.aaa
The blade???s power supply structure is shown in the following figure.a
???48V_A
???48V_B
Return_A
Return_B
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???48V_A
???48V_B
Return_A
Return_B
DC +3.3V
DC
Power Good
Figure 39: Blade Power Supply Structure
126 | PENT/ATCA???717 |
PCI Bridge P64H2 | Devices??? Features and Data Paths |
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PCI Bridge P64H2
The Intel P64H2 PCI bridge provides two PCI/PCI???X interfaces. Each interface is connected to two PMC sites. The P64H2 device supports peer???to???peer communication between the two PCI/PCI???X interfaces. This way no host intervention is required when PMC sites connected to different PCI/PCI???X interfaces communicate with each other. In PCI mode up to 533 MHz/s transfer rate is possible, in PCI???X up to 800 MByte/s.a
PENT/ATCA???717 | 127 |
Devices??? Features and Data Paths | Switching Unit |
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Switching Unit
The on???board switching unit is based on the Marvell 98DX160 Ethernet layer 2+ switch and provides switching functionality between on???board Ethernet ports, PMC sites and the backplane interfaces. It provides 16 Ethernet switching ports as well as one Serial Management interface (SMI) and one additional Ethernet port for configuration.aaa
Features
Important features of the switching unit are:aaa
S2 MByte internal memory
SHost management interface
SSupport for 1000 MII/GMII/RGMII and 1000Base???X
SManual and auto???negotiation
SSupport for jumbo frame length of 10KByte packets
SOn???chip 4K MAC address table
S4K VLANs with 256 active VLANs
SFlexible VLAN assignment for protocol??? port??? and tag???based VLANs
Management Interface
The switching unit provides two management interfaces towards the host: one slave Serial Management Interface (SMI) and one CPU Ethernet port. The SMI interface is accessible via FPGA registers and supports read and write accesses to address mapped entities. The CPU Ethernet port is constituted by an Intel 82540EM GBit Ethernet controller which is connected to the PCI interface of the blade???s South Bridge.aaa
Routing Options
The blade is designed to support dual???dual star backplanes. However, the currently available blade variants support only dual star backplanes. Ask your local Motorola representative for more information on available blade variants and switch options.a
Starting with blade revision 1.2, the blade provides support for PICMG 3.1 Option 2. This is achieved by configuring two fabric interface ports as one 2 GBit Ethernet trunc. Details are given below.a
128 | PENT/ATCA???717 |
Switching Unit | Devices??? Features and Data Paths |
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At blade start???up the Ethernet switch reads a serial PROM which contains switch configuration information such as predefined Virtual Local Area Networks (VLANs).a
The following table shows how the Ethernet interfaces are distributed across the 16 Ethernet switch ports.a
Table 12: Ethernet Switching Unit ???Ethernet Port Distribution
Interfaces | Number of Ethernet Ports |
PMC sites | 2 x 1 and 2 x 2 |
Host Ethernet | 2 x 1 |
Base interface | 2 x 1 |
Fabric interface | 2 x 1 and 2 x 2 |
Update channel interface | ??? |
Total | 16 |
Four VLANs are predefined. Each backplane Ethernet interface is assigned to one separate VLAN. On???board Ethernet interfaces, however, belong to more than one VLAN.a
The fabric interfaces are attached to tagged VLANs, and the base interfaces to untagged VLANs.a
The following figure illustrates the VLAN configuration.a
PENT/ATCA???717 | 129 |
Devices??? Features and Data Paths | Switching Unit |
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PMC 1A n/a |
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| 10 | Fabric channel 3 | |||
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PMC 1B | 0 |
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| 11 Fabric channel 4 | |
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PMC 2A | 5 |
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PMC 2B | 1 |
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PMC 3A | 6 |
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PMC 3B | 2 |
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PMC 4A | n/a |
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| 12 | Base channel 1 |
PMC 4B | 3 |
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| 13 | Base channel 2 | |||||||||||||||||||||||||||||||||||||||
Tagged VLAN
Untagged VLAN
Figure 40: VLAN Configuration
The following table summarizes the Ethernet switch configuration by listing Ethernet interfaces, port numbers, VLAN IDs and Ethernet types.a
130 | PENT/ATCA???717 |
Switching Unit | Devices??? Features and Data Paths |
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|
Note:aOnly port 0 and 1 of the fabric channels are used.a
Table 13: Ethernet Switching Unit ??? Port Assignment
Switching Unit | Destination | Interface Type | ID of Untagged | ID of Tagged |
Port Number |
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| VLAN | VLAN |
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0 | PMC 1B | 1000BaseT | 3 | 5 |
1 | PMC 2B | 1000BaseT | 3 | 5 |
2 | PMC 3B | 1000BaseT | 3 | 5 |
3 | PMC 4B | 1000BaseT | 3 | 5 |
4 | Fabric channel 1T | 1000BaseBX | ??? | 4 |
5 | PMC 2A | 1000BaseT | 2 | 4 |
6 | PMC 3A | 1000BaseT | 2 | 4 |
7 | Fabric channel 2T | 1000BaseBX | ??? | 5 |
8 | Fabric channel 1 | 1000BaseBX | ??? | 4 |
9 | Fabric channel 2 | 1000BaseBX | ??? | 5 |
10 | Fabric channel 3 | 1000BaseBX | ??? | ??? |
11 | Fabric channel 4 | 1000BaseBX | ??? | ??? |
12 | Base channel 1 | 1000BaseT | 2 | ??? |
13 | Base channel 2 | 1000BaseT | 3 | ??? |
14 | Primary base | 1000BaseBX | 2 | 4 |
| board/82546EB/G |
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| B Ethernet |
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| controller |
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15 | Secondary base | 1000BaseBX | 3 | 5 |
| board/82546EB/G |
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| B Ethernet |
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| controller |
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PENT/ATCA???717 | 131 |
6
Maps and Registers
132 | PENT/ATCA???717 |
I/O and Memory Maps | Maps and Registers |
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I/O and Memory Maps
The following table shows the blade???s main address map.a
Table 14: Memory Address Map
Base Address | Size | Device |
FFF0.000016 | 1 MByte | Boot Flash |
FFE0.000016 | 1 MByte | User Flasha |
0000.000016 | Up to 4GByte | Main Memory |
The I/O addresses of all on???board functional units are listed below.aaa
Table 15: I/O Address Map
Device | Base Address |
DMA Controller #1 | 00016...01F16a and 08016...09F16 |
Interrupt Controller #1 | 02016...03F16 |
Timer | 04016...05F16 |
Keyboard/Mouse | 06016...06F16 |
Real???Time Clock | 07016...07F16 |
Port 80 | 08016 |
Interrupt Controller 2 | 0A016...0BF16 |
DMA Controller 2 | 0C016...0DF16 |
IPMI Block Transfer Interface 1 | 0E416a ??? 0E616 |
IPMI Block Transfer Interface 2 | 0E816a ??? 0EA16 |
Glue Logic FPGA Index Register | 10016a ??? 10116 |
Ethernet Switch Management Interface | 15016...15516 |
Secondary Parallel ATA | 17016...17816a or 37616, 37716 |
Primary Parallel ATA | 1F016...1F816a or 3F616, 3F716 |
Floppy Disk | 3F016...3F516 |
COM 1 | 2F816...2FF16a or 2E816...2EF16a or |
| 3E816...3EF16a or 3F816...3FF16 |
COM 2 | 2F816...2FF16a or 2E816...2EF16a or |
| 3E816...3EF16a or 3F816...3FF16 |
PENT/ATCA???717 | 133 |
Maps and Registers | I/O and Memory Maps |
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Device | Base Address |
| |
COM 3 | 2F816... | 2FF16a or 2E816... | 2EF16a or |
| 3E816... | 3EF16a or 3F816... | 3FF16 |
COM 4 | 2F816... | 2FF16a or 2E816... | 2EF16a or |
| 3E816... | 3EF16a or 3F816... | 3FF16 |
134 | PENT/ATCA???717 |
Hardware Interrupts | Maps and Registers |
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|
Hardware Interrupts
The following table lists the blade???s hardware interrupts and the corresponding interrupt sources.a
Note:aAll interrupts marked with an asterisk (*) must not be used for PCI interrupt routing.
Table 16: Hardware Interrupts
Interrupt | Interrupt Source |
IRQ0* | Timer |
IRQ1* | Keyboard |
IRQ2* | Input of interrupt controller #2 |
IRQ3 | COM 2 or COM 4 |
IRQ4 | COM 1 |
IRQ5 | COM 3 |
IRQ6 | IPMI Block Transfer interface |
IRQ7 | PCI |
IRQ8* | Real time clock |
IRQ9 | PCI |
IRQ10 | PCI |
IRQ11 | PCI |
IRQ12 | Reserved or Mouse (PS/2) |
IRQ13* | Coprocessor |
IRQ14 | Reserved or primary parallel ATA |
IRQ15 | Reserved or secondary parallel ATA |
PENT/ATCA???717 | 135 |
Maps and Registers | PCI Devices |
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PCI Devices
The following figure shows the on???board PCI device structure.aaa
PCI I/O Bridge | Bus #5 | PMC#1 | Dev. No. = 3 |
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Dev. No. = 31 |
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| PCI |
Bus #3 | PCI |
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Host Bridge
PCI
PCI
| PMC#2 | Dev. No. = 1 |
Bus #4 | PMC#3 | Dev. No. = 2 |
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Dev. No. = 2 |
| Dev. No. = 29 |
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| PCI |
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| Dev. No. = 4 |
| PCI |
| South Bridge |
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| PMC#4 | |||
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| Dev. No. = 30 |
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| Intel |
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| PCI |
| Bus #2 82540EM |
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| Bus #0 | PCI |
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| ETH#2 | Dev. No. = 4 | |
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| 82546EB/GB |
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Figure 41: PCI Structure
The following table lists the PCI devices interrupt signals which are routed to the South Bridge. BIOS allows to map these signals to standard ISA interrupts.aaa
Table 17: PCI Device Interrupts
PCI Device | PCI IRQ | Device | IDSEL | PCI Bus |
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| No. |
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|
PMC 1 | PIRQA_N|PIRQB_N|PIRQC_N|PIRQD_N | 3 | 19 | 5 |
PMC 2 | PIRQA_N|PIRQB_N|PIRQC_N|PIRQD_N | 1 | 17 | 5 |
PMC 3 | PIRQA_N|PIRQB_N|PIRQC_N|PIRQD_N | 2 | 18 | 4 |
PMC 4 | PIRQA_N|PIRQB_N|PIRQC_N|PIRQD_N | 4 | 20 | 4 |
ETH 2 | PIRQC_N | 4 | 20 | 2 |
ETH 0|1 | PIRQA_N|PIRQB_N | 4 | 20 | 1 |
136 | PENT/ATCA???717 |
FPGA Registers | Maps and Registers |
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|
FPGA Registers
The FPGA provides various control and status registers. Some of these registers are accessible from the CPU host via the LPC bus, some by the IPMC, others by both. In the following all registers will be described which are accessible from the CPU. These registers are listed in the following table.aaa
Table 18: Registers Accessible from CPU via LPC Bus
Address Range | Data | Description |
| Width |
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|
0xE4 ??? 0xE6 | 8 bit | IPMI Block Transfer Interface 0 |
0xE8 ??? 0xEA | 8 bit | IPMI Block Transfer Interface 1 |
0x80 | 8 bit | Port 80 |
0x100 | 8 bit | Index Address Register (used for accessing further FPGA |
|
| registers)a |
0x101 | 8 bit | Index Data Register (used for accessing further FPGA registers) |
0x150 ??? 0x155 | 8 bit | Ethernet Switch Management Interface |
The FPGA provides further registers. In order to access them, first write the index address corresponding to the register to the Index Address Register, and then perform either a read or write access on the Index Data Register. All registers that can be accessed this way are listed in the following table.a
Table 19: Index Addresses of Registers Accessible from CPU via LPC Bus
Index Address | Data | Description |
| Width |
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0x00 | 8 bit | Reset Source Register |
0x01 | 8 bit | Reset Mask Register |
0x02 | 8 bit | Flash Control and Status Register |
0x03 | 8 bit | LED Control Register |
0x04 | 8 bit | PMC Status Register |
0x05 | 8 bit | Shut Down Register |
0x30 ??? 0x3F | 8 bit | Clock synchronization interface |
0x40 | 8 bit | Serial PROM Update Register |
0x41 | 8 bit | Access Control Register |
0xFF | 8 bit | Version Register |
All other | 8 bit | Reserved |
PENT/ATCA???717 | 137 |
Maps and Registers | FPGA Registers |
|
|
IPMI Block Transfer Interface Registers
The host can access the IPMC via the two Block Transfer (BT) Interfaces 0 and1. Both are fully compliant to the IPMI specification V1.5. Each BT interface provides the following registers.aa
Table 20: IPMI Block Transfer Interface Registers
Address Offset | Data Width | Description |
0x00 | 8 bit | Control and status register |
0x01 | 8 bit | Buffer Register |
0x02 | 8 bit | Interrupt mask register |
Control and Status Register
This register is used by the IPMC and the host CPU for various control functions.a
Buffer Register
This register provides access to an IPMC???to???Host and Host???to???IPMC buffer. The buffer has a size of 64 bytes and contains command streams between host and IPMC.a
Interrupt Mask Register
The host uses this register to mask interrupts generated by the IPMC.a
Port 80 Register
This read???only 8???bit wide register, which is located at the I/O address 8016astores the results obtained from the POST (Power On Self Test).a
Ethernet Switch Management Registers
The following registers consitute an Ethernet management interface accessible by the host. The registers allow to configure and control the operation of the on???board Ethernet switch. The Ethernet management interface conforms to the IEEE 802.3 management draft standard. The base address of these registers is 0x150.aaa
Table 21: Ethernet Switch Management Registers
Address Offset | Register |
0016 | Command and Status Register |
0116 | PHY address register |
138 | PENT/ATCA???717 |
FPGA Registers | Maps and Registers |
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|
Address Offset | Register |
0216 | Lower data register |
0316 | Upper data register |
0416 | Clock divider register |
0516 | I2C Control and Status Register |
Command and Status Register
This register controls the transfer of configuration data to and from the Ethernet switch.a
Table 22: Command and Status Register
Bit | Description | Access |
4..0 | PHY internal register address | r/w |
5 | Command flag | r/w |
| 0: Perform write access |
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| 1: Perform read access |
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6 | Read Error Flag | r/wc |
| 0: PHY responds to read access |
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| 1: Error occurred |
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7 | Interface Status | r |
| 0: Ready |
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1: Busy (wait until ready is indicated before initiating new access)
Data Registers
These registers contain the data that is read from or sent to the Ethernet switch.
Clock Divider Register
This register allows to program the frequency of the Ethernet Switch Management clock.a
I2C Control and Status Register
The Ethernet switch obtains its configuration data from a PROM device that is connected to it. This register allows to access this PROM and is used for PROM updates.a
Reset Registers
The blade provides two registers which are related to blade resets:aaaaa
SReset source register (index address 0x00)
PENT/ATCA???717 | 139 |
Maps and Registers | FPGA Registers |
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|
SReset mask register (index address 0x01)
The reset source register stores the source of the most recent reset. A write access clears this register.Each bit is associated with one reset source. If the bit is set to one, the corresponding reset has occurred. After a reset has occurred, this register should be cleared. Otherwise, after the next reset of another source, more than one bit is set and you may not be able to determine the most recent reset source.a
Table 23: Reset Source Register
Bit | Signal | Description | Default | Access |
0 | PWR_ON | 0: No reset | 12 | r/w |
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| 1: Power???on reset |
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1 | WDG_RES | 0: No reset | 02 | r/w |
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| 1: Watchdog reset |
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2 | PB_RES | 0: No reset | 02 | r/w |
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| 1: Face plate push button reset |
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3 | PMC_RST | 0: No reset | 02 | r/w |
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| 1: PMC slots reset |
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4 | RTM_RES | 0: No reset | 02 | r/w |
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| 1: RTM reset |
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5 | CPU_RST | 0: No reset | 02 | r/w |
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| 1: CPU reset issued by Host |
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| Bridge |
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6 | PCI_RES | 0: No reset | 02 | r/w |
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| 1: Legacy PCI bus reset |
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7 | IPMI_RES | 0: No reset | 02 | r/w |
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| 1: IPMC building block reset |
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|
The reset mask register allows to enable/disable particular resets. If a bit is set, the corresponding reset is enabled, otherwise it is disabled.a
Note:aIPMC, legacy PCI and power???on reset cannot be enabled/disabled via this register.a
Table 24: Reset Mask Register
Bit | Signal | Description | Default | Access |
0 | ??? | Reserved | 02 | r |
1 | WDG_RES | Watchdog reset | 12 | r/w |
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| 0: Disabled |
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| 1: Enabled |
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140 | PENT/ATCA???717 |
FPGA Registers | Maps and Registers |
|
|
Bit | Signal | Description | Default | Access |
2 | PB_RES | Face plate push button Reset | 12 | r/w |
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| 0: Disabled |
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| 1: Enabled |
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3 | DB_RES | ITP debug reset | 12 | r/w |
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| 0: Disabled |
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|
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| 1: Enabled |
|
|
4 | RTM_RES | RTM reset | 12 | r/w |
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| 0: Disabled |
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| 1: Enabled |
|
|
5 | PMC_RSTa | PMC slots reset | 12 | r/w |
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| 0 : Disabled |
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| 1: Enabled |
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|
6 | ??? | Reserved | 02 | r |
7 | ??? | Reserved | 02 | r |
Flash Control and Status Register
This register, which is accessible via the index address 0x02, indicates the status of the default and backup boot flash regarding write???protection, crisis recovery and booting. Additionally, this register allows to set the write???protection of the default boot flash data/instruction area.aa
Table 25: Miscellaneous Switch Status Register
Bit | Description | Default | Access |
0 | Default boot flash boot block write | 02 | r |
| protection |
|
|
| 0: Write???protected |
|
|
| 1: Write???enabled |
|
|
1 | Default boot flash data/instruction block | 12 | r/w |
| write protection (provided that bit 4 is set, |
|
|
| software can set this status) |
|
|
| 0: Write???protected |
|
|
| 1: Write???enabled |
|
|
2 | Backup boot flash boot block write | 02 | r |
| protection |
|
|
| 0: Write???protected |
|
|
| 1: Write???enabled |
|
|
3 | Backup boot flash data/instruction block | 02 | r |
| write protection |
|
|
0: | Write???protected |
1: | Write???enabled |
PENT/ATCA???717 | 141 |
Maps and Registers | FPGA Registers |
|
|
Bit | Description | Default | Access |
4 | Select status of default and backup boot | 02 | r |
| flash write protection |
|
|
| 0: Write???protection determined by |
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| on???board switches |
|
|
| 1: Write???protection determined by this |
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| register |
|
|
6:5 | Indicates flash that is booted from | 002 | r |
| 002: Default boot flash |
|
|
| 012: Backup boot flash |
|
|
7 | Crisis recovery (indicates status of crisis | 12 | r |
| recovery switch) |
|
|
0: Crisis recovery
1: Normal operation
LED Control Register
This register, which is accessible via the index address 0x03, allows to control the bicolor face plate HDD LED. This LED can be operated in parallel/serial ATA status indication mode and user mode. Toggling between both modes is possible via this register.a
In parallel/serial ATA status indication mode the LED shines GREEN and indicates the combined activitiy of all serial and parallel ATA interfaces. In user mode, the LED can be controlled to be red, green and OFF.aaa
Table 26: LED Control Register
Bit | Description | Default | Access |
1..0 | Controls LED in user mode | 012 | r/w |
| 002: OFF |
|
|
| 012: Red |
|
|
| 102: Green |
|
|
| 112: Reserved |
|
|
2 | Toggles between user mode and parallel/serial ATA | 02 | r/w |
| status indication mode |
|
|
| 0: User mode |
|
|
| 1: Parallel/serial ATA status indication mode |
|
|
3 | General purpose output on connector P30/pin A3 | 12 | r/w |
| 0: O/P is low |
|
|
| 1: O/P is open |
|
|
6 | Serial COM interface swapping | 12 | r |
| 02: No swapping |
|
|
| 12: COM 1 is swapped with COM3, and COM 2 is |
|
|
| swapped with COM 4 |
|
|
7..5 | Reserved | 0002 | r |
142 | PENT/ATCA???717 |
FPGA Registers | Maps and Registers |
|
|
PMC Status Register
This register, which is accessible via the index address 0x04, indicates the current status of all four on???board PMC sites.aaa
Table 27: PMC Status Register
Bit | Description | Default | Access |
0 | PMC slot 1 | ??? | r |
| 0: Empty |
|
|
| 1: Populated |
|
|
1 | PMC slot 2 | ??? | r |
| 0: Empty |
|
|
| 1: Populated |
|
|
2 | PMC slot 3 | ??? | r |
| 0: Empty |
|
|
| 1: Populated |
|
|
3 | PMC slot 4 | ??? | r |
| 0: Empty |
|
|
| 1: Populated |
|
|
4 | Routing of PCIX_PMC_INT_N interrupts | 02 | r/w |
| 02: Interrupts are routed to FPGA output |
|
|
| signals PIRQA???D_N |
|
|
| 12: Interrupts are routed to FPGA output |
|
|
| signals PXIRQ_N0???3 |
|
|
6:5 | Reserved | 0002 | r |
7 | Indicates if PMC slots are ready for PCI | aa | r |
| enumeration |
|
|
0: Not ready
1: Ready
Shut Down Register
This write???only register, which is accessible via the index address 0x05, allows to pull down the FRU_EN signal to GND and thus initiate a blade power???down.a
This register was introduced because the FRU_EN signal is under normal operation controlled by the IPMC. If the IPMC however is is not operating anymore, for example during a firmware upgrade, the FRU_EN signal is released and remains in the state it previously had been in. In this case it may be necessary to explicitly pull down FRU_EN via this register.a
Bit | Description | Access |
7:0 | Pull down FRU_EN signal | w |
| 001111002: Pull down FRU_EN |
|
PENT/ATCA???717 | 143 |
Maps and Registers | FPGA Registers |
|
|
Clock Synchronization Interface Registers
These registers are related to the clock synchronization building block of the blade. These registers are primarily used to:aa
SSelect system clock 1 or 2 from back plane
SSelect system or reference clock for DPLL input
SEnable reference clocks A and B to the backplane
SSelect recovered clock source
SDetermine programmable reference clock divider value
SDetermine reference clock pulse width
Note:aMotorola offers a device driver to access the clock synchronization interface. Instead of directly accessing the clock synchronization interface via the registers described in this section, it is strongly recommended to use this driver. Ask your local Motorola representative for details.a
The following clock synchronisation interface registers are available:
Table 28: Clock Synchronisation Interface Registers
Index Address | Register |
3016 | SPI Address register |
3116 | SPI Data register |
3216 | DPLL Input Select and Control register |
3316 | Reference Clock Divider register |
3416 | Lower Reference Clock Divder register |
3516 | Upper Reference clock Divider register |
3616 | Reference Clock Pulse Width register |
SPI Interface Registers
The used DPLL device ACS8525 from SEMTECH provides a Serial Peripheral Interface (SPI) which provides external access for device setup and controlling. Software that wishes to access the DPLL device has to first set the desired address in the SPI Address register followed by either a read or write access to the SPI data register. For details about configuring the DPLL device, refer to its data sheet.a
144 | PENT/ATCA???717 |
FPGA Registers | Maps and Registers |
|
|
DPLL Input Select and Control Register
Table 29: DPLL Input Select and Control Register
Bit | Description | Default | Access |
0 | Selects DPLL clock sourcea | 02 | r/w |
| 0: System clock |
|
|
| 1: Reference clock |
|
|
1 | Selects system clock source CLK1 or CLK2 | 02 | r/w |
| 0: CLK2 |
|
|
| 1: CLK1 |
|
|
2 | Unused | 02 | r |
3 | SPI interface is ready for access | 12 | r |
| 0: Wait |
|
|
| 1: SPI Ready |
|
|
4 | Enabling of 2 kHz system clock interrupt | 02 | r/w |
| 0: Disabled |
|
|
| 1: Enabled |
|
|
5 | 2 kHz system clock interrupt status | 02 | r |
| 0: Not active |
|
|
| 1: Interrupt pending |
|
|
6 | Clear 2 kHz system clock interrupt | ??? | r/w |
| Writing 0 clears the interrupt |
|
|
| Read accesses always return 0 |
|
|
7 | Reset signal for DPLL | 02 | r/w |
| 0: Reset asserted |
|
|
| 1: Normal operation |
|
|
Reference Clock Source Register
Table 30: Reference Clock Source Register
Bit | Description | Default | Access |
1..0 | Selects clock source for reference clock | 002 | r/w |
| 002: RCVD_CLK_0 |
|
|
| 012: RCVD_CLK_1 |
|
|
| 102: RCVD_CLK_2 |
|
|
| 112: RCVD_CLK_3 |
|
|
3..2 | Selects interrupt rate for interrupt | 002 | r/w |
| LCCB_INT_N clocked by 2 kHz system |
|
|
| clock reference |
|
|
002: 500 ??s
012: 1 ms
102: 10 ms
112: 1 s
PENT/ATCA???717 | 145 |
Maps and Registers | FPGA Registers |
|
|
Bit | Description | Default | Access |
4 | Enable reference clock CLK3_A | 02 | r/w |
| 0: Disabled |
|
|
| 1: Enabled |
|
|
5 | Enable reference clock CLK3_B | 02 | r/w |
| 0: Disabled |
|
|
| 1: Enabled |
|
|
6 | Selects if clock divider is bypassed | 12 | r/w |
| 0: Divide clock |
|
|
| 1: Bypass divider |
|
|
7 | Selection between pulse/clock on | 12 | r/w |
| REF_CLK output signal |
|
|
0: Pulse enabled
1: Pulse disabled
Reference Clock Divider Registers
The FPGA contains a clock divider which can be used in systems where the reference clock frequency does not match the recovered clock frequency. The clock divider is able to scale down a recovered clock frequency to the desired reference clock frequency. The scale down grade can be controlled via the upper and lower reference clock divider registers described in this section. Both registers correspond to the upper and lower divider of the division factor between recovered and reference clock. The division factor can be changed by software at any time. The new division factor becomes active with any new clock cycle avoiding spikes or truncated clock cycles. A plausibility check of register values is not required.a
Examples of recovered and reference clock frequencies and the corresponding division factors are given in the following table.a
Table 31: Examples of Division Factors Between Recovered and Reference Clock
Recovered Clock Frequency | Reference Clock Frequency | Division Factor |
8 KHz | 8 KHz | 1a |
1.544 MHz | 8 KHz | 193 |
2.048 MHz | 8 KHz | 256 |
19.44 MHZ | 8 KHz | 2430 |
38.88 MHz | 8 KHz | 4860 |
77.76 MHz | 8 KHz | 9720 |
19.44 MHz | 19.44 MHz | 1a |
146 | PENT/ATCA???717 |
FPGA Registers | Maps and Registers |
|
|
Recovered Clock Frequency | Reference Clock Frequency | Division Factor |
|
38.88 MHz | 19.44 MHz | 2 |
|
77.76 MHz | 19.44 MHz | 4 |
|
|
|
|
|
Note:aIf the division factor is 1, i.e. no clock division is done, the clock divider should be bypassed. This can be done via the reference clock source register.a
Lower Divider Register
Table 32: Lower Divider Register
Bit | Description | Default | Access |
7..0 | Divider lower byte | 0116 | r/w |
Upper Divider Register
Table 33: Upper Divider Register
Bit | Description | Default | Access |
7..0 | Divider upper byte | 0016 | r/w |
Reference Clock Pulse Width Register
This register determines the width of the reference clock high pulse in numbers of recovered clock cycles. The minimum pulse width is 150ns. If the clock divider is bypassed or the reference clock frequency is not 8 kHz, no pulse is generated.a
Table 34: Reference Clock Pulse Width Register
Bit | Description | Default | Access |
7..0 | Pulse width of reference clock signal | 0116 | r/w |
Serial PROM Update Register
The FPGA image is stored in two redundant PROMS.This register is used by upper layer software to control the upgrade of the FPGA image. Consult your local Motorola representative for the availability of new FPGA image versions and upgrade software.a
Version Register
This register indicates the version of the FPGA. The initial value is FE16a and is counted down with each new release.a
PENT/ATCA???717 | 147 |
Maps and Registers | FPGA Registers |
|
|
Table 35: Version Register
Bit | Description | Default | Access |
7..0 | FPGA version | FD16a(at the time of | r |
|
| writing this guide) |
|
Access Control Register
This register determines the current owner of the following interfaces:
SClock synchronisation building block interface
SEthernet switch management interface
SSPROM update interface
The current owner of each interface is either the IPMC or the host CPU.a
Only the current owner has write access to the corresponding registers. The non???proprietor has only read access.a
If the non???proprietor wants to become owner, it has to request ownership from the current owner. The current owner then has to grant ownership by inverting the bit corresponding to the interface.a
Table 36: Access Control Register
Bit | Description | Default | Access |
0 | Indicates the current owner of the clock | 02 | r/w |
| synchronisation building block interface |
|
|
| 0: Hosta |
|
|
| 1: IPMC |
|
|
1 | Indicates current owner of Ethernet switch | 12 | r/w |
| management interface |
|
|
| 0: Host |
|
|
| 1: IPMC |
|
|
2 | Indicates the current owner of the SPROM | 02 | r/w |
| update interface |
|
|
| 0: Host |
|
|
| 1: IPMC |
|
|
7..3 | Reserved | 000002 | r |
148 | PENT/ATCA???717 |
A
Troubleshooting
PENT/ATCA???717 | 149 |
Troubleshooting | Error List |
|
|
Error List
A typical ATCA system is highly sophisticated. This chapter can be taken as an error list for detecting erroneous system configurations and strange behaviors. It cannot replace a serious and sophisticated presales and postsales support during application development.
If it is not possible to fix a problem with the help of this chapter, contact your local sales representative or Field Application Engineer (FAE) for further support.
Problem | Possible Reason | Solution |
Blade does not work | Backplane voltage is too | Check that all backplane |
| low. | voltages are within their |
|
| specific ranges. |
|
| Check that power supply is |
|
| capable to drive the |
|
| respective loads. |
Blade does not start | No valid BIOS was found. | Make sure a valid BIOS |
|
| PROM is installed |
150 | PENT/ATCA???717 |
B
Battery Exchange
PENT/ATCA???717 | 151 |
Battery Exchange | Battery Exchange |
|
|
Battery Exchange
The blade contains an on???board battery. Its location is shown in the following figure.a
Figure 42: Location of On???board Battery
The battery provides data retention of seven years summing up all periods of actual data use. Motorola therefore assumes that there usually is no need to exchange the battery except, for example, in case of long???term spare part handling.aa
SBoard/System damage
Incorrect exchange of lithium batteries can result in a hazardous explosion.a Therefore, exchange the battery as described in this chapter.
152 | PENT/ATCA???717 |
Battery Exchange | Battery Exchange |
|
|
SData loss
If the battery does not provide enough power anymore, the RTC is initialized and the data in the NVRAM is lost.
Therefore, exchange the battery before seven years of actual battery use have elapsed.
SData loss
Exchanging the battery always results in data loss of the devices which use the battery as power backup.a
Therefore, back up affected data before exchanging the battery.
SData loss
If installing another battery type than is mounted at board delivery may cause data loss since other battery types may be specified for other environments or may have a shorter lifetime.a
Therefore, only use the same type of lithium battery as is already installed.
Exchange Procedure
1. Remove old battery
PCB and battery holder damage
Removing the battery with a screw driver may damage the PCB or the battery holder. To prevent this damage, do not use a screw driver to remove the battery from its holder.
2.Locate the ???+??? sign on the new battery. It indicates the positive terminal of the battery.a
3.Insert the battery into the blade???s battery holder in such a way that the ???+??? on top of the battery is face up
PENT/ATCA???717 | 153 |
Index
A
Accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
B
Backplane connectors . . . . . . . . . . . . . . . . . . . . . . . . 73
Boot device order . . . . . . . . . . . . . . . . . . 88 Main features . . . . . . . . . . . . . . . . . . . . . . 82 POST codes . . . . . . . . . . . . . . . . . . . . . . . 96 Restore default settings . . . . . . . . . 43,a91 Serial Console Redirection . . . . . . . . . . 84 Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Blade accessories . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Blade installation
Blade variants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Boot flashes
C
154 | PENT/ATCA???717 |
Main features . . . . . . . . . . . . . . . . . . . . . 124 Compact flash disk . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 COM ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110,a112 Configuration switches . . . . . . . . . . . . . . . . . . . . . . . . 42
D
Debug module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
E
Environmental Requirements . . . . . . . . . . . . . . . . . . 37 Ethernet switching unit
F
H
I
I/O address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
L
M
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PENT/ATCA???717 | 155 |
N
Non???maskable interrupts . . . . . . . . . . . . . . . . . . . . . 108
O
P
R
S
Serial interfaces . . . . . . . . . . . . . . . . . . . . . . . . 110,a112 SMBus Device Addresses . . . . . . . . . . . . . . . . . . . . 111 SMBus Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 South Bridge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Super I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
T
Critical hot spots . . . . . . . . . . . . . . . . . . . 38
Non???operating . . . . . . . . . . . . . . . . . . . . . 37
U
USB connectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
156 | PENT/ATCA???717 |
